D765

UPD765B NEC | Alldatasheet

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NEC Electronics Inc. uPD765A/uPD765B Single/Double Density Floppy-Disk Controller Description Features The uPD765A/B is an LSI floppy disk controller (FDC) chip which contains the circuitry and control functions for interfacing a processor to 4 floppy disk drives. It is capableof either IBM 3740singledensity format (FM), or IBM System 34 double density format (MFM) including double-sided recording. The uPD765A/B provides con- trol signals which simplify the design of an external phase-locked loop and write precompensation circuitry. The FDC simplifies and handles most of the burdens as- sociated with implementing a floppy disk interface. Hand-shaking signals are provided in the uPD765A/B which make DMA operation easy to incorporate with the aid of an external DMA controller chip, such as the uPD8257. The FDC will operate in eitherthe DMA or non- DMA mode. In the non-DMA mode the FDC generates interrupts to !he processor every time a data byte is to be transferred. In the DMA mode, the processor need only load the command into the FDC and all data transfers occur under control of the FDC and DMA controllers. There are 16 commands which the uPD765A/uPD765B will execute. Most of these commands require multiple 8-bit bytes to fully specify the operation which the processor wishes the FDC to perform. The following commands are available. Read Data Read Deleted Data Read ID Write Data Specify Write ID (Format Write) Read Diagnostic Write Deleted Data Scan Equal Seek Scan High or Equal Recalibrate Scan Low or Equal Sense Interrupt Status Version Sense Drive Status.

Ordering Information

Address mark detection circuitry is internal to the FDC which simplifies the phase-locked loop and read elec- tronics. The track stepping rate, head load time, and head unload time are user-programmable. The uPD765A/uPD765B offers additional features such as multi-track and multi-side read and write commands and single and double density capabilities. FM, MFM Control Variable recording length: 128,256, .8192 bytes/ sector IBM-compatible format (single- and double- sided, single- and double-density) Multi-sector and multi-track transfer capability Drive up to 4 floppy or micro floppydisk drives Data scan capability-will scan a single sector or an entire cylinder comparing byte-for-byte host memory and disk data Data transfers in DMA or non-DMA mode Parallel seek operations on up to four drives Compatible with uPD8080/85, uPD8086/88, V-series and uPD780 (Z80@) microprocessors Single-phase clock: 8 MHz maximum 3 +5V only Z80 is a registered trademark of the Zilog C orporation Pin Configuration Device Number uPD765AC2 uPD765B Package Type 40-pin plastic DIP 40-pin plastic DIP Max Freq. of Operation

8 MHz

No. Symbol

1 RESET

17 INDEX

Data or status select input Bidirectional data bus DMA request output DMA acknowledge input Terminal count input Index input 1 8 INT 1 9 CLK

20 GND

22 WINDOW

23 R DATA

24 SYNC

26 MFM

27 SIDE

30 WDATA

31, 32 PS0 P S 1

33 FLT/TRK0

34 WPRT/2SIDE

36 HDLD

37 FLTR/STEP

38 LCT/DIR

DC power ( +5 V) Pin Functions RESET (Reset) INT (Interrupt) The RESET input places the FDC in the idle state. It re- sets the output lines to the FDD to 0 (low), except PSO, 1 and WDATA (undefined), INT and DRQ also go low; DBO-7 goes to an input state. It does not affect SRT, HUT, or HLT in the Specify command. If the RDY input is held high during reset, the FDC will generate an inter- rupt within 1.024ms. To clear this interrupt, use the Sense Interrupt Status command. The INT output is FDC’s interrupt request. In Non-DMA mode, the signal is output for each byte. In DMA mode, it is output at the termination of a command operation. CLK (Clock) CLK is the input for the FDC’s single-phase, lTL-level squarewave clock: 8 MHz or 4 MHz. (Requires a pull-up resistor.) RD (Read Strobe) The RD input allows the transfer of data from the FDC to the data bus when low and either CS or DACK is asserted. WR (Write Strobe) The WR input allows the transfer of data to the FDC from the data bus when low. Disabled when CS is high. A0 (Data/Status Select) The A0 input selects the data register (A0 = 1) or status register (A0=O) contents to be accessed through the data bus. CS (Chip Select) The FDC is selected when CS is low, enabling RD and WR. DBo-DB7 (Data Bus) DBo-DB7 are a bidirectional 8-bit data bus. Disabled when CS is high. DRQ (DMA Request) The FDC asserts the DRQ output high to request a DMA transfer. DACK (DMA Acknowledge) When the DACK input is low, a DMA cycle is active and the controller is performing a DMA transfer. TC (Terminal Count) When theTC input is high, it indicates the termination of a DMA transfer. It terminates data transfer during Read/ Write/Scan commands in DMA or interrupt mode. INDEX (Index) The INDEX input goes high at the beginning of a disk track.

WCLK (Write Clock) The WCLK input sets the data write rate to the FDD. It is 500 kHz for FM, 1 MHz for MFM drives, for 8 MHz opera- tion of the FDC; 250kHz FM or 500 kHz MFM for 4 MHz FDC operation. This signal must be input for read and write cycles WCLK’s rising edge must be synchronized with CLK’s rising edge, except for the uPD765B. WINDOW (Read Data Window) The WINDOW input is generated by the phase-locked loop (PLL). It is used to sample data from the FDD and in distinguishing between clock and data bits in the FDC. RDATA (Read Data) The RDATA input is the read data from the FDD, containing clock and data bits. To avoid a deadlock situation, input RDATA and WINDOW together. WDATA (Write Data) WDATA is the serial clock and data output to the FDD. WE (Write Enable) The WE output enables write data into the FDD. SYNC (VCO Sync) The SYNC output inhibits the VCO in the PLL when low, enables it when high. MFM (MFM Mode) The MFM output shows the VCO’s operation mode. It is high for MFM, low for FM. SIDE (Head Select) Head 1 is selected when the SIDE output is 1 (high), head 0 is selected when SIDE is 0 (low). US0 US1 (Unit Select 0,1) The US0 and US1 outputs select up to 4 floppy disk drive units using an external decoder. PS0, PS1 (Preshift 0,1) The PS0 and PS1 outputs are the write precompensation request signals for MFM mode. They determine early, late, and normal times for WDATA shifting. READY (Ready) The READY input indicates that the FDD is ready to re- ceive data. HDLD (Head Load) The HDLD output is the command which causes the read/write head in the FDD to contact the diskette. FLT/TRKO (Fault/Track 0) In the read/write mode, the FLT input detects FDD fault conditions. In the seek mode, TRKO indicates track 0 head position. WPRT/2SlDE (Write Protect/Two Side) In the read/write mode, the WPRT input senses write protected status (at the drive or media.) In the seek mode, 2 SIDE senses two-sided media. FLTR/STEP (Fault Reset/Step) In the read/write mode, the FLTR output resets the fault flip-flop in the FDD. In the seek mode, STEP outputs step pulses to move the head to another cylinder. A fault reset pulse is issued at the beginning or each Read or Write command prior to the HDLD signal. LCT/DlR (Low Current/Direction) In the read/write mode, the LCT output indicates that the R/W head is positioned at cylinder 42 or greater. In the seek mode, the DIR output determines the direction the head will move in when it receives a step pulse. If DIR is 0, seeks are performed in the outward direction; DIR is 1, seeks are performed in the inward direction. RWlSEEK (Read/Write/Seek) The RW/SEEK output specifies the read/write mode when low, and the seek mode when high. GND (Ground) Ground. Vcc(+5v) +5 V power supply. 5-5

TA = 250C Power supply voltage, VCC -0 5 to +7v Input voltage, V1 -0.5 to +7v Output voltage, VO -0.510 +7v Operating temperature, TOpT - 1OOC to +7ooc Storage temperature, TSTG -65°C to +150°C Comment: Exposing the device to stresses above those listed in the Absolute Maximum Ratings could cause permanent damage. The device should not be operated under conditions outside the limits described in the operational sections of this specification. Exposure to absolute maximum rating condi- tions for extended periods may affect device reliability. DC Characteristics Th= -1O’C to +70°C,Vcc = +5V%lO%__ Limits Teal Parameter Symbol Min Typ Max Unit Conditions Input voltage -0.5 v IOW Input voltage VIH 2.0 5 v high Output voltage 0.45 V low Voltage 2.4 Input voltage 0.5 low (CLK + WCLK) Input voltage high (CLK + WCLK) Supply current kc) kc V 0.65 V v 150 140 Input load current high Input load -10 current low Output leakage current high Output leakage current low -10 Capacitance Parameter Input clock Limits Symbol Min Typ M a x Unit 20 pF Test Conditions (Note 1) Input capacitance 10 pF (Note 1) output COUT 20 pF capacitance Note: (1) All pinsexcept pin under test tied to AC ground. [Note 1) 5-6

DIFFERENCES BETWEEN,uPD765A AND uP D765B The uPD765B is a functionally enhanced version of the uPD765A. Differences are explained below. Overrun Bit [OR] In uPD765A, when executing a read- or write-type command (except READ ID and SCAN types), the result status OR bit is not set if there is an overrun on the final byte of a sector. An improvement in the uPD765B allows it to set the OR bit in any situation. DRQ Reset When an overrun occurs, the uPD765A needs DACK input to reset DRQ. If DACK is not available, an external DMA controller continues to operate even after the FDC enters the R-Phase (Result Phase), and stored result status may be transferred accidentally as ordinary data. On the other hand, the uPD765B resets DRQ auto- matically just before the R-Phaseentry and independent of the DACK input. See AC Characteristics for DRQ reset timing. Clock Synchronization The uPD765B does not require synchronization between the CLK and WCLK inputs. Version Command The Version command distinguishes the uPD765B from other devices. The ST0 response to the Version command is: Part No. ST0 Value uPD765A 80H uPD765B 90H 5-7

= -10 to V Parameter Symbol Min Typ Max Unit Conditions Clock period 120 125 500 CLK 240 250 ns CLK Parameter Symbol Min Typ Max Conditions WCLK cycle time MFM = 0 MFM = 1 Clock active (high, low) WCLK active time 250 350 ns Note 4 CLK WCLK ns delay only Clock rise time Clock fall 20 ns WCLK. RDATA and 20 ns WINDOW time WCLK, and 20 ns WINDOW fall time time DACK 0 setup time to RO CS, DACK 0 ns hold time from Preshift time from WCLK WCLK delav ns 20 100 ns width Data access from 200 140 = 100 20 100 ns DB to float delay 10 85 ns time from CS. OACK AW 0 setup time to WR I RDATA time 40 ns Window cycle time MFM=O OACK hold time ns 1 Window hold time 15 n s from RDATA width 200 ns Data setup time to 100 ns Window setup time to RDATA 15 n s setup time CLK to SEEK Notes 4, 5 SEEK setup time to DIR Data hold time from 0 ns time from ns Non-DMA mode + 135 Direction setup time to step hold time from step t 5.0 INT delay time from + 135 cycle time ns (Note 4) DACK 140 ns delav DRQ DACK 200 n s delay ns (Note 4) DACK width AA ns + 15 Step active time 6 7 8 Notes 4.5 (high) Step cycle time

33 Note 2Note 2

8.0 10 time (high) Write data width hold time CLK after seek Notes 3.4. SEEK hold time CLK from DIR Notes 4, 5 DIR hold time after step Index pulse TC width Reset width DRQ INT 60 7 7 response time INT DACK ineffective only

AC Characteristics (cont) Parameter Symbol Min Typ (1) Max Unit Conditions delay from DRQ 800 ns S-MHz CLK Note 4 delay from DRQ 250 ns response time from DRQ Notes: (1) Typical values for TA = 25°C and nominal supply voltage. (2) Under software controLThe range is from 1ms to 16ms at 8-Mhz clock period, and 2 ms to 32 ms at 4-Mhz clock period. (3) When one device is executing a SEEK operation, SENSE DRIVE STATUS is executed on another device. (4) Double these values for a 4-MHZ clock period (5) Thedrivesiderating has a variance of ~5Ons from the minimum value. liming Waveforms Processor Read Operation Processor Write Operation CS, DACK

liming Waveforms (Cont) Data Input Waveform for AC Test (Except CLK, 2.4 0.45 Clock (WCLK, Waveform for AC Test Output Clock Operation FDD Write Operation Write Enable 0 or Write Data Normal 0 0 Early Invalid Seek Operation step Overrun Operation Only) FLJ Reset I Fault Reset FDD Read Operation Terminal Count I Reset I 5-10

the signals RD, WR, and A0 is shown in table 1. Table 1. Status/Data Register Addressing Table 2. Main Status Register DB4 CB A Read or Write command is in orocess. (FDC Busy) FDC will not accept any other command. the processor to data register. transferred on the data bus. See figure 1. Figure 1. DIO and RQM

Table 3. Status Register Identification was not successfully completed. (Seek End) mand, this flag IS set lo 1 (high). time interval. this flaa is set. D3 Not used. This bit i s alwavs 0 (low). Table 3. Status Register Identification (cont) During execution of the Read ID command. an error, then this flag IS set. found, then this flag is set.

Table 3. Status Register Identification (cont) Command Symbol Description (A0=0) or data register (A0= 1). (Write Protected) write protected signal from the FDD. track 0 signal from the FDD. two-side signal from the FDD. unit select 1 signal to the FDD. unit select 0 signal to the FDD.

to all drives (FH=1ms, EH=2ms, etc.). ing the result phase after command execution. Table 4. Instruction Set (Notes 1,2) are compared against header on floppy disk. (2) A0 should equal 1 for all operations. (3) X = Don’t care, usually made to equal 0.

Table 4. Instruction Set (Notes 1,2) (cont)

1 Command codes

data fields from index hole to EDT.

Table 4. Set (Notes instruction Code Remarks Read Command W0 MF 0 0 1 0 Command codes W X X X X X HD US, Executron The first correct ID on the cylinder stored data register. Status information after command execution ST1 ST2 C Sector ID read during executron phase from floppy H N ID Command W MF 1 1 w X X X X X HD US, W N Bytes/sector WS C Sectors/track W GPL Gap3 W byte FDC formats an entire track. Status information after command execution ST1 ST2 C In this case, the ID has no H R N Scan Equal Command W MT SK 1 0 0 0 1 Command codes W X X X X X US, W C Sector command execution W H w W W EOT w GPL W STQ Execution Data between the and main Result ST1 Status after command execution ST2 C H Sector ID information after command fl N Note: (1) Symbols used this table are described at the end of this section should equal 1 for all operations. (3) X Don’t care, usually made to equal 0. 5-16

Table 4. Instruction Set (Notes