D7220D

UPD7220A NEC | Alldatasheet

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NEC Electronics Inc. Graphics Display Controller Description Features The uPD7220A high-pertormance graphics display Microprocessor interface controller (HGDC) is an intelligent microprocessor © — DMA transfers with 8257- or 8237-type peripheral designed to be the heart of a high-perfor- controllers mance raster scan computer graphics and character. — FIFO command buffering display system. Positioned between the video display C1 Display memory interface memory and the microprocessor bus, the HGDC — — Up to 256K words of 16-bits performs the tasks needed to generate the raster © — Read-modify-write (RMW) display memory display and’manage the display memory. Processor cycles as fast as 500 ns software overhead is minimized by the HGDC'ssophis- | — Dynamic RAM refresh cycles for nonaccessed 3 ticated instruction set, graphics figure drawing, and memory DMA transfer capabilities. The display memory sup- ©. Light pen input ported by the HGDC can be configured in any number 1 Drawing hold input of formats and sizes up to 256K 16-bit words. The O External video synchronization mode display can be zoomed and panned, while partitioned 0 Graphic mode screen areas can be independently scrolled. With its _ — Four megabit, bit-mapped display memory light pen input and multiple controller capability, the 1 Character mode HGDC is ideal for advanced computer graphics — 8K character code and attributes display applications. memory For a more detailed description of the HGDC's o Mee arenes ane character mode operation, please refer to the 7220/7220A design 74 megapixel ifall graphics manuals. 0 Graphics capabilities — Figure drawing of lines, arc/circles, rectangles, System Considerations and graphics characters in 500 ns per pixel ‘The HGDC is designed to work withageneral purpose — Display 1024-by-1024 pixels with 4 planes of microprocessor to implement a high-performance color or grayscale computer graphics system. Through the division of — Two independently scrollable areas labor established by the HGDC’s design, each of the CI Character capabilities system components is used to the maximum extent | — Auto cursor advanced through a six-level hierarchy of simultaneous tasks. At_ —- — Four independently scrollable areas the lowest level, the HGDC generates the basic video © — Programmable cursor height raster timing, including sync and blanking signals. — Characters per row: up to 256 Partitioning areas on the screen and zooming are also. _ — Character rows per screen: up to 100 accomplished at this level. At the next level, video Video display format display memory is modified during the figure drawing — Zoom magnification factors of 1 to 16 operations and data moves. Third, display memory — Panning addresses are calculated pixel by pixel as drawing © — Command-settable video raster parameters progresses. Outside the HGDC at the next level, (NMOS technology preliminary calculations are done to prepare drawing —_) Single +5 V power supply parameters. At the fifth level, the picture must be 1 DMA capability represented as a list of graphics figures drawable by — Bytes or word transfers the HGDC. Finally, this representation must be — 4 clock periods per byte transferred manipulated, stored, and communicated. By handling 0 On-chip pull-up resistor for VSYNC/EXT, HSYNC the first three levels, the HGDC takes care ofthe high- and DACK, and a pull-down resistor for LPEN/DH. speed and repetitive tasks required to implement a graphics system. NeoELo8e 3-259

Ordering Information Pin Identification Part Package Max Frequency Pin Number Type at Operation’ a. ‘Symbol Function wPore20a) ___AO-pin ceramic OP MH 2xWCLK Clock input wPOrz2OAD ___AO-pin ceramic OP MHZ DBIN Display memory read input flag wPore2ond-2 __AO-pin ceramic OP MH HSYNG Horizontal video sync output

4 V/EXT SYNC Vertical video sync output or external

Pin Configuration VSYNC input

5 BLANK —__CRT blanking output

eek 1 40 Veo 6 ALE ‘Address latch enable output DanC oo Air 2 Nessie eet neve 3 36 Ate 7 Ra DMA request output vext sync 4 27D ADs 8 DACK DMA acknowiedge input eLank 5 26 Ada —_—__ Err reer nede ssBapie 9 RD Read strobe input or microprocessor Back e sap ann 10 WR Write stobe input for microprocessor MOGs < separ interface wade 8 a1aoo " Ay ‘Address select input for microprocessor Aot11 & sof Ade interface Bo C12 2a Aor De DEEP blavectional Gab bis OST RIGD

1219 DByyDB; Bidirectional data bus to host micro-

oaiqlia as ane eB processor ; Be C14 27 DADs a bB3 15 26 DADs 20 GND Ground oB4 C16 25 ADs a LPEN/DH Light pen detect input drawing hold oasQ17 24f Ade input bes C18 23 ADt 22:34 ADp-AD: Address data lines to displ reeds ape Dp-ADi2 dress data lies to display memory ono G20 31 EILPENOE 35-37 AD ig ADIs Utilization varies with mode of sonoma operation BAG Utilization varies with mode of sn Litilizati operation Character Mode Pin Utilization a Tee

2 Utilization varies with mode of

No Symbol Function 0 Veo +5. +10% power supply

35.37 AD ADs Line counter bits 0 to 2 outputs

38 ADis_——_—_Line counter bit3 output

3 AD Cursor output and fine counter bit 4

Mixed Mode Pin Utilization Pin No Symbol Function 35-37 AD rADi5 ‘Address and data bits 13 to 15 Eo Ate ‘Attribute blink and clear line counter output x Ay Cursor and bit-map area flag output 3-260

° HsYNC Dae | et 3 aK PACK © © BLANK Microprocessor ° ‘Status CALE ao Rogister and Generator DBIN RDO Data Read wro Register Zoom and Pan Controller Fir $ Butter 3 3 1ex9 F

2 Drawing

z Command Processor ; with ast contro! ROM pisplay Memory [2 4-16

1284 Gontroller with © AD-15

Counter © AD-14 Line Counter © AD-13 RMW Data Path Parameter nam K-28) svoro 1x8 ss Light Pen GND Oe Degiiten and ° LPEN XWCLK 0 | “Rogister 2xWeik ai 3-261