D71051C

UPD71051 NEC | Alldatasheet

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i y E: C . vPD71051 NEC Electronics Inc. Serial Control Unit Description Ordering Information The #PD71051 serial control unit isa CMOS USART Part Number Clock (mz) Package designed to provide serial data communications in ,ppvi0s1c8=~=~*~*~*~S*~<CS« pI past DIP microcomputer systems. The CPU uses it as a peri ~~ —"~".4g. i? 0 pheral I/O device and programs it to communicate in —§ synchronous or asynchronous serial data transmission GBB 8 44-pin plastic QFP Protocols, including IBM bisync. GB-10 10 The USART receives serial data streams and converts Le 8 26-pin PLCC them into parallel data characters for the CPU. While Go 0 receiving serial data, the USART can also accept parallel data from the CPU, convert it to serial, and pin Configurations transmit the data. The USART signals the CPU when it has received or transmitted a character and requires 7 service. The CPU may read complete USART status 72-Pin Plastic DIP data at any time. oft Bp o oz ab Features RROATAC] 3 asp veo C1 Synchronous operation ods 2 One or two SYNC characters os § abars Internal/external synchronization od? & 2hos Automatic SYNC character insertion _ oe & aprsser C Asynchronous operation vemqs wpa Clock rate: (baud rate) adn Brew Ea x1, x16, or x64 codn wes Send stop bits: 1, 1.5, or 2 bits fod 1a 16 5 syncronx Break transmission rumor C4 15) teaoy Automatic break detection women Valid start bit detection C Baud rate: DC - 240 kbit/s at x1 clock O Full duplex, double-buffered transmitter/receiver O Error detection: parity, overrun, and framing

0 Five- to eight-bit characters

O Compatible with standard microcomputers O Functionally equivalent to (except standby mode) and can replace the uPD8251AF C1 CMOS technology O Single +5 V + 10% power supply Ci Industrial temperature range —40 to +85°C C 28-pin plastic DIP or PLCC or 44-pin plastic QFP 0 8 MHz and 10 MHz 5¢é-I 80011 (NECEL-coo130)

a Pin Configurations (cont) Pin Identification le tate! Sym Funct 44-Pin Plastic QFP Symbol) TxDATA Transmit data output x CLK Clock input $95 3 RESET Reset input z 3 put ° 2 fs gibS Estates ish Data set ready input AAARASAeaad as Request to send output SRERIOERUREEAEDEEIDE om Data terminal ready output a a = ne COI 33 PTT ne AXCLR Receiver clock input RRCLK Receiver clock inpue we CTT fo ve Voo +5 V power supply xara CI Er wa o ———Eoe cu C4 Lr reer} = P7-Do Data bus reser CO 3 or ic Internally connected (00 not connect ne COO yeort0st E15 we any signal to an IC pin) oan CI foo RxDATA Receive data input ms co Fo 9s Le EIEN 0717 Enis om Co Fr 1 Su Ground xe CO fo we TKCIK Transmitter clock input nc COT Se By pT we WR Write strobe input TITUU OT io Chip select input H H H H A H H H A H H cD Control or data input g é 3 ssesseee 80 Read strobe input 3° RXADY Receiver ready output soos] TARDY Transmitter ready output ‘SYNC/BRK Synchronization/Break input/output 28-Pin Plastic Leaded Chip Carrier (PLCC) ae ceartosendinpst ——OSOS™*~SSS crs Clear tosendinpuy < TxEMP Transmitter empty output Re & Bud NC Not connected eeERE SE TS Pin Functions Voo (26 ye 5 Tem Dy-Dp [Data Bus] Do Cl 27 wh os 01 146 [ SYNC/BRK D7-Do are an 8-bit, 3-state, bidirectional data bus. The p21 © pPp71051 15 [1 TeRDY bus transfers data by connecting to the CPU data bus. 232 +4 5 rurvy rxpata C3 13 PRD RESET [Reset] cro Qa npcd weoneakt A high level to the RESET input resets the »PD71051 Doo and puts it in an idle state. It performs no operations in 6aé 5G gs the idle state. The uPD71051 enters standby mode IE when this signal falls from a high level to a low level. smexa| — Standby mode is released when the CPU writes a mode byte to the uPD71051. The reset pulse width must beat least 6 tcyx cycles and the clock must be enabled. 50-2

CLK [Clock] DSR [Data Set Ready] This clock input produces internal timing for the | DSRisageneral-purpose input pin that can be used for uPD71051. The clock frequency should be at least 30 moderii control. The status of this pin can be determined times the transmitter or receiver clock input frequency __ by reading bit 7 of the status byte. (TxCLK, RxCLK) in sync or async mode with the X1 clock. This assures stable operation. The clock OTR [Data Terminal Ready] frequency must be more than 4.5 times the TXCLK or == DTR is a general-purpose output pin that can be used RXCLK in async mode using x16 or x64 clock mode. fo, modem control. The state of this pin can be SE ons controlled by writing bit 1 of the command byte. If bit 1 CS [Chip Select] =0, then DTR = 1. If bit 1 = 1, then DTR = 0. The CS input selects the uPD71051. The u4PD7 1051 is selected by setting CS=0.When CS=1,thezPD71051 RTS [Request to Send] is not selected, the data bus (D7-Do) is in the high =>— iS ATS is a general-purpose output pin that can be used impedance state, and the RD and We Signals ae f4¢ modem control. The status of this pin can be ignored. controlled by writing bit 5 of the command byte. If bitS BD [Read Strobe] =1, then RTS = 0. If bit 5 = 0, then RTS = 1. The RD input is low when reading data or status CTS [Clear to Send] information from the uPD71051 The CTS input controls data transmission. The We wer uPD71051 is able to transmit serial data when CTS = 0 WR [Write Strobe} and the command byte sets TxEN = 1. If CTS is set The WR inputis low when writing dataoracontrolbyte equal to 1 during transmission, the sending operation to the wPD71051. stops after sending all currently written data and the _ TXxDATA pin goes high. C/D [Control or Data] Ea The G/B inputdetermines the data type when accessing TXDATA [Transmit Data] the #PD71051. When C/D = 1, the data is a control The uPD71051 sends serial data over the TxDATA byte (table 1) or status. When C/D = 0, the data is output. character data. This pin is normally connected to the least significant bit (Ag) of the CPU address bus. TxRDY [Transmitter Ready] The TxRDY output tells the CPU that the transmit data Table 1 Control Signals and Operations nu tfer in the uPD71051 is empty; that is, that new c m WR ca ePOTIOS1 CPU Operation transmit data can be written. This signal is masked by Receive data butter the TXxEN bit of the command byte and by the CTS oo 1 0 D> Read recewe data input. It can be used as an interrupt signal to request ardbus data from the CPU Status register oa bi o 014 Read status The status of TxRDY can be determined by reading bit A 0 of the status byte. This allows the uPD71051 to be TTT nc OO poolied. Note _that TxRDY of the status byte is not o 10 0 Sed Wate wansmit data masked by CTS or TxEN. _Mansimit data bulter TX RDY is cleared to 0 by the falling edge of WR when Sata bus the CPU writes transmit data to the zPD71051. Data in Oo nt Seri waite contra byte the transmit data buffer that has not been sent is —_Sontrot nyievegistey destroyed if transmit data is written while TxRDY = 0. oot lok Data bus None High impedance le a Data bus None High umpevance $O-3

TxEMP [Transmitter Empty] determine the status of RXRDY by reading bit 1 of the . status byte and use the wPD71051 ina polling applica- ‘The 4PD71051 reduces CPU overhead by using @ jon, RxRDY becomes 0 when the CPU reads the double buffer; the transmit data buffer (second buffer) receive data, and the transmit buffer (first buffer) in the transmitter. ° When the CPU writes transmitdata tothe transmitdata Unless the CPU reads the receive data (after RxRDY = buffer (second buffer), the #PD71051 sends data by _ 1 isset) before thenext single characteris received and transferring the contents of the second buffer to the transferred to the receive buffer, an overrun error first buffer, after transmitting the contents of the first. occurs, and the OVE status bit is set. The unread data buffer. in the receive data buffer is overwritten by newly This empties the second buffer and TxRDY is set to 1 transferred data and lost. The TxEMP output becomes 1whenthecontentsof the RxRDYissettoOin the receive disable state. This state first buffer are sent and the second buffer is empty. is set by changing the RxEN bit to 0 through the Thus, TxEMP=1 shows that both butfers are empty.In command byte. After RxEN is set to 1 (making receiving half-duplex operation, you can determine when to possible), RxRDY becomes 1 whenever new characters change from sending to receiving by testing TxEMP=1. _ are received and transferred to the receive data buffer. When TxEMP = 1 occurs in async mode, the TxDATA 7 pin goes high. When the CPU writes transmit data, SYNC/BRK [Synchronization/Break] TxEMP is set to 0 and data transmission resumes. The SYNC pin detects synchronization characters in _ sync mode. The SYNC mode byte selects internal or When he on occurs syne mode wpD7 105) external SYNC detection. The SYNC pin becomes an register ‘and ais them through. the TRDATA pin. output when internal synchronization is set, and an TOMP ie set to 0 and resumes sending data after mPutwhen external synchronization is set. sending (one or two) SYNC characters and the CPU The SYNC output goes high when the wPD71051 writes new transmit data to the zPD71051 detects a SYNC character in internal synchronization. When two SYNC characters are used, SYNC goes high TxCLK [Transmitter Clock] when the last bit of the two consecutive SYNC —_ characters is detected. You can read the status of the The CTR int en et oe vavomitted SYNC signal in bit 6 of the status byte. Both the SYNC Sea aT Ineyne mode. In async mn amd status are set to 0 by a read status operation mode, set TxCLK to 1, 16, or 64 times the transmission In external synchronization, in order for the external rate. Serial data from TXDATA issentatthefallingedge circuit to detectsynchronization, a high level of atleast of TxCLK. one period of RXCLK must be input to the SYNC pin. ; When the zPD71051 detects the high level, it begins to an aebied on 9200 baud i Sy mone means receive data, starting at the rising edge of the next ed XOLK is 19. eK or. aud in async — RXCLK. The high level input may be removed when mode can represent a TXCLK of: synchronization is released. x Ce eet kHz The BRK output is used only in async mode and shows wed clock = 153.6 KHZ the detection of a break state. BRK goes high when a : low level signal is input to the RxDATA pin for two character bit lengths (including the start, stop, and RxDATA [Receive Data] parity bits). As with SYNC, you can read the status of ‘The uPD71051 receivesserialdatathroughtheRxDATA —_ BAK inbit6 of the status byte. BRK is not cleared by the input. read operation The set BRK signal is cleared when the RxDATA pin RxRDY [Receiver Ready] returns to high level, or when the 4PD71051 is reset by The RxRDY output becomes 1 when the 4PD71051 hardware or software. The SYNC/BRK pin goes low on receives one character of data and transfers that data _reset, regardless of previous mode. Figure 1 shows the tothe receive data buffer; that is, when the receivedata _ break state and BRK signal. can be read. This signal can be used as an interrupt signal for a data read request to the CPU. You can SCn4

Figure 1. Break Status and Break Signal wa k— tS) ex: aS manta Oe released and it waits for a mode byte to set the mode. reading, writing, and error handling during operations.

a Transmit Data Buffer Absolute Maximum Ratings Ta= 425°C the CPU that the transmitter will convert to serial data Power supply voltage, oo =05t0 +700 and output from the TxDATA pin. When the CPU writes Input voltage, V) =05 to Vop + 03V transmit Gata to the HPOTIOSY, the pPD71051 stores Ouiput voltage. Vo — 95 to Vp +030 lata in the transmit dat utfer. e transmit data 0 to BSC butter transfers the data to the transmitter, which Operating temperature, Topr_ AC 10 485°C sends the data from the TxDATA pin. Storage temperature, Tst¢ 65°C to +150°C Power dissipation, PDwax 10 Control Register Comment: Exposing the device to stresses above those listed in i Absolute Maximum Ratings could cause permanent damage. The This register stores the mode and the command bytes. device is not meant to be operated under conditions outside the limits described in the operational sections of this specification. Control Logic Exposure to absolute maximum rating conditions for extended The control logic sends control signals to the internal PeNo#s may allect device reliability blocks and controls the operation of the wPD71051 — , " " apacitance based on internal and external signals. Ta = +25°C, Voo =0V Synchronous Character Register _Himits Test rameter ibol This register stores one or two SYNC characters used Paremeter___Srmvbol iuin_Mox_Unt_Conerms _ in sync mode. During transmission, the SYNC input capacitance G 10 oF [Somoteived pins characters stored in this register are output from the —jjq capacitance. «0 «20—~pF__ returned toOV TxDATA pin when the CPU does not send a new WOcapactance Go 7) Ft character and TxEMP status is set. During receiving, . synchronization is established when the characters DC Characteristics received and the SYNC characters stored in this TAT “40°C 10 +85°C, Voo = *+8V + 10% register are the same. Limits qT itt Parameter___Symbol_Min_Typ_Max__Unit_Test Conditions _ ransmitter input voitage Vn 22 Voot03 V The contents of the transmit data bufferaretransferred high to the transmitter, converted from parallel toserial,and — Input voltage Vi. 05 08 OV ‘output from the TxDATA pin. The transmitter adds low start, stop, and parity bits. Output voltage VoH 0.7 x Yop Vo tox = ~400 yA ig! Receiver Output voltage Vor 04 V Wy=25mA The receiverconverts serial datainputfromtheRxDATA pin into parallel data and transfers the parallel data to Input leakage — 'L1H 10 uA -Vi=Noo the receive data buffer, allowing the CPUto read it. “went high input leakage | “10 uA W=0V The receiver detects SYNC characters and checks —currentiow “en parity bits in sync mode. It detects the start and stop Giiputieaxage lon SCC A= bits, and checks parity in the async mode. ote lon 0 ok Yom a0 Inasyne mode, receiving does not begin (thestart bitis Output leakage Ito. —10 yA Vo=0V not detected) until one effective stop bit (high level) is current low input to the RXDATA pin and Receive Enable (RXEN= Supply current 1) is set after setting up the mode. wP071051 pps 10 mA Normal mode ‘oe 50 100 yA Stand-by mode Modem Control 107105710 Ippr 40 mA Normal mode This block controls the CTS, RTS, DSR, and OTR oe 25D aA Stand-by mode modem interface pins. The RTS, DSA, and DTR pins_—_ << can also be used as general-purpose I/O pins. 5C-6

N; E Cc »PD71051 AC Characteristics Ta = ~40°C to +85°C, Vop = 5 V 410%

8 MAz Limits 10 Miz Limits

Parameter Symbol Min Max Min Max Unit__Test Conditions Read Cycle Address setup to RD | tgaR 0 0 ns ts. c/D Address hold fromRDt = stypa, 0 7 0 ns tS, cid AD low level width tra 150 7 5 ns Data delay fromRD! toRO ° 120 5 ns Cy = 150 pF Data float tromADT Strap 10 80 10 65 ns Port (OSA, CTS) set-uptoRD! __tgpa 20 20 tovk Write Cycle Address setup to WR } tsaw 0 0 ns ts, c/D Address hold trom WA T twa 0 0 ns ts. cid WR low level width twwe 150 95 ns Data setup to WR f tspw 80 80 ns Data hold from WR f tawo 0 0 tovk Port (OTR, RTS), delay from WAT — towe 8 8 tevk Write recovery time tav 6 6 tek Mode initialize 8 8 tovk sync mode 16 16 tera Sync mode Serial Transfer Timing CLK cycle time Tore Ed oC 100 0c ns CLK high level width KKH 50 Ed ns CLK low level width tkKL % 25 ns CLK rise time KA 5 20 5 20 ns CLK fall time tke 5 20 5 20 ns TxDATA delay from TxCLK torkrp 08 05 us Transmitter input clock pulse {TKTKL. 12 12 tevk ‘1xBR (Note 1) width low level Ty BR Transmitter input clock pulse trKTKH 15 15 tovk 1xBR width high level ee ee ee eee Transmitter input clock thx 0c 240 oC 300 KHZ 1xBR frequency Wote 2) oC 1836 oC 1920 kHz 16xBR 0c 1596 0c 1920 kHz 64xBR Receiver input clock pulse TRKRKL 12 12 tevk 1xBR width tow level ee ee Receiver input clock pulse TRKRKH 5 18 tork 1x8R width high level 0 ee tok 1 KBR se-T

p»PD71051 N: FE Cc ee AC Characteristics (cont)

8 Miz Limits 10 Miz Limits

Parameter Symbol Min Max > Min Max Unit Test Conditions Serial Transfer Timing (cnt) Receiver input clock frequency fax 0 240 0G 300 ke _1x8R (Note2) 0c 1596 oC 1920 wie GR pc 1536 0c 1920 kHz oer AXDATA set-up to Sampling pulse tsnosP 1 1 a RXDATA hold from sampling tHSPRO 1 1 ws OO pulse TREMP delay time (TxDATA) ____torxep tev TxRDY delay time (TxRDY 1) ‘ova OO TxRDY delay time (TXRDY!) a ns a AXRDY delay time (RxRDYT) a kK RxADY delay time (RXRDY1) toraxa a SYNC output delay time toRKSY a (for internal sync) SYNC input setuptime = tssyme— 8 ‘ovk (for external sync) RESET pulse width 6 6 Tork Notes: (1) BR= Baud rate (2) 1xBR: fy or fax S 1/30 tei K, 16x, 64xBR: frK OF fr S 1/4 Stork (3) System CLK is needed during reset operation (4) Status update can have a maximum delay of 28 tcyx from the event effecting the status Timing Waveforms Write Data Cycle Read Data Cycle , jl ‘ gE a ae | Nea | me ne a oes ome a lowe. | Le sumer | . Bes

Timing Waveforms (cont) Transmitter Clock and TxDATA . - rer. ee, ~ | HETR |) BA) co betoroe4 tore term, arog, THOLK (16 x BR} a veel torxto-»} = TxDATA x x Receiver Clock and RxDATA Timing Cc = a FRCLK (1 x BR) f stovebael feel tc Stow Pune mata —\\, sat on ‘C= _— omeKR. ama 6B breerriaeal cycle Gia to Cyoe { Sternfe-el fools re Sampling f Yr RROATA \\ Start Bit ‘tat Date Bit xX AC Test Input Write Recovery Time aay 22v 22v wa rr ae oasy o8v osv -—_ sour ain Clock ton tee - > fotknee} on. cux tore 200704 5E-9-

characters to be sent after the mode byte; set C/D = 1. are written. Figure 3 shows this operation sequence. Figure 2. System Connection | ge [1) This is done with C/B = 0. Others are operated with C/5 ~ 1.

N. FE C vPD71051 Mode Register Figure 4. Mode Byte for Setting Asynchronous Mode When the ¢PD71051 is in standby mode, writing a cb mode byte to it will release standby mode. Figure 4 “spasaaeie shows the mode byte format for designating async SO mode. Figure 5 shows the mode byte format for a designating sync mode. Bits 0 and 1 must be 00 to ——ferfeo] secdnwe designate sync mode. Async mode is designated by all Pep wes other combinations of bits 0 and 1. Epc] The P1, PO and L1, LO bits are common to both modes. Bits P1 and PO (parity) control the generation and Se checking (sending and receiving) functions. These —— parity bit functions do not operate when PO = 0. When | P1, PO = 01, the 4PD71051 generates and checks odd cs parity. When P1, PO= 11, it generates and checks even Parity. { P2] Po Parity Generate/Check | Bits L1 and LO set the number of bits per character (n). ER} B= Additional bits such as parity bits are not included in Peery this number. Given n bits, the uPD71051 receives the | lower n bits of the 8-bit data written by the CPU. The {sri]sto] Transmit Stop Ons | upper bits (8 -n) of data that the CPU reads from the [ro fo [vse tesa | uPD71051 are set to zero. ER} —=— The ST1, STO and B1, BO bits are used in async mode. a The ST1 and STO bits determine the number of stop weaoatcare bits added by the zPD71051 during transmission. Soom The B1 and BO bits determine the relationship between Ea the baud rates far sending and receiving, and the ure 5._ Mode byte for Setting Synchronous Mode clocks TxCLK and AXxCLK. B1 and BO select a multi- = plication rate of 1, 16, or 64 for the frequency of the pss 43245 sending and receiving clock relative to the baud rate. | GeclexsencforTro] [oT >To] Multiplication by 1 isnot normally used in async mode. | i Note that the data and clock must be synchronizedon | [urTeo] the sending and receiving sides when multiplication by — | EE} —=— | Vis used. i The SSC and EXSYNC bits are used in sync mode. The eh SSC bit determines the number of SYNC characters. aaa eee) SSC = 1 designates one SYNC character. SSC = 0 eto] —woreny ——] designates two SYNC characters. The number of [o[s| oearany ] | SYNC characters determined by the SSC bit are cs a written to the uPD71051 immediately after writing the | | mode byte. fexsync] Sync Detect] . | internat (Output _| The EXSYNC bit determines whether sync detection | Sa during receiving operations is internal or external. EXSYNC = 1 selects external sync detection and [ssc] sre creas] EXSYNC = 0 selects internal sync detection. [of zisscy a aon are Sa-11

a Command Register The TxEMP and RxRDY bits have the same meaning as ‘ he pins of the sam Thi /BRK bit general Commands are issued to the uPD71051 by the CPU by Pigriokabiiliniirieg See NCIBRIE pin al y command bytes that control the sendingand receiving ‘gxternal synchronization mode, the status of this bit pe tira of ine uPD71051. A command byte is sent goes not always coincide with the pin. In this case, the ater ee te (in one ING come byte SYNC pin becomes an input and the status bit goes to 1 the CPU must set Coes Figure araciere and when a rising edge is detected at the input. The status the ‘4 byte - se ae ‘igure 6 shows the bit remains at 1 until it is read, even when the input level command byte format. at the SYNC pin goes low. The status bit becomes 1 Bit EH is set to 1 when entering hunt phase to when a SYNC character is input with the RxDATA synchronize in sync mode. Bit RXEN shouldalso beset input, even when the pin is at a low level. to 1 at that time. Data reception begins when SYNC The pgR bit shows the status of the DSR input pin. The characters are detected and synchronization iS status bit is 1 when the DSA pin is low. achieved, thus releasing hunt phase. . The FE bit (frami hen less thi When bit SRESisset to 1, asoftwareresetisexecuted, one foe nina ming oreo eo es ee ata block and the uPD71051 goes into standby mode and waits qyring asynchronous receiving. Figure 8 shows how a foramode byte, __ framing error can happen. Bit RTS controls the ATS output pin. ATS is low when the RTS bit = 1, and goes high when RTS = 0. Figure 6. Command Byte Format Setting bit ECL to 1 clears the error flags (PE, OVE, and co=1 FE) in the status register. Set ECL to 1 when entering ee oe the hunt phase or enabling the receiver. [e-Tsnes]rrsfece] sone] ren ford rxe%] i = [ren] Tom eae] Bit SBRK sends a break. When SBRK = 1, the data [iemmense| currently being sent is destroyed and the TxDATA pin KS goes low. Set SBRK = 0 to release a break. Break also works when TxEN = 0 (send disable). Com [omencona] Bit RxEN enables and disables the receiver. RXEN = 1 [ro [ora enables the receiver and RxEN = 0 disables the Cet ome receiver. Synchronization is lost if RxEN = 0 during aloe] sync mode. [Vo [ bieabie | Bit DTR controls the DTR output pin. DTR goes low | CT eestie J when the DTR bit = 1 and goes high when the DTR ea] eee] whet [+ fos wate The TxEN bit enables and disables the transmitter. =e TxEN = 1 enables the transmitter and TxEN = 0 disables the transmitter. When TxEN = 0, sending (ra ner] stops and the TxDATA pin goes high (mark status) Fo [re neaton_| after all the currently written data is sent. [5 [rer Fea cess] Status Register | ES The CPU can read the status of the #PD71051 at any [a] aso) time except when the #PD71051 is in standby mode. Status can be read after setting C/D = 1 and RD =0. poe Status is not updated while being read. Status updating a is delayed at least 28 clock periods after an event that | affects the status. Figure 7 shows the format of the om ee status register. [0 [wo operation | [1 [enter Hunt Prase] Wot {11 The EH itis etectve ony i SYNC mods SC -12

: : When the CPU reads the data, RxRDY becomes 0. When a start bit is detected, the sampling points of the _ these errors. data bits, parity bit (when used), and stop bit are 45 . Figure 13. Start Bit Detection level of more than one bit is input to the RxDATA pin Samsting async transmit example.

1 Sameting

[2) Start is recognized because R x Data is low at the sampling time. Figure 14. Asynchronous Receiver Example

Receiving in Synchronous Mode bit becomes 1, and goes to 0 when the status is read. to 1. In internal synchronization, data onthe RXDATA _ by issuing an enter hunt phase command. hunt phase and SYNC is setto 1 inthe center ofthelast is read. by setting the SYNC pin high from an external circuit _ sent by the previous sync transmit program example. data reception can start. At this time, the SYNC status = and AXCLK on the receiver must be the same. Figure 19. Internal Sync Detection Example

0 Giereipr epee ee ah

Dulterportaisvalidand part aienotused SYNC ~ when part 2.