D7004C | DigiCamel IC Datasheet

Online Datasheet

Read D7004C online.

UPD7004C NEC | Alldatasheet

Document overview

Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 18

Technical content

. NE C-ELECTRONICS INC 30E D M@@ 6427525 003054 5 ME T-s/-[0-10 Bl, REAL MOS INTEGRATED CIRCUIT O Bee ‘uPD7004C (nobus re 10-BIT CMOS SUCCESSIVE APPROXIMATION A/D CONVERTER oe The uPD7004 is a 10-bit monolithic CMOS analog-to-digital converter using the Successive Approximation Register (SAR) technique. The uPD7004 incorporates an 8-channel multiplexed analog input and full microproces- sor interface to achieve a high degree of versatility. The designer has a choice of either serial or parallel output and - interface to 8080 type microprocessors or advanced signal processors like the uPD7720.

FEATURES

( @ channel multiplexed analog input . © Serial or parallel interface @ 10-bit resolution © Linearity: 1 LSB MAX. (Ty = 25°C) © Conversion time: 10 us (foLk = 1 MHz) © Input voltage range 0 to Vage © Temperature range from ~40 to +85 °C © © Operates from single +6 volt supply (5 V +10 %) BLOCK DIAGRAM AY, ” ia ctock £3 FESTSADECKI vc “ye 2 2 i | ; F 7 4 cH7 0 Progam s OA uence C \\ ors | vee Frgauerey | Cx jequence Controller ofse Register oe Senister H T C87/sO - ‘ O8g/St 2 oes/suiet ° OB g/SCKO

108 O”A a —— 28;/08V

NEC cannot assume any responsibility for any circuits shown or reprerent that they are free from patent infringement. . ( . D NEC Corporation 1987

NN E C ELECTRONICS. INC 306 D M@@ &b427S525 0030547 7 a BEI RRS EES OS 0 queens CONNECTION DIAGRAM (Top View) , _~ TEESE ECSTECE ) { 1 ( fo SsS5 35292 § 3 83 | Fae3a88928 gaeia2 PIN IDENTIFICATION . . PinNo. | © Sumbol = d

3 CHg | Analog input CHg,

: > Pa Digital Power Supply Note Analog Power Supply Nowe | ee [2 iho | CAnatoginoutcHg Note: Connect to Digital Ground (0.GND) with Analog Ground (A.GND) externally. a Connect to Digital Power Supply (D.Vpp) with Analog Power Supply (A.Vpp) externally. 2 . .

NE C ELECTRONICS INC 30E-D mm 6427525 0030549 0 mm : CONVERSION CHARACTERISTICS (T, = 25 °C, Voo = Vacr = 5.0 #0.5 V, fox: = 1 MHz) - DC CHARACTERISTICS (Vpp = Vaer = 5.0 0.5 V, T, = -40 to +85 °C, foxi = 1 MHz) a) ____1_-_____ tent to the series circuit between Ril and ‘ct ! 100 | > pF: Ch : x * Equivalent Circuit External Internal Analogue Input AID Block (CH to 7) Cy i) I Charge or discharge current flows at the internal multiplexer switching timing. Therefore, connect a capacitor (0.01 pF) to the analog input terminal in case the external is high. 4 :

o NE C ELECTRONICS INC 30E D m@@ 6427525 0030550 7 = Rm . ad Re CES rR NS TRS CTR BA ET RD BEARS SE RE LON TY TST RR TOT Oe Be Saye a Nie REED ON SAS CA OU ag at Ry Se Ray Pen ee sen ER REY, AC CHARACTERISTICS (Voo = Vaer = 5 #0.5 V, T, = -40 to +85 °C, foxy = 1 MHz) Q a ‘ Output Delay Time tRD : "450 | ns | RO 4— 08 (Parallel Mode) toxo | ' | 250 | ms | SCKI4, SCKO 4 +0 (Serial Mode 1, 2) Serial-qut Enable Delay Time 1 tHKS oO} | 200 | ma: SCKO 4 ~ SOEN t (Serial Mode 2) Serial Clock Output Cycle tcyK tok! ns * (Serial Mode 2) High-level Serial Clock Pulse Width | twHK 400 | I ns. (Serial Mode 2) Low-level Serial Clock Pulse Width / twik 400 | | | ns | (Serial Mode 2) Serial Clock Rise Time | tse | 20 | | ns. | (Serial Mode 2) a t ... Rising edge ' +... Falling edge TIMING CHART 1, Parallel Mode g (1) Write Mode CS, Ag t AW twa : j nw wa : tow ew 080 to7 — s

NE C ELECTRONICS INC 306 D. mw 6427525 0030551 7 mm See Te a ee pe ey -51-10-10 eee (2) Read Mode . . : wo GiAg - ) . tan 5] tRA tAR - iio) ) . - tro tor 080 t07 XY 2. Serial Mode 1 Eoc stHECS ISCSKy wird THKCS i | CT 7 bak . | Wu sre: | i st 1 ' TtHKST. ; 5T8 SN mrp tone : att ‘Fcso b 3. Serial Mode 2 SOEN Vv - I _WHK . tCYK tHKS | . ; tsks ee loam . os y _f p {Wek toKo ' a 6 .

ae NE C’ ELECTRONICS INC 30E D mm@ 6427525 00305Se 0 mm — SCO c Ge Co a ey = T-51-10-10 oO INTERNAL BLOCK OPERATION . ‘ 1, Sequence Controller . . The sequence controller controls the operation of the comparator, internal sequence of the successive approxi- . mation register, and the 3-state buffers. . The A/D conversion starts in the parallel mode when the MPX address is written, and in the serial mode when the CS signal changes to the high level. . When the A/D conversion is terminated, the sequence controller issues an end-of-conversion signal (EOC) to notify this to the external environment. . 2. Successive Approximation Register The successive approximation register sends signals to the decoder of the 10-bit D/A according to the control signals from the sequence controller and then decides to set or reset the signals for the decoder, starting with the MSB, with the help of the results from the comparator. ( 3. Bi Directional Shift Resister This is the register into which the contents of the successive approximation register are entered. It outputs the converted data via 3-state buffers when in the parallel mode. In serial mode 1, it outputs the converted data from the SO terminal when the SIKI signal falls and the CS signal is low, and fetches serial data (MPX address selector data) from the SI terminal when the SCKI signal rises. In serial mode 2, 10-bit converted data accompanied by 6-bit high data is output from the SO terminal synchro- nously from the falling edge of the SCKO signal. Q 4. Status, Address Latch The status and address latch are 3-bit registers to latch the clock division selector ratio data, code selector data of the conversion data, and selector data for the MPX address. It reads the data entered from the data buses (DBg ¢q 7) in the parallel mode. In serial mode, it latches the division ratio selector data and code selector data specified by the multi-function terminals (DBp/DEV 9, 0B,/DEV4, 0B2/ CODE) and also the MPX address selector data entered through the SI! terminal. However, that the MPX address is fixed at CH7 and cannot be selected in serial mode 2. ' 5. Programmable Frequency Divider The programmable frequency divider designates clock signals entered from the external circuit to one of the ratios 1/1, 1/2, 1/4, and 1/8, . 7

NE C ELECTRONICS INC 30E D m@ 6427525 0030553 2 ; SE SEG REEL NES ga REE on aa re eae oe, POETS! ahh «aA e eats Maes Bele ne eA EA pean pozdd: Pee wen ante eee EMG n er ee ree apes Be ae : T-51-10-10 OPERATING MODE . ~, The UPD7004, serving as an interface circuit with the microcomputer, supports two kinds of serial modes and a ) parallel mode, . 1, Parallel Mode : The parallel mode allows a direct connection to the microprocessor data buses, Shown below is an example of the basic sequence; . . a Or a Oo Wr LI LI YS Ag ) ae JONG AIO Conversion AID Conversion

2 Se 2 3 3 3 3

2 § 3 32. «32 a5 E33 EB 33 833 33 53 335 ‘

38 B gs (33 23 ge ms

33 $3 The initialization designates the clock signal division ratio for the clock signal entered from the external environ: ment and the conversion data code (2' s complement/binary). Normally, initialization is performed to initialize the peripheral circuits of the microcomputer. After initialization, the data entered is held until the next initialization. AY Writing the MPX address into the 4PD7004 (WR signal) after the initialization makes the A/D conversion start from , the rising edge of WR signal. The A/D conversion requires fox {internal clock: fox X division ratio) to be 96 to 104 cycles, The EOC signal changes to the low level when the A/D conversion is complete to notify this to the external environment. The 10-bit converted data is read out from the UPD7004 eight bits at a time. The low byte has valid data in its two high-order bits, followed by six '0"’s in the rest (DBs to DBg). Resetting the MPX address starts the next A/D conversion, changing the EOC signal to the high level at the falling edge of WR signal. 8 . .

NE C ELECTRONICS INC 30E D M@@ 6427525 0030554 4 mm SEINE Cech eo ea ae J-51-10-10 oO Data Bus I/O Operation (parallel mode MC = H) . Control terminal ( = — — Operation ‘Serves as a data bus terminal : cs Wa aD Ag | Hq x x x | | No Operation High-impedance State . L H a x i L t 4 Ht Initialize 1 Code Select, Clock Division Ratio Input . L L H tL | Address Set | Anatogue Channel Select Data Input L H u H =| High-byte Read 1 High-byte Data Output L H L L Low-byte Read Low-byte Data Output L L L x I Inhibit i - (1) Initialize In the parallel mode, the initialization data for the clock division ratio and the A/D conversion data code are written into the uPD7004 through data buses. 0B7 08g 08% 084 083 082 0B; 980 eT Te TL = [one oon [oe] i © High-impedence state H DEV; | DEVo | uc {oH 12 | Loop fe CODE Code Select Data written at the initialization is held afterwards, H 2 s Complement O2t2 oO - . 9

NE C ELECTRONICS INC 30E.D M@@ b427S525 0030555 b mm a See BeOS ee ee — T-51-10-10 {2) Address set . . lam The selector data for the analog channel is written into the 4PD7004. Nae 087 08% 08 084 083 DBg 08, 08% Cersrersrsccacs Lf Lf pe fe fete | . ee Pope Poa . v (3) High-byte/low-byte read The A/D conversion data is read from the uPD7004. 087 08 08s 084 083 082 08; O89 High-byte | MSB | 2NO | 3RO | 4TH | STH | 6TH | 7TH , BTH | Low-byte | 9TH j LsBo} Lo! cof te foe bos ef ) EXAMPLE OF THE PARALLEL MODE INTERFACE Fig, 1 shows an example of connecting the uPD7004C to the uPD780C system. As shown in the example, the parallel mode can handle connections using such basic interface circuits as microcomputer peripheral LSIs. In this example, the 4PD780C is employed as a CPU, It is also possible to have other 8-bit CPUs connected in the same logic design, with some timing management by the wait cycle. 10 .

~: NE C ELECTRONICS INC 30E D m@ 6427525 0030556 6 mm Bt Me tn tensa aa, cob ape ee Lea NY MRA DYESS HME SENS Sle UiasiehTiar Saher RE EEE: aaete | JE ap ee ai nee en ee te eee ee "[-51-10-10 eal © Fig. 1 uPD780C/uPD7004C connection owr | 4PO780C DataBus 7 System . ay SO Address Bus } Address Decoder 2.Voo AYop y 089 to7 Ag oS RO | WA Analog input © CHoto7 mc 0c a

7 I cLocK 2

A.GND A.GND) A.GND 0.GND AVop 0.Vop Vaert © Sil *1 Can be used for interrupt request signals to the CPU. *2. Can apply a clock to the CPU, (up to 8 MHz) a . 11

. NE € ELECTRONICS INC 306 D m@ 6427525 0030557 T Bs Ok PRP Rae Pr PRET ERAE US GORE Got Ree ag PIU DA aa pS PTD eo Wen bisa (ee mee ee eae T-51-10-10_ Sos 2. Serial Mode . The serial mode includes serial mode 1 and serial mode 2, Described below are the functions of terminals operat: ing in each mode, ) SERIAL 1/0 OPERATION (Serial Mode 1, 2, MC = L) . : | Serial Mode 1 | Serial Mode 2 Symbol Pin No. 1 {External Serial Clock, Ag = L) (Signal Processor Mode, Ag = H) . i vo | Funetion vo Funetion so _ 7 { Ourput | Serial output (three state). Data are : ; SuIpUE atthe falling edge of SCKi or i : SCKO, st 8 Input __ Serial Input. Data read at the rising | Input Connect to Vo * edge of SCKI or SCKO. | SHIFT 9 Input ——Shift Select (H: LSB first, L: MSB first) . 5CKO 10 - Connect to GND F Output —_| Serial Clock Output (* Internal Clock) SOEN " - Connect to GNO Output; Serial Output Enable (= Active Low) ) cope 12 Input Code Select (H = 2's complement, L * Binary) oevt 13 Input —_* Division Ratio Setting fov, rertrttutnt i ee DEVO 14 Input DEV rr ee : “Division Ratio 2A | 2" 1/4" 1/8; S76 19 Input _ Address strobe Input MPX addresses £ Input * Connect to GND are latched at the rising edge of STB i : Input, , SCKi 21 Input SEKI controls the shift operation of - = = Connect to VoD ; 1/0 interface shift register. Data are : : _ Output at the falling edge, and input : at the rising edge. es 22 Input Chip select signal input. Low level of < Input {Internal sequence reset signal input. : + GF resets the internal sequence, and | Sequence controller are reset at the : ! * 1/0 intertace is enabled. : | tow level of CS, and A/D conversion H i \\ | starts at the rising edge of CS. ) : t : Notes: 1. In serial mode 1, the following signals are strobed by the CS signal, Therefore, the input signals are ignored and the out- put terminals become high impedance when CS = HIGH. Input Terminal: St, $76, SCKI Output Terminal: SO 2. In serial mode 2, the internal sequence reset signal (CS) specifies CH7. wa 12 . .

NE C ELECTRONICS INC BoE) b4y27SeS oe 1m ‘SESE PERE a RENT ea eee ne VE Roose Hes SR Saya sEENECon ols cue ce ee 1-s1-10-10 a] 2.1 Serial Mode 1 : . Serial mode 1 supports the serial data 1/0 when the CS signal is at the low level, outputs the serial data from the ( falling edge of the serial clock signal (SCKT) entered from the external circuit, and fetches the serial input data at the * rising edge of the SCKI signal. . \\f the MSB-first data is specified (SHIFT = L), the last three bits of the 10-bit serial input data for the MPX ad- dress selection contain valid data. If the LSB-first data is specified (SHIFT = H), the first three bits of the 10-bit data for the MPX address selection contain valid data. This MPX address data latch in the uPD7004C is implement: . ed when at the rising edge of the STB signal. The latch can also be achieved at the rising edge the CS signal, if the STB signal is fixed at the low level. The A/D conversion starts from the rising edge of CS signal. The EOC signal changes to the low level at the end of the conversion to notify this to the external environment. The time required for the A/D conversion is the same as that required in the parallel mode, The EOC signal changes to the high level from the falling edge of CS signal. The A/D conversion is repeatedly operated when the CS signal stays in the high-level and the EOC signal remains in the low-level. ( Serial Mode 1 Timing Chart =< ) cs ¥ i st 5 Fy - ) SHIFT =U) (sssaX 2naX_3ra X atm X sem X str X 7m SENSE NESS) | Shan Selector tgiet=ny Xs KEEN SIX 7 (Bem Y Sm Yen Y 3ea YX 2a Xs 9X | Data tout STS re Vr Ss niet uy) ~~~ “(SB Gna aes ae XSi YS YT Ge Xe XS - - - so ; suiet=m) —~~--(ose (Gn am \\ 7m (mm my Ge ea SE = The 3 low-order bits of the serial input data serve as channel selection data, 8th bier ute HH? Hi H | $s = - i 9th a ee Ho. kL ' kL i oH H | 1 use en ee ee SS Hq! ay 795-5 SPT? TP aT . | Channel i CHo | CHy | CHz ; CH3 , CHg j CHs ; CHe ; CH7 | . 13

cq NE C ELECTRONICS INC 306 D m™ 6427525 0030559 3 a EYES REET RRS ER RN Se OE TB EME ES STIS COD GEE 5 anes Tape aed Se ep OGst ee eee kee, = T-51-10-10 ad Serial Mode 1 Sequence Timing Chart . . a cr cc cc ) SCKI — Fr | se 0000000000000 IE -- - A rr i re ce Conversion A/D Con- Conversion A/O Con- Data Read version Oata Read version MPX Addr e MPX Address i. 3 3. 3 5 53 $2 8a 5a 8a éa y Example of the Interface with the uPD78CO6A Fig. 2 shows an example of the interface with the uPD78CO6A. Fig. 2 uPD7004C/uPD78C06A connection ; : ‘ uPOD78CO6A f o-Voo uPO7004C so si SCKO Fd nn Fo ml) ove ScK SCKI SOEN Ct cope _ | | Serial Mode 1 aE ve LI : ee PBQ Eoc DEV + 2's Complement Code — * Division Ratio: 1/2 sTB | out CLOCK mc I , : ho . 7 -@ A.VOD Vec O.Vpp 0.GND | A ae Vrert CHg~7 © Analog Input . A.GNO A.GNO . OUT * 2 MHz . a 14 :

wen NE C ELECTRONICS INC 30E D m™m@ b42e7Se5 0030560 T ml SE ap rs car a eae TOIT ERAS HE SPA EOE: 7 RO Be Pre Deh EE RE ATG SRL, gaelic HS Bees Vy SRO fr RS RC GR eee eg LN SRS, T-51-10-10 StF HPD78CO6A contains a serial interface circuit and handles 8-bit data tragsfer. Therefore, the uPD78CO6A operates 8-bit data transfer twice to handle the uPD7004C's 10-bit serial data transfer. The timing of the data t transfer is shown in Fig. 3. . Fig. 3 Timing in serial mode 1 (connection with HPD78CO6A ) , EOC (P8q) ES (PAQ) SRE) PUT Sols , —---(aSeX and Ged (atm Sem KSA KTH X_Bth__ XS TSBO EYOTA ISAK Dig === oa — AID . Conversion Data 1 si (so) (OTs OraOraOraXOr XO 1K Os KOs Or KOS KOs KF KOs KS2X Oi} D9 Analogue Channel ( Selector Data *2 "1 The data entered through the SI terminal is output from so, _ *2. Channel selector data is latched at the rising edge of the cs signal when the STB signal is fixed at the low level, Channel selector data D2 Pe} ed ej ede tw | HLA | ae » Dy "oe! ts At HG kos kb | HOY HE 100 ee ee ce * Channel | CHo ° CHy : CHg | CHg } CHg } CHs | CHg ! CH7 € : . . 15

amNEC ELECTRONICS INC 30E D M@™@ 6427525 0030561 1 ' PREP Ae cee ee CE Gey = 7-51-10-10 Bees 2.2 Serial Mode 2 ‘ . . : . Serial mode 2 allows direct connection to the serial interface of the signal processor uPD7720AC. . Shown on the right is an example of connecting principal terminals between the uPD7004C and uPD7720AC, J Serial mode 2 differs from the other two modes. This mode cannot specify the MPX address to the uPD7004C since the address is fixed at CH7. : Although the data through the A/D conversion consists of 10 bits, it is followed by six bits of high data when it . is output as serial data. These six bits of high data always follow the converted data for MSB-first or LSB-first. (Refer to the Serial Mode 2 Timing Chart.) The A/D conversion sequence starts upon the initialization. The Initialization is operated by holding the CS signal at the low level for more than eight clock cycles, The A/D conversion starts when the CS signal changes to the high- level. The A/D conversion requires 104 clock pulses (fx). The EOC signal, as in the other mades, changes to the low level to notify the end of the conversion to the exter- nal environment. The EOC signal remains at the low level until the initialization is implemented. The data converted and output immediately after the initialization is invalid. Valid data is available from the second output. This is because the MPX address is fixed at CH7 for theconverteddata output after the initialization. ’ The A/D conversion and the converted data output are repeatedly operated while the CS signal is in the high level. d (Refer to the Serial Mode 2 Sequence Timing Chart.) . HPO7004C 4PD7720AC $0 si : : SOEN SEN SCKO sck . . Sarial Mode 2 Timing Chart SOEN \\ [ Esc amen WO OO OW oO ) (suite =u) = - = -- SE) Rra Gra atm X Sth Eth YX 7th Latn omn Xs8/ --- Fe a eens @ SED. 0) 09 LD CD aD CTD Ee CED CS D--- Serial Mode 2 Sequence Timing Chart Sf SOEN \\ / \\ [ \\ a 16 .

my NE C ELECTRONICS INC 30E D M@M@ b427525 O0305be 3 mm hi Ke Pig RES A ERED Peer ia Seve T-51-10-10 INTERFACE IN SERIAL MODE 2 4 In serial mode 2 direct connection can be made to the digital signal processor (uPD7720AC) and A/D conversion, unlike the parallel mode and serial mode 1, is operated in a periodic cycle. Signals in the interface, unlike with serial mode 1, are controlled by the uPD7004C. Fig. 4 shows an example of . connecting the #PD7004C to the uPD7720AC. = Fig. 4 uPD7004C/uPD7720AC connection #PD7720AC #PD7004C o-oo HwPCE49C SIEN SOEN ( O.VoD -9 GND A.GND : a st cLK oo o(1 MHz) a CODE 3c RESET Ao 9.Vop a DEVo Vrert ae || 3°. FT 0.GND . | | mic A.GND D.GNO { As shown in Fig, 4, it is possible to interface with only three kinds of signal connection lines in serial mode 2. A/D conversion is operated every 104 ys cycle (where clock = 1 MHz). The converted data is output synchronously with the SOEN signal. The pPD7720AC's serial interface operates 16-bit data transfer, while the converted data consists of 10 bits. Therefore, 6 bits of high data automatically follow the 10 bits of converted data. In the example above, the external sample & hold circuit (uPC649C) is used and the whole operation is operated as a kind of pipe-line processing. The SOEN signal supplies valid data three cycles after the reset cancellation, and then supplies converted data every 104 us after this. , 17

w NE C ELECTRONICS INC 30E D m™@ b4e7Ses 0030563 5 ml — SNLar mg Une aren error a Ts -10-10 EA ; PACKAGE DIMENSIONS 4 wa 28PIN PLASTIC DIP (400 mil) : 28 15 - 1 14) A ; ) ~ oh ” VOI BBA AAAYuee'Uy i F ae HD cs M o~18" . P28C-100-400 ——— NOTES ; “\\TEM MILLIMETERS INCHES 1) Each lead centerline is located within 0.25 aa 2a eee 2) Item “K" to center of leads when formed ; Tore 3a 1 parallel. io! 0.50 | 0.020 8888 ) iF } 1.1 MIN. 1 0.043 MIN. 4H | 0.51 MIN, {0.020 MIN. | mo L 8.6 i 0.339 [ou | 0.25 8.68 0.010 78 883 x [oz Toor

Product Information

D7004C specifications and overview.

Summary

MOS INTEGRATED CIRCUIT

Description

MOS INTEGRATED CIRCUIT

Source title D7004C Datasheet(PDF) - NEC

Related Parts

More parts from the same family.

Browse manufacturer