D65005C198

UPD65000 NEC | Alldatasheet

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i VE Cc _? vPD65000 (CMOS-2) SERIES NEC Electronics Inc. 3-MICRON CMOS GATE ARRAYS < 5 April 1985 Description Figure 1. CMOS Gate Array Chip Layout The uPD65000 (CMOS-2) series of gate arrays are low- gate CMOS technology. The basic cell on the chip _} = consists of four transistors, two P-channel and two = AL ——--—-—--- If 2 N-channel, with double-layer metal interconnects. See St ee figures 1 and 2. Uf -----===== |) Hl out Gate arrays are available In a variety of sizes (400 to mon 2,000 cells) and package types. Gate arrays are intended for customers seeking cost effective alternatives. With gate arrays, customers can reduce component count and board size so that they NEC's gate array program allows a customized IC to be ———— developed quickly and at a smail fraction of the cost of as a full custom development program. . NEC's comprehensive CAD support system and master slice system significantly reduce the time and expense este Ont usually associated with semicustom devices. Normal cc 4 turnaround time, after logic validation, is only 8 to 12 | | weeks. Advanced CAD tools, such as logic simulation, { | j C automatic placement and routing, delay simulation, joq 4 I . and test program generation ensure accurate error- i" wn? | free designs of all NEC gate arrays. | Features “| . CO High speed: 3.0 ns/gate (with fan-out of 3 t | and 3-mm wiring) vL--———--—-4 S CO Low power: 30 uW/gate/MHz © Quick turnaround time: 8 - 12 weeks woomnres D Simple interface to customer's circuit diagram and test pattern sheets Figure 2. Coll Configured as a Two-Input

1 Fully supported by advanced CAD 2 NAND Gate

— Logic simulation — Automatic placement and routing tos — Test program generation — Delay simulation O Direct access to CAD simulation — Designers can use thelr own terminals through a s focal network to an NEC design center for logic one simulation © Four types of output buffers — Normal 2 — Open-drain — Three-state — Bidirectional CO Wide choice of DIP, QIP, PGA, and flat packages to sult unique applications j

vPD65000 (CMOS-2) SERIES NEC | 3-MICRON a | Absolute Maximum Ratings DC Characteristics ). Ta= 425°C Ta =—40 to +85°C; Von = 5 V+10% Power supply voltage, Vop 0510 +7.0V a. tet Input voltage, Vj 0.5 ¥ to Vpp +0.5V Porameter Symbol Min Typ Max Unit Conditions Output currant, io 10mA Static current = 0.1 200 pA V\\=Vpo or GND Operating temperature, Topr 40 to 485°C Dynamic loo 6 wh 1 Mike Storage temperature, Ts1¢ 65 to +150°C Sen input current 405 10 wA Vj=Vpp or GND Comment: Exposing the device to stresses above those listed in Se > —_—_ Absolute Maximum Ratings could cause permanent damage. The Low-tovel le 32 «6 mA Vo. = OAV device is not meant to be operated outside the Recommended output current Operating Conditions below. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Ce rect lon 1 2 mA Vou™ Yoo 04 Recommended Operating Conditions Soa velene Vou O1 Vo to=0 Ta=—40 to +85°C a Limits Test ouput vottage YOH Yoo~0.1 Vo bp=0 Parameter Symbot Min Typ Max Unit Conditions vz 0TvV——— Power Vo 45 #5 SS V AC Characteristics Supply voltage Ty = 4010 +85 °C; Voy = 5 V +10% Input voltage WO Yoo ¥ eo ee —— a __ Test Vit 0 0.3Vpp V CMOS level Parameter Symbsl Min Typ Mex Unt Conditions High-level input voltage Yt 97 Yoo Vpo V CMOS level ~— fyax 10 MHz 4 Low-evel | inputvortage YR OO 08 V Tiievelt Delay time! hd Fa Fa Gate - High-level Input yottege YM 20 Yop ¥ TIL levelt bok ta 5 ns 0, =15 pF Input rise, fall times fale 0 © « Output te 8 ns C,=15pF Nole: 1. Ty =O to +70°C, Vop = 8 V 5% Note: 1. With fan-out of 3 and 3 mm wiring. 2. With G, = 18 pF Configuration Data yPD6S003 ~=,POSSOG2 © —PDGSGI0 —_,PD65020 Number of cells 47 8 1,388 212 Girowsx G6rowsx 76rowsx SBrowsx Configuration 7 columns 13 columns 18 columns 22 columns ‘Number of input butters B “8 4 7 Number of output butters hed bad % a

Figure 4. Example of a Test Pattern Chart

uPD65000 (CMOS-2) SERIES - NEC 3-MICRON . Gate Array Development Process . ) Figure 5 Is a flowchart showing supporting data, development steps, and customer/NEC interface options. Customer/NEC Interface Options Development Steps NEC’s computer and communications environment Design Rule Checking. Once the circult interconnect allows gate array designers to select the Interfacemost data is complete, the first step of the logic validation suitable to their needs. process is the design rule check. Parameters such as Standard Data. Forthesimplest interface, the customer 2! usage, power Giosiveton and fan-out loading are provides a circuit diagram and test patterns. The determined and checke remainder of the development process is NEC’s Unit Simulation [Static Logic Simulation}. Here, any responsibility. coding errors and data conversion errors are eliminated. Macro Converted Data, The customer provides a Delay Time Simulation. Before automatic placement circuit diagram based on the macros in the Block and routing, delay time simulation gives an accurate Library plus test pattern data. - estimate of the expected circuit delays. File Generated Data. The customer provides a netlist | Automatic Placement and Routing. NEC's advanced and test pattern file in NEC compatible format. The —_ software allows up to 95-percent cell utilization without netlist is a text file describing circult Interconnections. —_ resorting to manual routing. Data may be sent to NEC on magnetic tapeorafloppy Final Delay Time Simulation. Here, wire lengths are disk or transmitted via telephone. The formats and taken into account. Results of this step provide the F Pras anpreer tase Nak Desks Oeeter. fullyspecified — customer with an accurate circult analysis. © SOP FOS . . Production. If the above steps are completed suc- Graphic PC Generated Data. Using the PC9800 cessfully, design enters actual production followed by — workstation, a customer can easily generate the —_490-percent wafer testing. ) so eetaton supports schematic ¢ sour and inohog Packaging. Successfully tested wafers aredivided into design rule checking. individual chips, which are then die-bonded onto the customer-specified package. Chips are then wire- Workstation Generated Data. For this interface, the bonded and sealed. The do parameters and logic ; customer performs logic simulation using either — functions of each chip are checked in the final test. i workstations by Valid Systeme, Mentos oreo Daisy Pro . Ten engi ng samples are : _— Soopuier: NEC: ven the hnelconspatotity delivered to the customer for the system function test. ; check. (Separate manuals describe the various work- If customer evaluation is satisfactory, the development station interfaces.) process is finished. NEC Is ready to begin mass PG Mask Tape Interface. A separate manual will be P . Issued when this interface becomes available. TEGAS-S Is the trademark of Calma Company. J

NEC uPD65000 (CMOS-2) SERIES ’ : 3-MICRON C: Figure 5. Flowchart for Gate Array Development (_ systm ostition _) sa Standard Oala me [nace conse | Se eS Macro converted data lO oe Block Library Dats Keptn [ Getesnen | |__Gonwroson—_| -_-_so File general data [Design Rule Check_] Graphic PC generated data Late End> oK : - OK OK MASTER2 — ——S Laine | TTT NBO OAD toes funder doreloprecst] [aes Prossesing [Feat [—senpie Gainey ( ) [istomer vertesuon (wavs Production) secon . 5

NE C ELECTRONICS INC 72 DEP G427525 oODaeso 4 G0 1-42-11-09~ : uPD65000 (CMOS-2) SERIES . NEC 3-MICRON Development Procedure Essential Documents : ) The semicustom approach of gate arrays offers a 1 Contract and nondisclosure agreement unique and effective method of manufacturing ICs at Circuit diagram based on the NEC Block Library reduced cost and development time. NEC makes this 0 Interconnection data file (LOGINC) possible by stocking wafers that are completely ( Test pattern file (NELPAT) fabricated except for the final step of interconnection. 0 Pin assignment (if required) This provides adesignerthe freedom ofinterconnecting 1 Critical path identification (if required) the uncommitted components to achieve a unique circuit configuration. CMOS-2 Block Library List Interface Blocks Functional Blocks [cont] Bok BK Type Function Type Function Cells Fi0t Input Buffer (CMOS Level) NAND F302 2-Input NAND Gate 1 Foe Input Buffer (TTLtevel) ‘F303 S'inputNAND Gate SSS Fi03, Fl04 Oscillator block F304” “input NAND Gate SSSSSC«S~S FOO! Output Buffer (Normal) F305 “SinputNAND Gate SS __EXT2___Output Buffer (Pech Open Drain) FOB BinputNANDGate B003 1/0 Buffer (Three-State CMOS Level In) AND F312 2-Input AND Gate 2 8004 __1/0 Buffer (Three-State TTL Level In) ‘Fad SinputANDGate SSO

8008 Output Buffer (Three-State) Fad GinputANDGateSSSSSC«SS )

AND-NOR F421 2-Wide, 1-2-Input AND-OR-Inverter 2 Fao” $-Wide, 11-2nput AND-OR-Inverter 2 ok "F424 2-Wide, 22-Input AND-OR-Inverter 2 Tyre _Funetion “F425” 3-Wide, 2-2-2Input AND-OR-Inverter 3 “Inverter F101 ‘t-input(F.O=8) F429. 4-Wide, 2-2-2-2-Input AND-OR-Inverter 4 Foo Lint) F442 2-Wide, 4-4-Input AND-OR-Inverter 4 "Fis tinput(f0=2) SSSC~CS:~S OR-NAND — F431 2-Wide, 1-2nput OR-AND-Inverter 2 “Hod” Cinput(FO=32) SO F482. 2-Wide, 22-Input ORVAND-Inverter 2 Butter Fil! input (F.0. =8) 1 F433 2-Wide, 1-3-Input OR-AND-Inverter 2 Fi2 Vinput(eO=1)SSSSSS™S~«i~S F434 | 2Wide, 22-Input OR-AND-Anverter 2 Fs tinput(.0.=2) F495. 2-Wide, 2--Input OR-AND-Inverter 3 Hid Vinput(.0.=32) SSCS F496 2-Wide, 33:Input OR-AND-Inverter 3. NOR F202 _2-Input NOR Gate 7 Pa Wide, 2:2-2-2Input OR-AND-Inverter 4 “F203 “Zinput NOR Gate er AFB Cloth OO ee Food “AinputNORGateSSSS*S~S*CS F502 Clock Driver (Dua) nnn F208 B-inputNORGate SSS F503 Glock Driver (With Buffer) men OR F212 _2-Input OR Gate 2 F504 Clock Driver (Dual with Buffer) 4 “Faia input oR Gato ______ FOS, H2eInput NAND-ANDAnverter 2 Q Fai Cinput OR Gate ORGY DAnput Exelusive-OR Gate

NE C ELECTRONICS INC 72 Def by2?ses on082a1 Re. 42-11-09 EC _ p~PD65000 (CMOS-2) SERIES : 3-MICRON a XK Functional Blocks [cont] Block Block Type Function Cells Type Function Cells Full Adder F521 _1 Bit Full Adder 7 Flip-Flop F691 _Serlal/Parallel Shift Resister 5 Tiree-State F531 Three-State Butler (EN) (F.0. =8) 3 Pot2__ 4 Bit Serial/Parallel Shift Resister 24 ufter nent F913 4 Bit Parallel Shift Resister with Reset 35 F582 _ Three-State Butfer (EN) (F.0.=8) 3 “Fri2” Toggle with Reset. SSS ___F533_Three-State Buffer (EN) (F.0.=24) 4 “Fria. TogglewithSetSSSSSS~S~S Multiplexer F569 8-1 Multiplexer “Frid” Toggle with Set-Reset = iL A “F7i5” “Toggle with Reset ST __F582_SBitEven Parity Generator 18 F735. Toggle (T) with Reset 7 latch FIPS at een "F736" “Toggle (i) with Set FOO Debate nnn F737. Toggle (T) with Set-Reset 7 Fore __D-Latch (with Reset) F742 Toggle (Buffered Out) with Reset 3 F603, D-Latoh (with Reset) ee F743 Toggle (Buffered Out) with Set “6 F604 Dea nnn F744 Toggle (Buffered Out) with Set-Reset 6 i F806 _O-LatchG with Reset F745 Toggle (Buffered Out) with Reset 3 ; Poot A BIRD F746 Toggle (Buffered Out) with Set = j < Fm BitDtateh F747 Toggle (Buffered Out) with Set-Reset 8 : Flip-Flop FON OTY PO nnn ae F765 Toggle (Buffered Out) (T) with Reset 8 Fo12_OType with Reset F766 Toggie (Buttered Out) (7) with Set O13 DeType with Set F767 Toggle (Buffered Out) (T) with Set-Reset 8 F614 D-Type with Set-Reset an F791 Toggle with Set-Reset and Tog-EN = 9 F615 D-Type with Reset ne F792 Toggle (T) with Set-Reset and Tog-EN 9 F616 D-Type with Set ene ‘Fa uKRFOOC™~—CSSCS FoI D-Type with Set-Reset “F2 JKF/FwithResect. SSCS F681 OTD enn i “Fig UKF/FwithSetSSSSSSS™S~wN'~S F685 D Type G with ROS eE Frid JKF/F with Set-Reset at Fedt O-Type (Buttered Out) “FT JKE/F with SetReset. SSN £808" DType Gre Ou wih asst co eee nna F643__D-Type (Buffered Out) with Set 8 “Fras JKF/FGwithReset. SST” F644 __D-Type (Buffered Out) with Set-Reset_ 8 “Fas JKF/FGwithSet = SSSS~S~STS*S F645_D-Type (Buffered Out) with Reset 8 - "Fre? JKE/FCwith Set Reset SSN F646 __D-Type (Buffered Out) with Set 8 Counter F961 4-Bit Sync Binary Counter with Reset a4 . F647 __D-Type (Buffered Out) with Set-Reset_ 8 “F962” 4-Bit Sync Binary Counter with Reset 34 F661__O-Type (Buffered Out) CO Decoder F981 2-to-4 Decoder with EN 9 ( F065 D-Type (Buttered Out) G with Reset 8 Fie Ue becker i - F666 D-Type (Buffered Out) Cwith Set 8 Comparator F985 4-Bit Magnitude Comparator 46 F667 _D-Type (Buffered Out) C with Set-Reset 8 Misc BUSA Bus Array | ___Fev2_4BitO-Type with Reset 28 |

eo ane np a eeee nn anne en nn Ne nt Hea Le . N E C ELECTRONICS INC 72 ya | b42a7525 OO08ede 4 r T+42-11-09 »PD65000 (CMOS-2) SERIES . NEC 3-MICRON Operating Characteristics . ) Output Voltage vs Input Voltage [CMOS Input] Output Voltage vs Input Voltage [TTL Input] e 6 a a | Yoo=s8v a Vo-Ls2sv es p vee=tay — 1 Woo —s28) a | 5 pacers |] Lpcteor any : ade eercrs Ba A ‘ Ra : eli | | ita ° 1 2 3 I % 1 2 3 I Input Voltage [V] Input Voltage [V} Output Current vs Output Voltage [N-Channel] Output Current vs Output Voltage [P-Channel] _ Vas =55¥ _ LD ! i - — z s a dl Bos i o 1 2 3 VYoo~3 Voo-2 VYoo-1 Yoo Output Voltage [V} Output Voltage [V) Delay Time vs Fan-Outs [NAND] : Delay Time ve Fan-Outs [NOR] . ® Ta= 425°C Tan 28'S Cength = 3 mmm Cenath = 3 mm foun 6 6 | lL g i + = =| Ee » FE eet |! = TTT] eb Larry ye ty 1 2 3 4 6 i 9 1 2 3 4 5 6 Fen-Outs Fan-Outs: .

N E C ELECTRONICS INC ?e Na | b4y27525 0008283 O | D T-42-11-09 Ni: F IC »uPD65000 (CMOS-2) SERIES ; 3-MICRON aS C Operating Characteristics (cont) Delay Time vs Length [NAND] Delay Time vs Length [NOR] 6 6 4 - 4 | : fee i, z ‘ i , i 0 1 2 3 4 5 6 0 1 2 3 4 5 6 Length (mm] Length [mm] Delay Time vs Supply Voltage [NAND] Delay Time vs Ambient Temperature [NAND] ‘ 5 | —{ i. | 3] ob TF E z i. | ot se i, | i | _- t 1 Fan-ins =2 2 _— Fan-Outs = 3 _ i Length = 3 mm <

0 H 1 H

40 45 5.0 58 60 50 o 50 100 Supply Voitage [V] ‘Ambient Temperature [°C] Delay Time vs Supply Voltage [Input Buffer] Delay Time vs Load Capacitance [Output Buffer] 8 “ es ; a aim | a i ee a ‘ a ——J ‘tei [CMOS-Inpul] ba = — C : 2 . >= aa | | | | b EL tl ty oe 45 50 55 60 9 2 “0 60 LJ 100 ‘Supply Voltage [V] Load Capacitance [PF] + 9

"NE C ELECTRONICS INC 72 DEJ bue7S25 DOOaz84 1 | ree y»PD65000 (CMOS-2) SERIES . NEC 3-MICRON a Operating Characteristics (cont) ) Delay Time vs Fan-Ins [NAND] Delay Time vs Fan-Ins [NOR] 8 bad nae 7 re). T= " pa 7a i 2 TT ; EpDier | Fan-iee Fanine : Power Dissipation vs Load Capacitance [Output Butter] Rise and Fall Times vs Load Capacitance [Output Buffer] i 3 50 | a a A | et rl i 7 i td i eo é o 20 “0 60 eo 100 ° 2 4 eo 80 100 Load Capacitance [pF] Load Capacitance [pF] 10 .

NE C ELECTRONICS INC 72 DEgf b427525 O008e85 3 | T-42-11-09 NEC _ pPD65000 (CMOS-2) SERIES : 3-MICRON a ra Packaging Information Package Marking The 3-micron gate arrays are available in a wide variety Example of Plastic Package of packages to accommodate unique applications. The following table shows the package types in the origin Company eae uPD65000 (CMOS-2) series. (DIP = Dual in-line “wv MS va package; QIP = Quad in-line package; PGA = Pin grid \\ 7 array.) NEC 8220K1 JAPAN Package Availability “Fokye CO 65000 C 011 Type wPD65003 —,PDG5002 —_,PDESO10 _,PD65020 /- ~ $A OU Pl Master Package —Ciircult erin __. _ “me sxoxicon hh si a ih, 40-Pin a Se Omen ABP nennennnnnnnen nt 64-Pin (shrink) ° ° ap a _SAPim Cut ; 44-Pin e . . . a he erin PGA erin Wo