D6467

UPD6467 NEC | Alldatasheet

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Technical content

Datasheet sections

• 1.1 Initial Status Setting
• 1.2 Application Block Diagram
• 1.3 Display with RGB + VC1 + VC2 Pins
• 1.3.1 Character signal output with output select option A
• 1.3.2 Character signal output with output select option B
• 1.3.3 Character signal output with output select option C
• 1.3.4 Displaying characters specified by VC2
• 2.1 Command Format
• 2.2 Command List
• 2.3 Power-ON Clear Function
• 3.1 Video RAM Batch Clear Command
• 3.2 Display Control Command
• 3.3 Background Color/Frame Color Control Command
• 3.5 Character Color Reverse ON/OFF Command
• 3.6 Blue Back ON/OFF Command
• 3.7 Character Address Bank Select Command
• 3.8 Output Switch Control Command
• 3.9 Character Display Position Control Command
• 3.10 Write Address Control Command
• 3.11 Output Pin Control Command
• 3.12 Character Size Control Command
• 3.14 Initial Status Setting Command
• 3.15 Display Character Control Command
• 3.16 Test Mode
• 4.4 Successive Input of Command
• 4.4.1 When 2-byte successive command end code is not used
• 4.4.2 When 2-byte successive command end code is used

© 1999 DATA SHEET µPD6467 MOS INTEGRATED CIRCUIT Document No. S14455EJ1V0DS00 (1st edition) Date Published November 1999 N CP(K) Printed in Japan ON-SCREEN CHARACTER DISPLAY CMOS IC FOR 512-CHARACTER, 12-ROW, 28-COLUMN, CAMERA-CONTAINED VCR The µPD6467 is a CMOS LSI for on-screen character display, and can be used in combination with a microcomputer to display the tape counter, time, and date in the view finder of a video camera, or the time of a video tape, messages such as dates on pictures, and channel number on a TV screen. Characters are displayed in 12 (horizontal) by 18 (vertical) dots. Two or more characters can be combined to display Kanji (Japanese characters) and symbols. This LSI supports color view finders and is provided with three sets of character output signals (RGB output: for color view finder, VC1 output: for recording (or monitor pin), VC2 output: for monitor pin (or recording)). In addition, the µPD6467 is also equipped with a power-ON clear function and a video RAM batch clear command so that it can mitigate the workload of the microcomputer. The command format of this LSI is identical to that of the existing models, the µPD6461, 6462 and 6466, and therefore, the µPD6467 is compatible with the existing models, and the software resources for the existing models can be used.

FEATURES

• Number of display characters : 12 rows, 28 columns (336 characters)
• Types of character : 512 types (ROM). Changeable by using mask code option.
• Character size : Can be expanded up to four-fold in vertical and horizontal directions independently, in units of lines.
• Number of character colors : 8 colors
• Framing : Framing or no framing, or white or black framing selectable in screen units.
• Dot matrix : 12 (horizontal) × 18 (vertical) dot configuration. No gap between adjacent characters.
• Blinking : Blinking can be turned ON/OFF in character units. The blinking ratio is 1:1. The blinking frequency can be selected from about 1 Hz, about 2 Hz, and about 0.5 Hz in screen unit.
• Character color reversing function : The color of the character and that of the background can be reversed.
• Character left and right reverse : Left and right can be reversed for display in character units.
• Background : No background, blank background, or filled background selectable in screen units.
• Blue back function : Blue or white can be selected as the background.
• External dot clock input : Frequency 2-divide function is selectable.
• Signal output : 3 sets (output (1) R, G, B + BLK/V C1 + VBLK1 /VC2 + VBLK2 and output (2) R + R BLK /B + BBLK /G + GBLK selectable by command) When output (1) is selected, VC1 and VC2 outputs can be selected from three types.
• Video RAM data clear : Implemented by video RAM batch clear command or by clear function on power-ON. The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.

µPD6467 Data Sheet S14455EJ1V0DS00

• Interface with microcomputer : 8-bit variable word length serial input (LSB first/MSB first selectable by command)
• Supply voltage : Supports low voltage (2.0 to 3.6 V)
• Process : CMOS low power consumption
• Small package size : 20-pin plastic shrink SOP (225 mil)

ORDERING INFORMATION

µPD6467GR-xxx 20-pin plastic shrink SOP (225 mil) Remarks 1. NEC’s standard model is the µPD6467GR-001. For the details of the character generator ROM, refer to 5. CHARACTER PATTERNS . 2. xxx indicates a ROM code suffix.

µPD6467 Data Sheet S14455EJ1V0DS00 BLOCK DIAGRAM Remark Signals in ( ) are set by using an initial status setting command (RGB + RGB compatible blanking). CMDCT Data input shift register DATA CLK CS Instruction decoder Data selector... Control signals Display control register Character size register Horizontal address register Write address counter Horizontal size counter Horizontal position counter Horizontal address counterVertical address register Oscilla- tion circuit Synchro- nization protection circuit TEST VDD GND PCL Character data 9 bits 336 words Color data 3 bits 336 words Blink data 1 bit 336 words Reverse data 1 bit 336 words Output specification data 1 bit 336 words Video RAM Back- ground control data register Hsync Vsync Vertical position counter Vertical size counter Output controller VR VBLKVBVG BLK2VC2BLK1VC1 (GBLK ) (RBLK )(BBLK ) Character generator ROM 12×18 bits 512 words OSC IN OSC OUT Vertical address counter 16 17 18 15 12 11 14 13

µPD6467 Data Sheet S14455EJ1V0DS00 PIN CONFIGURATION (Top View) 20-pin plastic shrink SOP (225 mil) µPD6467GR-xxx CLK 1 CS 2 DATA 3 PCL 4 VDD 5 CMDCT 6 OSC OUT 7 OSC IN 8 TEST 9 GND 10 Hsync Vsync V B VG VR VBLK (BBLK ) VC2 (GBLK ) BLK2 (RBLK ) VC1 BLK1 Remarks 1. xxx indicates a ROM code suffix. 2. Signals in ( ) are set by using an initial status setting command (RGB + RGB compatible blanking).

µPD6467 Data Sheet S14455EJ1V0DS00 BBLK : Blanking B BLK1, BLK2 : Blanking Output 1, 2 CLK : Clock CMDCT : Command Control CS : Chip Select DATA : Data Input G BLK : Blanking G GND : Ground Hsync : Horizontal Synchronous Signal Input OSC IN : Oscillator Input OSC OUT : Oscillator Output PCL : Power-ON Clear R BLK : Blanking R TEST : Test VB : Character Signal Output VBLK : Blanking Signal Output for VR , VG , VB VC1 , VC2 : Character Signal Output 1, 2 VDD : Power Supply VG : Character Signal Output VR : Character Signal Output Vsync : Vertical Synchronous Signal Input

µPD6467 Data Sheet S14455EJ1V0DS00 PIN FUNCTIONS Pin No. Pin Pin Name Note Function SymbolNote 1 CLK Clock input This pin inputs a clock for reading data. Data input to the DATA pin is read at the rising edge of this clock. 2 CS Chip select input Serial transfer can be accepted if this pin is made low. 3 DATA Serial data input This pin inputs control data. Data is read in synchronization with the clock input to the CLK pin.

4 PCL Power-ON clear This pin, when high, initializes the internal circuitry of the IC on power

application. 5V DD Power supply This pin supplies power.

6 CMDCT Command specification This pin selects whether a command is input with the LSB first or MSB

select first. When this pin is low, the command is input with the LSB first; when it is high, the command is input with the MSB first. To input the command with the LSB first, this pin may be opened.

7 OSC OUT LC oscillation I/O These are an input and an output pin for an oscillation circuit that

8 OSC IN (OSC IN: external clock generates a dot clock. input) A coil and capacitor for oscillation are connected to these pins. (If the input of an external clock is selected by the initial status setting command, an external clock (clock synchronized with Hsync) is input. OSC OUT is opened at this time.) 9 TEST Test pin This pin is used to test the IC. Normally, connect this pin to GND. When the TEST pin is connected to GND, the test mode is not set. 10 GND Ground pin Connect this pin to GND of the system. 11 BLK1 Blanking signal output 1 This pin outputs a blanking signal to cut the video signal. It supports output of V C1 , and is high-active. (If RGB compatible blanking is selected by a command, this pin outputs the logical sum of RBLK , GBLK , and BBLK .) 12 V C1 Character signal output 1 This pin outputs a character signal, and is high-active. (If RGB compatible blanking is selected by a command, this pin outputs the logical sum of VR , VG , and VB.) 13 BLK2 Blanking signal output 2 This pin outputs a blanking signal to cut the video signal. It supports (RBLK ) (blanking R) output of V C2 , and is high-active. (This pin outputs a blanking signal supporting output of VR and is high-active.) 14 V C2 Character signal output 2 This pin outputs a character signal, and is high-active. (GBLK ) (blanking G) (This pin outputs a blanking signal supporting output of V G and is high-active.) 15 V BLK Blanking signal output This pin outputs a blanking signal to cut the video signal. It supports (BBLK ) (blanking B) output of V R , VG , and VB, and is high-active (this pin outputs a blanking signal supporting output of VB and is high-active). 16 V R Character signal output This pin outputs a character signal, and is high-active.

17 V G

18 V B

19 Vsync Vertical sync signal input This pin inputs a vertical sync signal. Input a negative sync signal. 20 Hsync Horizontal sync signal input This pin inputs a horizontal sync signal. Input a negative sync signal. Note Signals in ( ) are set by the initial status setting command (RGB + RGB compatible blanking).

µPD6467 Data Sheet S14455EJ1V0DS00

µPD6467 Data Sheet S14455EJ1V0DS00 1. INITIAL STATUS SETTING

1.1 Initial Status Setting

The µPD6467 selects the following parameters by using an initial status setting command. Parameter Selected by: (1) Dot clock LC oscillation External clock input (2) Vertical display start position 3-row unit setting 9-row unit setting (3) Pin selection RGB + V C1 + VC2 RGB + RGB compatible BLK (RGB + 3BLK) (4) Output selection Option A Option B Option C (5) Character color reversal Black character White character specification selection (6) Function selection Character blinking Character left/right reversal (7) External clock frequency selection ×1 frequency mode ×2 frequency mode (1) Dot clock To select a dot clock for character display. If an external clock input is selected, refer to External Clock Input in 6. ELECTRICAL CHARACTERISTICS . (2) Vertical display start position To select the setting accuracy of the vertical display start position of the character display area. In 3-row units, the vertical display start position can be set more finely than in 9-row units. (3) Pin selection To select the setting of the output pins. When RGB + V C1 + VC2 is selected, character signals are output from pins VR , VG , VB, VBLK , VC1 , BLK1, VC2 , and BLK2. When RGB + 3BLK is selected, character signals are output from pins VR , VG , VB, RBLK , GBLK , BBLK , VC1 , and BLK1. When RGB + V C1 + VC2 is selected with a video camera with a color view finder, colored characters can be displayed in the view finder. When RGB + 3BLK is selected, character signals can be separated color specification. (4) Output selection To set the output format of the character signal where the setting of the output pin is RGB + V C1 + VC2 (setting the output format of the character signal is invalid where the setting of the output pin is RGB + 3BLK). When an on-screen character display IC is used in a video camera, some items of information (such as date and title) are displayed on the video tape, and the others (such as battery alarm, focus, and counter indication) are only displayed in the view finder. The µPD6467 can select these items of information in row or half-row units by using the output pin. Select the output format from three types: option A, option B, and option C (when 3BLK is selected, however, be sure to select option B).

µPD6467 Data Sheet S14455EJ1V0DS00 (5) Character color reversal specification selection To select the specifications when the character color is reversed (valid only for RGB output).

• Black character: Outputs an area with dots in black and prohibits framing.
• White character: Outputs an area with dots in white and prohibits framing. (6) Function selection To select either of the character blinking or character left/right reversal functions. (7) External clock frequency selelction The external clock frequency 2 divided function is built in the µPD6467.
• ×1 frequency mode: External clock frequency is not divided by 2 in the µPD6467.
• ×2 frequency mode: External clock frequency is divided by 2 in the µPD6467. When the dot clock control bit (OSC) is “1 (External clock input)”, this function is able to use. Example If ×2 frequency mode is selected, and the external input frequency is 14 MHz, the internal dot clock frequency is become to 7 MHz. The default setting assumed on power application is as follows: (1) Dot clock = LC oscillation (2) Vertical display start position = 3-row unit (3) Pin selection = RGB + V C1 + VC2 (4) Output selection = Option B (5) Character color reversal specification selection = Black characters (6) Function selection = Character blinking (7) External clock frequency selection = ×1 frequency mode

µPD6467 Data Sheet S14455EJ1V0DS00

1.2 Application Block Diagram

Example of application in a video camera (1) (in the case of RGB + VC1 + VC2 ) (When VR , VG , VB, VBLK , VC1 , BLK1, VC2 , and BLK2 pins are used) DATA CLK CS PCL Hsync Vsync RGB VC2 VC1 Character mixing circuit Video Video+character Character mixing circuit Color view finder Recording block (deck block) PD6467 RGB : VR , VG , VB, VBLK VC1 : VC1 , BLK1 VC2 : VC2 , BLK2 Character mixing circuit Monitor pin block (video signal output) µ Microcontroller Example of application in a video camera (2) (RGB + 3BLK (RGB compatible BLK)) (When VR , VG , VB, RBLK , GBLK , and BBLK pins are used) DATA CLK CS PCL Hsync Vsync R G B Video Video+character Character mixing circuit Color view finder Recording block (deck block) Monitor pin block (video signal output) PD6467 R : VR , RBLK G : VG , GBLK B : VB, BBLK Video Video Character mixing circuit Character mixing circuit µ Microcontroller

µPD6467 Data Sheet S14455EJ1V0DS00

1.3 Display with RGB + VC1 + VC2 Pins

The µPD6467 has three output options: A, B, and C. The following figure shows the output with each option specified (the output is controlled by an output pin control command (refer to 3.11 Output Pin Control Command)). Output pin control command (with MSB first (The command is input from the MSB (D15).) (because this command is a 2-byte command, input of 16 bits is necessary when this command is input more than once successively.) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

10011100 O D 1 O D 0 00 A R 3 A R 2 A R 1 A R 0

(MSB) (LSB) Row specification bits Function Specifies row 0. Specifies row 1. Specifies row 11. Setting prohibited AR3 AR2 AR1 AR0 Output pin control bits Pin output VC1 : Outputs specified row, VC2 : Fixed to low level VC1 : Fixed to low level, VC2 : Outputs specified row OD1 OD0 Option A Output pin control bits Pin output VC1 : Outputs all rows, VC2 : Fixed to low level VC1 : Outputs all rows, VC2 : Outputs specified row OD1 OD0 Option B Output pin control bits Pin output VC1 : Outputs columns 0-27, VC2 : Fixed to low level VC1 : Outputs columns 0-11, VC2 : Outputs columns 12-27 VC1 : Outputs columns 12-27, VC2 : Outputs columns 0-11 VC1 : Fixed to low level, VC2 : Outputs columns 0-27 OD1 OD0 Option C

• Row specification control Specify whether the character signal is output to the VC1 or VC2 pin in row units (or 12-column, 16-column units).
• Output pin control The output of the VC1 and VC2 pins can be selected from three types, A, B, and C, by using the initial status setting command (the blanking signal is output in the same manner).

µPD6467 Data Sheet S14455EJ1V0DS00 Output with option A Output pin control bit OD1 OD0 Pin output

00 V C1 : Outputs specified row, VC2 : Fixed to low level (1)

01 V C1 : Fixed to low level, VC2 : Outputs specified row (2)

Output Character signal Background signal (with background specified) In the case of (1) VC1 output Outputs character signal resulting from Outputs background signal to area other ORing VR , VG , and VB pins (specified row). than that specified by VC2 . However, character specified by VC2 is not output. VC2 output Fixed to low level (specified row) Outputs background signal to only area specified by VC2 In the case of (2) VC1 output Fixed to low level (specified row) Outputs background signal to area other than that specified by VC2 VC2 output Outputs character specified by VC2 Outputs background signal to only area (specified row) specified by V C2 Output with option B Output pin control bit OD1 OD0 Pin output

00 V C1 : Outputs all rows, VC2 : Fixed to low level (1)

01 V C1 : Outputs all rows, VC2 : Outputs specified row (2)

Output Character signal Background signal (with background specified) In the case of (1) VC1 output Outputs character signal resulting from Outputs background signal to area other ORing VR , VG , and VB pins (all rows). than that specified by VC2 . However, character specified by VC2 is not output. VC2 output Fixed to low level (specified row) Outputs background signal to only area specified by VC2 . In the case of (2) VC1 output Outputs character signal resulting from Outputs background signal to area other ORing VR , VG , and VB pins (all rows). than that specified by VC2 . However, character specified by VC2 is not output. VC2 output Outputs character specified by VC2 Outputs background signal to only area (specified row). specified by V C2 .

µPD6467 Data Sheet S14455EJ1V0DS00 Output with option C Output pin control bit OD1 OD0 Pin output

00 V C1 : Outputs columns 0-27, VC2 : Fixed to low level (1)

01 V C1 : Outputs columns 0-11, VC2 : Outputs columns 12-27 (2)

10 V C1 : Outputs columns 12-27, VC2 : Outputs columns 0-11 (3)

11 V C1 : Fixed to low level, VC2 : Outputs columns 0-27 (4)

Output Character signal Background signal (with background specified) In the case of (1) VC1 output Outputs character signal resulting from Outputs background signal to area other ORing VR , VG , and VB pins (columns 0-27 of than that specified by VC2 . specified row). However, character specified by VC2 is not output. VC2 output Fixed to low level (specified row) Outputs background signal to only area specified by VC2 . In the case of (2) VC1 output Outputs character signals resulting from Outputs background signal to area other ORing VR , VG , and VB pins (columns 0-11 of than that specified by VC2 . specified row). However, character specified by VC2 is not output. VC2 output Outputs character specified by VC2 (columns Outputs background signal to only area 12-27 of specified row). specified by V C2 . In the case of (3) VC1 output Outputs character signal resulting from Outputs background signal to area other ORing VR , VG , and VB pins (columns 12-27 of than that specified by VC2 . specified row). However, character specified by VC2 is not output. VC2 output Outputs character specified by VC2 (columns Outputs background signal to only area 0-11 of specified row). specified by V C2 . In the case of (4) VC1 output Fixed to low level (specified row) Outputs background signal to area other than that specified by VC2 . VC2 output Outputs character specified by VC2 (columns Outputs background signal to only area 0-27 of specified row). specified by V C2 . The signal of the character specified by VC2 is not output from the RGB or VC1 output channel, but the background is output as described above. When the µPD6467 is set to output RGB, VC1 , or VC2 signal, the following setting can be performed as well as the above output control.

• Independent ON/OFF control of character display of each channel (3-channel independent display ON/OFF command)
• Independent background control of each channel (3-channel background control command)

µPD6467 Data Sheet S14455EJ1V0DS00

1.3.1 Character signal output with output select option A

Whether a signal is output to the character signal output pin VC1 in row units can be specified by the OD0 bit that selects an output pin. The VC2 output can be specified in character units, and the VC1 outputs only characters for which the VC2 in the rows for which the OD0 bit is set to 1. The character specified by VC2 is not output to the RGB and VC1 output. Display example (to use VC2 channel for information for recording) REC TAPE BATT 0000 AM 11:30 2000. 2.22 YOKOHAMA BAY BRIDGE Displayed information such as alarm and tape counter Recording information such as date and title Example of view finder display (RGB and VC2 output) Output example REC TAPE BATT 0000 RGB character output (color character) Character output of VC2 channel (specified row, character specified by VC2 ) AM 11:30 2000. 2.22 YOKOHAMA BAY BRIDGE REC TAPE BATT 0000 Character output of VC1 channel (specified row)

• Character information on the row specified by clearing the OD0 bit to 0 is output from V C1 . However, the characterspecified by VC2 is not output.
• The row specified by setting the OD0 bit to 1 is not output (fixed to low level).
• The row specified by clearing the OD0 bit to 0 is not output (fixed to low level).
• Only the character information specified by VC2 on the row specified by setting the OD0 bit to 1 is output from VC2 .
• The character specified to VC2 is not output.

µPD6467 Data Sheet S14455EJ1V0DS00

1.3.2 Character signal output with output select option B

The VC1 outputs characters of all rows regardless of setting of the OD0 and OD1 bits. The VC2 output can be specified in character units, and the VC2 outputs only characters for which the VC2 in the rows for which the OD0 bit is set to 1. The character specified to VC2 is not output to the RGB and VC1 output. Display example (to use VC2 channel for information for recording) REC TAPE BATT 0000 AM 11:30 2000. 2.22 YOKOHAMA BAY BRIDGE Displayed information such as alarm and tape counter Recording information such as date and title Recording information at the leftmost position (e.g., weather).RAIN Example of view finder display (RGB and VC2 output) Output example REC TAPE BATT 0000 RGB character output (color character) Character output of VC2 channel (specified row, character specified to VC2 ) AM 11:30 2000. 2.22 YOKOHAMA BAY BRIDGE REC TAPE BATT 0000 Character output of VC1 channel (all rows) RAIN

• The character information on all the rows is output from VC1 regardless of the OD0 bit. However, the character specified to V C2 is not output.
• Only the character information specified to VC2 on the row specified by setting the OD0 bit to 1 is output from VC2 .
• The character information specified to VC2 is not output on the row specified by clearing the OD0 bit to 0 is not output.
• The character specified to V C2 is not output.

µPD6467 Data Sheet S14455EJ1V0DS00

1.3.3 Character signal output with output select option C

Columns 0 through 11, and 12 through 27 on each row can be output to the VC1 and VC2 pins by using the OD0 and OD1 bits of the “output pin control command”. Display example TAPE BATT AM 11:30 2000. 2.22 Displayed information such as alarm and tape counter Recording information such as date and title0000 REC 0 11 12 27 Example of view finder display YOKOHAMA BAY BRIDGE Output example TAPE BATT RGB character output (color character) Character output of VC2 channel (character specified by VC2 ) AM 11:30 2000. 2.22 YOKOHAMA BAY BRIDGE TAPE BATT Character output of VC1 channel (specified row) 0000 REC 0000 REC

• In the case of setting OD1 bit to 0, the VC1 outputs the characters of columns 0 to 27 in specified rows for which the OD0 bit is set to 0, or the characters of columns 0 to 11 in specified rows for which the OD0 bit is set to 1, excluding the characters for which the V specified.
• In the case of setting OD1 bit to 1, the VC1 outputs the characters of columns 12 to 27 in specified rows for which the OD0 bit is set to 0, and the rows for which the OD0 bit is set to 1 are not output (the V C1 pin is fixed to low level), excluding the characters for which the V C2 specified.
• In the case of setting OD0 bit to 0, the VC2 outputs the characters of columns 0 to 11 in specified rows for which the OD1 bit is set to 1, and the rows for which the OD1 bit is set to 0 are not output (the V C2 pin is fixed to low level).
• In the case of setting OD0 bit to 1, the VC2 outputs the characters of columns 12 to 27 in specified rows for which the OD1 bit is set to 0, or the characters of columns 0 to 27 in specified rows for which the OD1 bit is set to 1.
• The character specified to V C2 is not output.

µPD6467 Data Sheet S14455EJ1V0DS00

1.3.4 Displaying characters specified by VC2

The characters specified by VC2 by the display character control command are not output to the RGB and VC1 output channels (the RGB and VC1 output channels displayNote the same manner as when Display Off Data is written). Therefore, even if a background is specified by the RGB and VC1 output channel (no background/filled background), no background is displayed at the specified portion. Note The display is slightly different from Display Off Data. Filling data: Character filling all 12 × 18 dots

• When Display Off Data is displayed with RGB, VC1 , and VC2 channel In the case of Display Off Data, framing (or background, if any) of adjacent characters is displayed with the framing or background overlapping the area of Display Off Data by one dot of the minimum size (the framing overlaps the area of Display Off Data, when there are dots at the leftmost or rightmost position of the adjacent character area).
• Displaying character area specified by V C2 with RGB and VC 1 channels In the case of a character specified by VC2 , the framing of the adjacent characters is displayed with the framing overlapping the VC2 -specified character area by one dot of the minimum size, but the background does not overlap to the VC2 -specified area.
• Displaying VC2 -specified character area with VC2 channel Even if the VC2 -specified character exists with the VC2 output, the framing also overlaps the adjacent character area, but the background does not (the framing overlaps the V C2 -specified character area, when there are dots at the leftmost or rightmost position of the adjacent character area).
• If VC2 character specification area exists at the edge of display area (The figure shows the leftmost position of the display area. The same applies to the rightmost position of the display area.) Portion output with framing or background overlapping (Width is 1 dot of the minimum character width.) Portion where framing overlaps Portion where background overlaps (1)-(5) (2)-(5) The background is not output overlapping the VC2 -specified character area. Filling Data Display Off Data Filling Data Filling Data VC2 -specified character area Filling Data Display Off Data Display Off Data VC2 -specified character area Filling Data Filling Data Filling Data Filling Data (1) (3) (4) (5) (2)

µPD6467 Data Sheet S14455EJ1V0DS00 2. COMMAND

2.1 Command Format

Control commands can be serially input in 8-bit units. The word length of a command is variable. Three types of commands are available: 1-byte commands that consist of 8 bits including the instruction and data, 2-byte commands, and 2-byte successive commands that can be input in an abbreviated form. Inputting command data with the MSB first or LSB first can be selected by using the CMDCT pin. When the CMDCT pin is high, the data is input with the MSB first; when it is low, the data is input with the LSB first.

2.2 Command List

(1) MSB first 1-byte commands (MSB) Function D7 D6 D5 D4 D3 D2 D1 D0 Video RAM batch clear 00000000 Display control 0001 D O L C B L 1 B L 0 Background color/frame color control0010R G B B F C 3-channel independent display ON/OFF 01110 D O A D O B D O C Character color reverse ON/OFF 0111100 BCRE Blue back ON/OFF 01111 C L R 0 B B Character address bank select 0111111 B C Output switch control 0 1 0 S3A S3B SW4 SW2 SW1 2-byte commands (MSB) Function D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Character display position control100000 V 4 V 3 V 2 V 1 V 0 H 4 H 3 H 2 H 1 H 0 Write address control 1000100 A R 3 A R 2 A R 1 A R 0 A C 4 A C 3 A C 2 A C 1 A C 0 Output pin control 10011100 O D 1 O D 0 00 A R 3 A R 2 A R 1 A R 0 Character size control 100110 S V 1 S V 0 S H 1 S H 0 00 A R 3 A R 2 A R 1 A R 0 3-channel background control 1011001 B A 1 B A 0 B F A B B 1 B B 0 B F B B C 1 B C 0 B F C Initial status setting 101101 E C K 00 B R R S O P 1 O P 0 C O C V S T O S C Test modeNote 10110000 T 7 T 6 T 5 T 4 T 3 T 2 T 1 T 0 Note Must not be used. 2-byte successive command (MSB) Function D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Display character control 1 1 RV R G B BL V C2 C7 C6 C5 C4 C3 C2 C1 C0

µPD6467 Data Sheet S14455EJ1V0DS00 (2) LSB first 1-byte commands (LSB) Function D0 D1 D2 D3 D4 D5 D6 D7 Video RAM batch clear 00000000 Display control BL0 BL1 LC DO 1000 Background color/frame color control BFC B G R 0100 3-channel independent display ON/OFFD O C D O B D O A 01110 Character color reverse ON/OFF BCRE 0011100 Blue back ON/OFF BB 0 CLR 11110 Character address bank select BC 1111110 Output switch control SW1 SW2 SW4 S3B S3A 0 1 0 2-byte commands (LSB) Function D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Character display position control V3 V4000001 H 0 H 1 H 2 H 3 H 4 V 0 V 1 V 2 Write address control AR3 0010001 A C 0 A C 1 A C 2 A C 3 A C 4 A R 0 A R 1 A R 2 Output pin control 00111001 A R 0 A R 1 A R 2 A R 3 00 O D 0 O D 1 Character size control SV0 SV1 011001 A R 0 A R 1 A R 2 A R 3 00 S H 0 S H 1 3-channel background control BA1 1001101 B F C B C 0 B C 1 B F B B B 0 B B 1 B F A B A 0 Initial status setting 0 ECK 101101 O S C V S T C O C O P 0 O P 1 R S B R 0 Test modeNote 00001101 T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7 Note Must not be used. 2-byte successive command (LSB) Function D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 Display character control V C2 B L B G R R V 1 1 C 0C 1C 2C 3C 4C 5C 6C 7

µPD6467 Data Sheet S14455EJ1V0DS00

2.3 Power-ON Clear Function

Because the internal status of the IC is undefined on power application, execute power-ON clear by lowering the PCL pin for the duration described below. Command setting on power-ON clear is as follows:

• Clears test mode
• Default setting of initial status (Refer to 3.14 Initial Status Setting Command.)
• Clears all character data (12 rows, 28 columns) of video RAM (Display Off Data (FEH)). No data blinks.
• Video RAM write address (row 0, digit 0)
• Standard size for all rows as character size (SV1, SV0, SH1, SH0) = (0, 0, 0, 0)
• All rows specified for output pin selection (OD1, OD0) = (0, 0)
• Display OFF, LC oscillation ON, blinking OFF
• Display of each channel OFF
• No background and framing for all three channels
• Character color reversing OFF
• Character left and right reverse OFF
• Blue back OFF
• Low-order (0) bank for character address
• Output switch control is only SW1 = ON, others OFF (S3A, S3B, SW4, SW2, SW1) = (1, 0, 0, 0, 1) The time required for power-ON clear can be calculated by the following expression. Do not input any command during this time. t (Time required for power-ON clearing) = t PCLL Note + Video RAM clear time = 10 (µs) + 10 (µs) + 12/fOSC (MHz) × 336 = 10 (µs) + 10 (µs) + 24/fOSC2 (MHz) × 336 fOSC (MHz): LC oscillation frequency or external input clock frequency (when ×1 frequency mode is selected) fOSC2 (MHz): External input clock frequency (when ×2 frequency mode is selected) Note Refer to Power-ON Clear Specifications in 6. ELECTRICAL CHARACTERISTICS . To clear the video RAM, the dot clock (OSCIN pin) must be input. Be sure to input the clock when the input of an external clock is selected.

µPD6467 Data Sheet S14455EJ1V0DS00 3. DETAILS OF COMMANDS

3.1 Video RAM Batch Clear Command

This command can be used to clear the video RAM with a single command (regardless of whether the MSB or LSB comes first) (MSB) (LSB) D7 D6 D5 D4 D3 D2 D1 D0 00000000 The following contents are set by the video RAM batch clear command.

• Clears all the character data (Display Off Data (FEH)) of the video RAM (12 rows, 28 columns). No data blinks.
• Video RAM write address: (Row 0, column 0)
• Standard size for all rows as character size (SV1, SV0, SH1, SH0) = (0, 0, 0, 0)
• All rows specified for output pin selection (OD1, OD0) = (0, 0)
• Display OFF, LC oscillation ON, blinking OFF The time required for clearing the video RAM can be calculated by the following expression. Do not input any command during this time. t (Time required for video RAM clearing) = Video RAM clear time = 10 ( µs) + 12/fOSC (MHz) × 336 = 10 (µs) + 24/fOSC2 (MHz) × 336 fOSC (MHz): LC oscillation frequency or external input clock frequency (when ×1 frequency mode is selected) fOSC2 (MHz): External input clock frequency (when ×2 frequency mode is selected) To clear the video RAM, the dot clock (OSCIN pin) must be input. Be sure to input the clock when the input of an external clock is selected. Remark This command resets the hardware of the IC by inputting a signal to the PCL pin. While initializing the IC including clearing the video RAM and the test mode, the video RAM batch clear command executes software reset to initialize the IC, and does not clear the test mode.

µPD6467 Data Sheet S14455EJ1V0DS00

3.2 Display Control Command

This command controls the display output, LC oscillation, blinking the characters, and left to right reverse. (1) With MSB first (The command is input from MSB (D7).) D7 D6 D5 D4 D3 D2 D1 D0

0001 D O L C B L 1 B L 0

(MSB) (LSB) Blinking control bit (screen unit) Function Blinking OFF Blinking frequency: approx. 2 Hz Blinking frequency: approx. 1 Hz Blinking frequency: approx. 0.5 Hz BL0 LC oscillation control bit Function LC oscillation OFF LC oscillation ON LC Character display ON/OFF control bit Function Display OFF Display ON DO Left to right reverse control bit Function Character left to right reverse OFF Character left to right reverse ON BL1 BL1 BL0 With blinking character selectedNote With character left and right reverse selected Note Note Set with the initial setting command.

µPD6467 Data Sheet S14455EJ1V0DS00 (2) With LSB first (Use of each bit is the same as (1). The command is input from LSB (D0).) (LSB) (MSB) D0 D1 D2 D3 D4 D5 D6 D7 B L 0 B L 1 L C D O 1000

• Blinking control (screen units) The function selected by the initial setting command is controlled.
• Blinking control (screen units) Whether the characters written to the video RAM blink or not is controlled in screen units. The character specified to blink by the display character control command blinks. The blinking ratio is 1:1, and the blinking frequency can be selected from three types.
• Left to right reverse control The character specified to be reversed left to right by the display character control command is reversed (this is valid only if character left to right reverse is selected by the initial setting command). Display example of character specified to be reversed left to right (character “F” is displayed) When left to right reverse is OFF When left to right reverse is ON
• LC oscillation control The oscillation circuit can be turned ON/OFF by the oscillation control bit. Oscillation is stopped during the period in which the characters are not displayed, to reduce the power consumption. Nothing can be written to the video RAM while the oscillation is stopped. To write data to the video RAM, be sure to turn ON oscillation.

µPD6467 Data Sheet S14455EJ1V0DS00 Cautions 1. When LC oscillation is used : Oscillation is synchronized with Hsync when the character display is ON, and is stopped while Hsync is low. When character display is OFF, oscillation continues regardless of Hsync. 2. When external clock is input : When an external clock is used, the clock is supplied to the IC’s internal circuitry when oscillation is turned ON. When oscillation is OFF, the clock supply to the internal circuitry is stopped.

• Character display ON/OFF control Character display output can be turned ON/OFF. The display is turned ON/OFF in synchronization with the falling of Hsync.

µPD6467 Data Sheet S14455EJ1V0DS00

3.3 Background Color/Frame Color Control Command

This command specifies the background color and frame color. This command is valid when filling of the background, blank background, or framing is specified. (1) With MSB first (The command is input from MSB (D7).) D7 D6 D5 D4 D3 D2 D1 D0 0010R G B B F C (MSB) (LSB) Background color control bit Function Black Blue Green Cyan Red Magenta Yellow White R Frame color control bit Function Frame color: Black Frame color: White BFC G B (2) With LSB first (Use of each bit is the same as (1). The command is input from LSB (D0).) (LSB) (MSB) D0 D1 D2 D3 D4 D5 D6 D7 B F C B G R0100

• Frame color control The frame color (white/black) can be selected in screen units (RGB output). If the frame is specified with VC1 and VC2 output, the frame color is fixed to black.
• Background color control The background color can be selected (from eight colors) in screen units (RGB output). If the background is specified with V C1 and VC2 output (blank background or filled background), the background color is fixed to black.

µPD6467 Data Sheet S14455EJ1V0DS00 3.4 3-Channel Independent Display ON/OFF Command This command can turn ON/OFF the display of character output of 3 channels independently. (1) With MSB first (The command is input from MSB (D7).) D7 D6 D5 D4 D3 D2 D1 D0

01110 D O A D O B D O C

(MSB) (LSB) Control bit DOA DOB DOC DOA DOB DOC Control bit Function RGB display OFF RGB display ON V C1 display OFF VC1 display ON VC2 display OFF VC2 display ON Function Character display OFF Character display ON Don't care Don't care With support of RGB/V C1 /VC2 output selected With R/G/B/3BLK output selected (2) With LSB first (Use of each bit is the same as (1). The command is input from LSB (D0).) (LSB) (MSB) D0 D1 D2 D3 D4 D5 D6 D7 D O C D O B D O A 01110

• Displaying the character signal of the 3 channels (RGB, VC1 , and VC2 ) can be independently turned ON/ OFF. When RGB + RGB compatible BLK is selected, it is controlled by the display ON/OFF command.
• Turning ON display each output channel by using this command is valid only when the display is turned ON by the display control command.
• If the display is turned OFF by the display control command, the display remains OFF even if it is specified to be ON by this command.

µPD6467 Data Sheet S14455EJ1V0DS00

3.5 Character Color Reverse ON/OFF Command

This command specifies reversal of character color in screen units. (1) With MSB first (The command is input from MSB (D7).) D7 D6 D5 D4 D3 D2 D1 D0

0011100 BCRE

(MSB) (LSB) BCRE Function Character color not reversed Character color reversed Character color reverse control bit (2) With LSB first (Use of each bit is the same as (1). The command is input from LSB (D0).) (LSB) (MSB) D0 D1 D2 D3 D4 D5 D6 D7 BCRE 0011100 The color of the character specified by the display character control command is reversed for the whole screen with the reverse specifications (character color: black or white) specified by the initial status setting command. Example of display of reversed character (example of reversing character “I”) or No framing Framing Color reverse OFF Color reverse ON Character color: Black, no framing Character color: White, no framing Selected from two types by initial setting command Character color with reverse OFF Character color: White, black frame or Specification of framing is invalid for black character. Specification of framing is invalid for white character. Character color with reverse OFF

µPD6467 Data Sheet S14455EJ1V0DS00 The character color/background color (with blank background or filled background) can be selected from eight types in the case of RGB output when reversing character color is specified to be OFF. In the case of VC1 and VC2 , the character color is white and the background color is black. The Display Off Data is not affected even when inverted. If Blank Data is reversed, it is filled with the character color originally specified. The character color and the color of the framing in the above figure are valid with the RGB. Only black and white are displayed in the case of V C1 and VC2 . In the case of VC1 and VC2 , framing in the character color reverse area is invalid (same as the µPD6461, 6462 and 6466).

µPD6467 Data Sheet S14455EJ1V0DS00

3.6 Blue Back ON/OFF Command

This command turns ON/OFF the blue back function in screen units. (1) With MSB first (The command is input from MSB (D7).) (MSB) (LSB) D7 D0 0B B CLR Blue back control bit BB Function Blue back OFF Blue back ON Color specification bit CLR Function Blue White (2) With LSB first (Use of each bit is the same as (1). The command is input from LSB (D0).) (LSB) (MSB) D0 D1 D2 D3 D4 D5 D6 D7 B B 0 C L R 11110 By turning ON the blue back function, the character, framing, and area where no background is output are all displayed in blue. This command is valid only for RGB output.

µPD6467 Data Sheet S14455EJ1V0DS00

3.7 Character Address Bank Select Command

This command selects the area of the character address specified by the character address specification bit of the display character control command. (1) With MSB first (The command is input from MSB (D7).) D7 D6 D5 D4 D3 D2 D1 D0

0111111 B C

(MSB) (LSB) Character address bank select control bit Function Low-order bank (0) High-order bank (1) BC (2) With LSB first (Use of each bit is the same as (1). The command is input from LSB (D0).) (LSB) (MSB) D0 D1 D2 D3 D4 D5 D6 D7 B C 1111110 If the low-order bank (0) is specified by the 8-bit data (the second byte of the display character control command) of the character data, character addresses 00H through FFH (common addresses 000H through 0FFH) of the low-order (0) bank are specified. If the high-order bank (1) is specified, character addresses 00H through FFH (common addresses 100H through 1FFH) of the high-order (1) bank are specified. If FEH is specified at the character address of the display character control command for both banks, the command can be used as the Display Off code. If FFH is specified, it can be used as a 2-byte successive command end code.

µPD6467 Data Sheet S14455EJ1V0DS00

3.8 Output Switch Control Command

This command controls ON/OFF of SW1 through SW4, and selects the output format of RGB and VC1 . (1) With MSB first (The command is input from MSB (D7).) (MSB) (LSB) D7 D0

0 SW1

Controlled by row unit data (OD1) OD1 = 0 : OFF, OD1 = 1 : ON S3B OFF regardless of OD1 ON regardless of OD1 (2) With LSB first (Use of each bit is the same as (1). The command is input from LSB (D0).) (LSB) (MSB) D0 D1 D2 D3 D4 D5 D6 D7 SW1 SW2 SW4 S3B S3A 0 1 0

µPD6467 Data Sheet S14455EJ1V0DS00 Output format in each switch status Mode SW1 SW2 SW4 SW3 RGB V C1 VC2

1 ON OFF OFF ON RGB V C1 VC2

2 ON OFF OFF OFF RGB V C1 VC2

3 ON ON OFF ON RGB+V C2 VC1 VC2

4 ON ON OFF OFF RGB V C1 VC2

5 ON OFF ON ON RGB V C1 +V C2 VC2

6 ON OFF ON OFF RGB V C1 VC2

7 ON ON ON ON RGB+V C2 VC1 +V C2 VC2

8 ON ON ON OFF RGB V C1 VC2

9 OFF ON ON ON RGB+V C2 VC2 VC2

10 OFF ON ON OFF RGB V C1 VC2

11 OFF OFF ON ON RGB V C2 VC2

12 OFF OFF ON OFF RGB V C1 VC2

13 OFF OFF OFF ON RGB V C1 VC2

14 OFF OFF OFF OFF RGB V C1 VC2

15 OFF ON OFF ON RGB+V C2 VC1 VC2

16 OFF ON OFF OFF RGB V C1 VC2

Caution The V C2 character is output by each channel as follows. The VC2 outputs only VC2 regardless of the status of SW1 to SW4 (same as µPD6461, 6462 and 6466).

• If RGB channel is RGB, RGB + VC2 : Not controlled at all by output pin control command.
• If VC1 channel is VC1 , VC1 + VC2 : Output pins at VC1 side are controlled.
• If VC1 channel is VC2 : Output pins at VC2 side are controlled. Image of Internal output and Terminal output RBG output SW1 SW3 SW4 SW2 VC1 output VC2 output RBG channel output VC1 channel output VC2 channel output These switches are controlled by 3-channel independent display ON/OFF command.

µPD6467 Data Sheet S14455EJ1V0DS00

3.9 Character Display Position Control Command

This command can be used to set the character display start position in 32 steps in units of 3 dots in the horizontal direction, and in 32 steps in units of 3 rows in the vertical direction (because this command is a 2-byte command, input of 16 bits is necessary when this command is input more than once successively). (1) With MSB first (The command is input from MSB (D15).) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

100000 V 4 V 3 V 2 V 1 V 0 H 4 H 3 H 2 H 1 H 0

(MSB) (LSB) Horizontal display start position control bit FunctionH4 H0 Time from rising of Hsync ( s) (22+3×0)/fOSC (MHz) (45+6×0)/fOSC2 (MHz) H3 H2 H1 00 0 0 0 00 0 0 0 11 1 1 1 Time from rising of Hsync ( s) (22+3×1)/fOSC (MHz) (45+6×1)/fOSC2 (MHz) Time from rising of Hsync ( s) (22+3×31)/f OSC (MHz) (45+6×31)/fOSC2 (MHz) Remark fOSC : LC oscillation frequency or external input clock frequency (×1 frequency mode) fOSC2 : External input clock frequency (×2 frequency mode) Vertical display start position control bit FunctionV4 3H ×0+2H (9H×0+2H) from rising of Vsync 3H ×1+2H (9H×1+2H) from rising of Vsync 3H ×31+2H from rising of Vsync Remarks 1. H: row 2. ( ): If 9H unit is selected by the initial status setting command. µ µ µ (2) With LSB first (Use of each bit is the same as (1). The command is input from LSB (D0).) (LSB) (MSB) D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 V 3 V 4 000001 H 0 H 1 H 2 H 3 H 4 V 0 V 1 V 2

µPD6467 Data Sheet S14455EJ1V0DS00

• Horizontal display start position control (1) In case of LC oscillation or Exernal input clock ×1 frequency mode The horizontal display start position can be set in 32 steps in units of 3 dots (3/fOSC (MHz)) 22 clocks (22/fOSC (MHz)) after the rising of the horizontal sync signal input to the Hsync pin (fOSC : LC oscillation frequency or external input clock frequency). (2) In case of External input clock ×2 frequency mode The horizontal display start position can be set in 32 steps in units of 3 dots (6/fOSC2 (MHz)) 45 clocks (22/fOSC2 (MHz)) after the rising of the hirizontal sync signal input to the Hsync pin.
• Vertical display start position control The vertical display start position can be set in 32 steps in units of 3 or 9 rows (refer to 3.14 Initial Status Setting Command ) from the rising of the vertical sync signal input to the Vsync pin. B A Vertical sync signal (Vsync) Horizontal sync signal (Hsync) Display area: 12 rows, 28 columns A : 3H × (24V4 + 23V3 + 22V2 + 21V1 + 20V0) + 2H B : (1) In case of LC oscillation or External input clock ×1 frequency mode (2) External input clock ×2 frequency mode × (24H 4 + 23 H 3 + 22H 2 + 21H 1 + 20H 0) +fOSC (MHz) fosc(MHz) 9H if 9H unit is selected by the initial status setting command. fOSC : LC oscillation frequency or external input clock frequency (×1 frequency mode) × (24H 4 + 23 H 3 + 22H 2 + 21H 1 + 20H 0) +fOSC2 (MHz) fOSC2 (MHz) fOSC2 : External input clock frequency (×2 frequency mode) H : row

µPD6467 Data Sheet S14455EJ1V0DS00

3.10 Write Address Control Command

This command is used to specify a write address when characters are written to the display area (video RAM) of 12 rows and 28 columns (because this command is a 2-byte command, input of 16 bits is necessary when this command is input more than once successively). (1) With MSB first (The command is input from MSB (D15).) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1000100 A R 3 A R 2 A R 1 A R 0 A C 4 A C 3 A C 2 A C 1 A C 0

(MSB) (LSB) Write column address control bit Function Sets column 0 Sets column 1 Sets column 27 Setting prohibited AC4 AC3 AC2 AC1 Write row address control bit Function Sets row 0 Sets row 1 Sets row 11 Setting prohibited AR3 AR2 AR1 AR0 AC0 (2) With LSB first (Use of each bit is the same as (1). The command is input from LSB (D0).) (LSB) (MSB) D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 A R 3 0010001 A C 0 A C 1 A C 2 A C 3 A C 4 A R 0 A R 1 A R 2

• Write column address control One row consists of 28 columns in the horizontal direction. Specify to which column data is to be written.
• Write row address control One column consists of 12 rows in the vertical direction. Specify to which row data is to be written.

µPD6467 Data Sheet S14455EJ1V0DS00

3.11 Output Pin Control Command

This command selects the format of pin output of the option (A, B, or C) specified by the initial status setting command (because this is a 2-byte command, input of 16 bits is necessary if this command is input more than once successively). Remark This command is invalid when RGB + RGB compatible BLK output is selected. (1) With MSB first (The command is input from MSB (D15).) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 (MSB) (LSB) Row specification bit Function Sets row 0 Sets row 1 Sets row 11 Setting prohibited AR3 AR2 AR1 AR0 Output pin control bit Pin output VC1 : Outputs specified row, VC2 : Fixed to low level VC1 : Fixed to low level, VC2 : Outputs specified row OD1 OD0 Option A Output pin control bit Pin output VC1 : Outputs all rows, VC2 : Fixed to low level VC1 : Outputs all rows, VC2 : Outputs specified row OD1 OD0 Option B Output pin control bit Pin output VC1 : Outputs columns 0-27, VC2 : Fixed to low level VC1 : Outputs columns 0-11, VC2 : Outputs columns 12-27 VC1 : Outputs columns 12-27, VC2 : Outputs columns 0-11 VC1 : Fixed to low level, VC2 : Outputs columns 0-27 OD1 OD0 Option C (2) With LSB first (Use of each bit is the same as (1). The command is input from LSB (D0).) (LSB) (MSB) D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 00111 0 01 A R 0 A R 1 A R 2 A R 3 00 O D 0 O D 1

• Row specification control Specify to which of the VC1 or VC2 pin the character signal is to be output in row units (or 12-column, 16- column units).
• Output pin control Output of the VC1 and VC2 pin can be selected from A, B, or C by using the initial status setting command (the blanking signal is output in the same manner).

µPD6467 Data Sheet S14455EJ1V0DS00

3.12 Character Size Control Command

The character size can be specified in row units (independently in the horizontal and vertical directions. Because this is a 2-byte command, input of 16 bits is necessary when this command is input more than once successively). (1) With MSB first (The command is input from MSB (D15).) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

100110 S V 1 S V 0 S H 1 S H 0 00 A R 3 A R 2 A R 1 A R 0

(MSB) (LSB) Row specification control bit Function Sets row 0 Sets row 1 Sets row 11 Setting prohibited AR3 AR2 AR1 AR0 Horizontal character size control bit FunctionSH1 1 dot = 1t dots (horizontal standard size) 1 dot = 2t dots (horizontal ×2 size) 1 dot = 3t dots (horizontal ×3 size) 1 dot = 4t dots (horizontal ×4 size) SH0 Vertical character size control bit FunctionSV1 1 dot = 1H (vertical standard size) 1 dot = 2H (vertical ×2 size) 1 dot = 3H (vertical ×3 size) 1 dot = 4H (vertical ×4 size) SV0 Remark 1t dots (µs) = = fOSC : LC oscillation frequency or external input clock frequency (×1 frequency mode) fOSC2 : External input clock frequency (×2 frequency mode) (2) With LSB first (Use of each bit is the same as (1). The command is input from LSB (D0).) (LSB) (MSB) D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 S V 0 S V 1 011001 A R 0 A R 1 A R 2 A R 3 00 S H 0 S H 1

• Row specification control The character size is specified in row units. Which row is specified is controlled.
• Character size control Four steps (16 types) of character size can be selected in the vertical and horizontal directions independently. fOSC (MHz) fOSC2 (MHz)

µPD6467 Data Sheet S14455EJ1V0DS00 3.13 3-Channel Background Control Command This command can be used to independently specify the background for the output of the 3 channels (because this command is a 2-byte command, input of 16 bits is necessary when this command is input more than once successively). (1) With MSB first (The command is input from MSB (D15).) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

1011001 B A 1 B A 0 B F A B B 1 B B 0 B F B B C 1 B C 0 B F C

(MSB) (LSB) VC2 background control bit Function No background Blank background Must not be specified Filled background BC1 BC0 VC2 framing control bit Function Framing OFF Framing ON BFC VC1 background control bit Function No background Blank background Must not be specified Filled background BB1 BB0 VC1 framing control bit Function Framing OFF Framing ON BFB RGB background control bit Function No background Blank background Must not be specified Filled background BA1 BA0 RGB framing control bit Function Framing OFF Framing ON BFA V C2 output VC1 output RGB output (2) With LSB first (Use of each bit is the same as (1). The command is input from LSB (D0).) (LSB) (MSB) D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 B A 1 1001101 B F C B C 0 B C 1 B F B B B 0 B B 1 B F A B A 0

µPD6467 Data Sheet S14455EJ1V0DS00

• Framing control Whether a character is framed is specified in screen units. Framing: If the rightmost or leftmost dots of the dot matrix forming a character are used, the frame is displayed in the adjacent character display area. If the rightmost or leftmost dots of the dot matrix are not used, the frame is displayed on the left or the right of, above, or upper or lower left or right of the character. Even when the top or bottom dot is used, framing does not overlap the line above or below. Dots other than those at the top or bottom of the dot matrix are framed vertically, horizontally, and diagonally. Character dots Framing The size of the framing is fixed to one dot of the minimum size even if the character size changes.
• Background control No background, blank background, or filled background can be selected in screen units. The background color is selected by the background color/framing color control command. No background : Only character data is output. Blank background : The background is displayed in the display area of the characters written to the video RAM and the portion overlapping by one dot of the minimum size from the rightmost and leftmost position of that area. Filled background : In addition to the area where the background is displayed in the blank background mode above, the background is displayed in the areas other than the character display area.
• Background and frame display in the case of RGB + V C1 + VC2 output The portion of the character for which VC2 is specified by the display character control command is not output to the RGB and VC1 channels. Therefore, even if a background (blank background or filled background) is specified for the RGB or VC1 output, no background is displayed in the VC2 -specified area. In addition, no background is displayed at the portion of the character other than those specified by VC2 in the case of VC2 output (for the details of display of VC2 -specified character area for RGB and VC1 output, refer to 1.3 Display with RGB + VC1 + VC2 Pins and 1.3.4 Displaying characters specified by VC2 ). When RGB + RGB compatible BLK output is selected, only the background control bit of RGB output is valid, and the background control bit of V C1 output and VC2 output is invalid (when RGB + RGB compatible BLK output is selected, the VC2 output pin is not used. The VC1 channel outputs the logical sum of the RGB output).

µPD6467 Data Sheet S14455EJ1V0DS00 Display format of background and frame Display example with character XXH Character A XYH Character B YYH Filled Data YZH Blank Data FEH Display Off Data Cannot be changed with mask code option (address fixed)Can be designed with mask code option No background + no frame Display Off Data Blank Data Display Off Data Filled Data Character Video No background + frame Display Off Data Blank Data Display Off Data Filled Data Character Video Frame Eight colors can be selected for the character and background, and two colors (black and white) can be selected for the frame, in screen units.

µPD6467 Data Sheet S14455EJ1V0DS00 Display Off Data Blank Data Display Off Data Blank background + no frame Display Off Data Display Off Data Character Video Filled background + no frame Character Video Blank background + frame Character Video Filled background + frame Filled Data Character Video Display Off Data Blank Data Display Off Data Filled Data Display Off Data Frame Background Frame Background Background Background Blank Data Filled Data Blank Data Display Off Data Filled Data

µPD6467 Data Sheet S14455EJ1V0DS00

3.14 Initial Status Setting Command

This command initializes the operation mode. Execute this command first on power application. To change the initial setting, be sure to execute this command with the display OFF. (1) With MSB first (The command is input from MSB (D15).) Note When the dot clock control bit (OSC) is “1 (External clock input)”, the external clock frequency selection bit (ECK) is able to set “1”. When OSC is “0”, ECK should be set “0”. (2) With LSB first (Use of each bit is the same as (1). The command is input from LSB (D0).) (LSB) (MSB) D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

0 E C K 101101 O S C V S T C O C O P 0 O P 1 R S B R 0

D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

101101 E C K 00 B R R S O P 1 O P 0 C O C V S T O S C

(MSB) (LSB) Vertical display start position control bit Function Vertical display start position setting unit = 3 rows Vertical display start position setting unit = 9 rows VST

1 Output selection control bit

RGB + RGB compatible BLK (3BLK) COC Dot clock control bit Function LC oscillation External clock input OSC Character color reverse control bit FunctionRS Character color: Black (frame specification is invalid) Character color: White (frame specification is valid) Function selection bit FunctionBR Character blinks Character left to right reverse External clock frequency selection bit FunctionECK 1Note ×1 frequency mode ×2 frequency mode

µPD6467 Data Sheet S14455EJ1V0DS00 This command sets the information selected by a mask code option in the µPD6461 and 6462. The default setting is as follows: OSC = 0 : LC oscillation VST = 0 : 3-row units COC = 0 : RGB + V C1 + VC2 (OP1, OP0) = (0, 1) : Option B RS = 0 : Black character BR = 0 : Character blinks ECK = 0 : External input clock ×1 frequency mode

3.15 Display Character Control Command

This command specifies the character data to be written to the video RAM, blinking data, and character color. When inputting this command, turn ON LC oscillation (if the oscillation is OFF, characters cannot be written to the video RAM). This command is a 2-byte successive command. To write character data successively without changing the blinking data, character color, and character address bank, the second character and those that follow can be input in the abbreviated form by using only the low-order 8 bits (D7 through D0). In this case, the write column address is automatically incremented (If a character is written to the 27th column, the next write address is automatically incremented to column 0 (leftmost) on one row below. If characters have been written to the 27th column on the 11th row, the next write address is automatically incremented to column 0 on row 0). Row n+1 Row address ( ) Row address increment Column address ( )

µPD6467 Data Sheet S14455EJ1V0DS00 (1) With MSB first (The command is input from MSB (D15).) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

11 R V R G B B L V C2 C7 C6 C5 C4 C3 C2 C1 C0

(MSB) (LSB) Character specification bit Function Outputs data of 00H Outputs data of 01H Outputs FEH (Display Off Data) FFH (2-byte successive command end code) VC2 output specification bit Function VC2 specification OFF VC2 specification ON VC2 Blinking control bit (character units) Function Character color specification bit Function Black Blue Green Cyan Red Magenta Yellow White R G Character color reverse specification bit Function Character color reverse specification OFF Character color reverse specification ON RV B BL Character does not blink. Character blinks. Left and right reverse character control bit FunctionBL Left and right reverse character specification OFF Left and right reverse character specification ON With character blinking selectedNote With character left and right reverse selectedNote Note Set these bits with the initial setting command.

µPD6467 Data Sheet S14455EJ1V0DS00 (2) With LSB first (Use of each bit is the same as (1). The command is input from LSB (D0).) (LSB) (MSB) D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 VC2 R B B G R R V 1 1 C 0C 1C 2C 3C 4C 5C 6C 7

• Character specification Specify the addresses of the 256 types of characters in each bank. Note, however, that addresses FEH and FFH are respectively fixed to Display Off Data and a 2-byte successive command end code (these addresses are also fixed when characters are changed by using a mask code option, and no characters can be stored to these addresses). The design of the characters can be created by using a mask code option. C2 output specification The character output from the VC2 pin can be specified in character units. The character specified by VC2 is not output from the RGB output or VC1 output channel (this specification is invalid when RGB + RGB compatible BLK output selected).
• Blinking control (character units)Note Whether the character written to the video RAM blinks is specified in character units. Blinking is turned ON/OFF in screen units by using the character display control command (refer to 3.2 Display Control Command ).
• Left to right reverse character specificationNote Left to right reverse can be turned ON/OFF in character units (this specification is valid when left and right reverse is turned ON by the display control command). Note Character blinking or character left to right reverse, whichever selected by the initial setting command, is valid.
• Character color control A character color can be set in units of one character (valid for RGB output only. The color is fixed for the VC1 and VC2 output).
• Character color reverse specification It can be specified whether the color of a character can be reversed or not, in character units. Turning ON/ OFF the character color reverse is specified in screen units by the character color reverse ON/OFF command (refer to 3.5 Character Color Reverse ON/OFF Command).

µPD6467 Data Sheet S14455EJ1V0DS00

3.16 Test Mode

This command is used to test the IC and must not be used for any other purposes. The IC cannot be set in the test mode when the TEST pin (pin 9) is connected to GND. (1) With MSB first (The command is input from MSB (D15).) (MSB) (LSB) D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

10110000 T 7 T 6 T 5 T 4 T 3 T 2 T 1 T 0

(2) With LSB first (Use of each bit is the same as (1). The command is input from LSB (D0).) (LSB) (MSB) D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15

00001101 T 0 T 1 T 2 T 3 T 4 T 5 T 6 T 7

µPD6467 Data Sheet S14455EJ1V0DS00 4. TRANSFERRING COMMANDS 4.1 1-Byte Command D7-D0 With MSB first: The command is input from bit D7.DATA DATA CLK CS D0-D7 With LSB first: The command is input from bit D0. 4.2 2-Byte Command D15-D8 With MSB first 1st byte: D15-D8 2nd byte: D7-D0 DATA D0-D7 D7-D0 D8-D15 1st byte 2nd byte 1st byte 2nd byte DATA CLK CS With LSB first 1st byte: D0-D7 2nd byte: D8-D15 When transferring a 2-byte command, do not make CS high and keep it low between the first and second bytes.

µPD6467 Data Sheet S14455EJ1V0DS00 4.3 2-Byte Successive Commands D15-D8 MSB firstDATA D0-D7 D7-D0 D8-D15 1st byte 2nd byte 1st byte 2nd byte DATA CLK CS LSB first D7-D0 D8-D15 2nd byte 2nd byte The 2-byte successive command writes characters to the video RAM. To successively write characters without changing the blinking data, reverse specification data, and VC2 specification data, first transfer the first byte and then transfer the second byte (character address). To change the contents of the above data, change the contents of the data and then input the command from the first byte after terminating the 2-byte successive command once (by either making CS high or transferring the 2-byte successive command end code). However, the command cannot be transferred successively across banks. When the low-order bank is selected, the command can be transferred successively in a character address range of 000H to 0FFH; when the high-order bank is selected, the character address range is from 100H to 1FFH. It is recommended that characters that are frequently used be stored to both the high-order and low-order banks. To write a character that across the banks, complete successive transfer once, and then transfer the command from the first byte after changing the bank.

µPD6467 Data Sheet S14455EJ1V0DS00

4.4 Successive Input of Command

Transfer each of the 1-byte, 2-byte, and 2-byte successive commands from a microcontroller to the µPD6467 as follows. To transfer a 1-byte or 2-byte command, or a 2-byte successive command with blinking data changed after a 2- byte successive command has been transferred, either make CS high once, or transfer FFH (2-byte successive command end code) at the end of the 2-byte successive command. In the latter case, it is not necessary to make CS high.

4.4.1 When 2-byte successive command end code is not used

Example 1-byte command → 2-byte successive command → 1-byte command DATA CLK CS Make CS low once and then back high again. 2nd byte (D0-D7) MSB first (LSB first) 2nd byte (D8-D15) 00H-FEH (normal character) 2-byte successive command 1st byte (D0-D7) 1-byte command (D0-D7) (D8-D15) 00H-FEH (normal character) D7-D0D7-D0D15-D8D7-D0 D7-D0 1-byte command

4.4.2 When 2-byte successive command end code is used

Example 1-byte command → 2-byte successive command → 1-byte command DATA CLK CS 1-byte command 2nd byte (D0-D7) MSB first (LSB first) 2nd byte (D8-D15) 00H to FFH (normal character) 2-byte successive command 1st byte (D0-D7) 1-byte command (D0-D7) (D8-D15) FFH (2-byte successive command end code) D7-D0D7-D0D15-D8D7-D0 D7-D0 It is not necessary to make CS low and then back high again. Remark By using the 2-byte successive command end code, the CS pin may remain low. However, it is recommended to make CS pin high to improve the noise immunity.

µPD6467 Data Sheet S14455EJ1V0DS00 5. CHARACTER PATTERNS The µPD6467 can display 512 character patterns, including alphanumeric characters, Kanji characters, and symbols, which are stored in the character generator ROM. Each pattern in the character generator ROM can be modified by specifying a mask code option. However, the Display Off Data at character address FEH and 2-byte continuous command end code at FFH cannot be modified because they are fixed in both high-order (1) and low-order (0) banks. Therefore, no character pattern can be input at these addresses. When none of the 12 × 18 dots are filled for a character pattern at addresses 000H to 0FDH and 100H to 1FDH, the character pattern is called Blank Data. Character address FEH in both banks is called Display Off Data. Blank Data and Display Off Data are represented in the same way (with no dots filled) in character patterns (of the µPD6467GR-001) shown on the following pages, but they are different as follows: Character Code Display of Character Area in Each Background Mode No background Minimum background Overall background Blank Data Displays image Displays background Displays background Display Off Data Displays image Displays image only Displays image only (without background) (without background) You cannot specify Display Off Data for addresses other than FEH when using a mask code option. Blank Data, however, can be specified at any address from 000H to 0FDH or 100H to 1FDH (address 0FFH and 1FFH cannot be used because they are fixed to the 2-byte continuous command end code). The character patterns of the µPD6467GR-001 (NEC’s standard model) are shown on the following pages.

µPD6467 Data Sheet S14455EJ1V0DS00 µPD6467GR-001 Character Patterns [039H] [03AH] [03BH]

µPD6467 Data Sheet S14455EJ1V0DS00

µPD6467 Data Sheet S14455EJ1V0DS00 [0A0H] [0A1H] [0A2H] [0A3H] [0A4H] [0A5H] [0A6H] [0A7H] [0A8H] [0A9H] [0AAH] [0ABH] [0ACH] [0ADH] [0AEH] [0AFH] [0B0H] [0B1H] [0B2H] [0B3H] [0EFH] [0B4H] [0B5H] [0B6H] [0B7H] [0B8H] [0B9H] [0BAH] [0BBH] [0BCH] [0BDH] [0BEH] [0BFH] [0C0H] [0C1H] [0C2H] [0C3H] [0C4H] [0C5H] [0C6H] [0C7H] [0C8H] [0C9H] [0CAH] [0CBH] [0CCH] [0CDH] [0CEH] [0CFH] [0D0H] [0D1H] [0D2H] [0D3H] [0D4H] [0D5H] [0D6H] [0D7H] [0D8H] [0D9H] [0DAH] [0DBH] [0DCH] [0DDH] [0DEH] [0DFH] [0E0H] [0E1H] [0E2H] [0E3H] [0E5H] [0E4H] [0E6H] [0E7H] [0E8H] [0E9H] [0EAH] [0EBH] [0ECH] [0EDH] [0EEH]

µPD6467 Data Sheet S14455EJ1V0DS00 [0F0H] [0F1H] [0F2H] [0F3H] [0F4H] [0F5H] [0F6H] [0F7H] [0F9H] [0F8H] [0FAH] [0FBH] [0FCH] [0FDH] Note 1 [0FEH]Note 2 [0FFH]Note 3 [100H] [101H] [103H] [102H]

µPD6467 Data Sheet S14455EJ1V0DS00

µPD6467 Data Sheet S14455EJ1V0DS00 [19AH] [19BH] [19CH] [19DH] [19EH] [19FH] [1A0H] [1A1H] [1A2H] [1A3H] [1A4H] [1A5H] [1A6H] [1A7H] [1A8H] [1A9H] [1AAH] [1ABH] [1ACH] [1ADH] [1AEH] [1AFH] [1B0H] [1B1H] [1B2H] [1B3H] [1B4H] [1B5H] [1B6H] [1B7H] [1B8H] [1B9H] [1BAH] [1BBH] [1BCH] [1BDH] [1BEH] [1BFH] [1C0H] [1C1H] [1C2H] [1C3H] [1C4H] [1C5H] [1C6H] [1C7H] [1C8H] [1C9H] [1CAH] [1CBH] [1CCH] [1CDH] [1CEH] [1CFH] [1D0H] [1D1H] [1D2H] [1D3H] [1D4H] [1D5H] [1D6H] [1D7H] [1D8H] [1D9H] [1DAH] [1DBH] [1DCH] [1DDH] [1DEH] [1DFH]

µPD6467 Data Sheet S14455EJ1V0DS00 [1E0H] [1E1H] [1E2H] [1E3H] [1E4H] [1E5H] [1E6H] [1E7H] [1E8H] [1E9H] [1EAH] [1EBH] [1ECH] [1EDH] [1EEH] [1EFH] [1F0H] [1F1H] [1F2H] [1F3H] [1F4H] [1F5H] [1F6H] [1F7H] [1F8H] [1F9H] [1FAH] [1FBH] [1FCH] [1FDH] Note 1 [1FEH]Note 2 [1FFH]Note 3 Notes 1. Blank data 2. Display Off Data (character addresses are fixed) 3. 2-byte continuous input end code (character addresses are fixed) Remark 0xxH indicates character address of the low-order (0) bank, and 1xxH indicates that of the high-order (1) bank.

µPD6467 Data Sheet S14455EJ1V0DS00 6. ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Parameter Symbol Conditions Ratings Unit Supply voltage VDD VDD –0.5 to + 4.6 V Input pin voltageVIN VIN –0.3 to VDD + 0.3 V Output pin voltage V OUT –0.3 to VDD + 0.3 V Operating ambient temperature T A –20 to +75 °C Storage temperature T stg –40 to +125 °C Power dissipation P D TA = +75 °C 270 mW Output current I O ±5m A Caution Exposure to Absolute Maximum Ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. The device should be operated within the limits specified under DC and AC Characteristics. Recommended Operating Range Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply voltage range V DD Dot clock: LC oscillation 2.7 3.6 V Dot clock: External input 2.0 3.6 Oscillation frequency (LC oscillation) fOSC VDD = 2.7 to 3.6 V 6.0 8.0 MHz External dot clock frequency f OSC VDD = 2.0 to 3.6 V 4.0 8.0 MHz (×1 frequency mode) External dot clock frequency f OSC2 VDD = 2.0 to 3.6 V 8.0 16.0 MHz (×2 frequency mode) Operating ambient temperature T A –20 +75 °C Electrical Characteristics (TA = –20 to + 75 °C, unless otherwise specified, VDD = 2.0 to 3.6 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Supply voltage range V DD 2.0 3.3 3.6 V Current consumption 1 I DD fOSC = 8.0 MHz, VDD = 3.3 V 5 mA Current consumption 2 I DD fOSC = 8.0 MHz, VDD = 2.0 V 4 mA Control input high-level voltage V CIH 0.7 VDD V Control input low-level voltage V CIL 0.3 VDD V Signal output high-level voltage V OSH IOSH = –1.0 mA (VDD = 3.3 V) 0.9 V DD V Signal output low-level voltage V OSL IOSL = 1.0 mA (VDD = 3.3 V) 0.1 V DD V Remark Control input : DATA, CLK, CS, PCL, Hsync, Vsync, CMDCT Signal output : VR , VG , VB, VC1 , VC2 , VBLK , BLK1, BLK2 (RBLK , GBLK , BBLK ) ( ): Set by initial status setting command

µPD6467 Data Sheet S14455EJ1V0DS00 Recommended Operation Timing (T A = –20 to +75 °C, VDD = 2.0 to 3.6 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Setup time t SET 200 ns Hold time t HOLD 200 ns Minimum clock low-level width t CKL 300 ns Minimum clock high-level width t CKH 300 ns Clock cycle t TCK 700 ns CS setup time t CSS 300 ns CS hold time t CSH 400 ns Minimum Hsync low-level width t HWL 4 µs Minimum Vsync low-level width t VWL 8 µs 10 % tHWL Hsync 10 % tVWL Vsync CS CLK DATA tCSH 90 % tCKHtCKLtCSS tTCK 10 % 10 % 90 %90 % tSET tHOLD 10 %

µPD6467 Data Sheet S14455EJ1V0DS00 Power-ON Clear Specifications Parameter Symbol Conditions MIN. TYP. MAX. Unit PCL pin low retention period t PCLL 10 µs tPCLL

0.8 VDD

0.16 VDD

External clock input timing (valid when selected by initial status setting command) tC-H 50 % tH-C 50 % tS 10 % 90 % Hsync External input clock Parameter Symbol Conditions MIN. TYP. MAX. Unit External clock falling t C-H 20 ns → sync signal rise time Sync signal rise time t H-C 20 ns → external clock falling tS (rising slew rate) t S Note ns Note 10% of cycle of external clock Example Where the external clock frequency is 8 MHz Clock cycle = 125 ns tS = 12.5 ns (MAX.) because 125 ns × 10% (MAX.) Remarks 1. Always keep the phase relation between the rising of Hsync and external input clock. 2. Make sure that noise of greater than 100 ns is not superimposed on the input of Hsync. 3. Keep the OSCOUT pin open when the external clock is input.

µPD6467 Data Sheet S14455EJ1V0DS00 Character and BLK Signal Output Characters and BLK signal are output in synchronization with the falling of the dot clock. CDSCUSDTWCDL 50 % 50 % 10 % 90 % External input clock Character signal BLK signal Output Timing (TA = –20 to +75 °C, output load capacitance = 10 pF, pins: VR , VG , VB , VBLK , VC1 , BLK1, VC2 , BLK2, (RBLK , GBLK , BBLK )) ( ): Set by initial status setting command Parameter Symbol Conditions MIN. TYP. MAX. Unit Character/BLK signal output delay CDL VDD = 3.0 V 5 10 30 ns Character/BLK signal output delay CDL VDD = 2.0 V 10 15 50 ns Character/BLK signal rise time CUS V DD = 3.0 V 1 10 ns Character/BLK signal rise time CUS V DD = 2.0 V 1 25 ns Character/BLK signal falling CDS V DD = 3.0 V 1 10 ns Character/BLK signal falling CDS V DD = 2.0 V 1 25 ns Minimum size of 1 dot width DTW V DD = 3.0 V, External input clock ×1 frequency mode (1/fOSC )–5 (1/f OSC )+5 ns VDD = 3.0 V, External input clock ×2 frequency mode (2/fOSC2 )–5 (2/f OSC2 )+5 ns Minimum size of 1 dot width DTW V DD = 2.0 V, External input clock ×1 frequency mode (1/fOSC )–5 (1/f OSC )+5 ns VDD = 2.0 V, External input clock ×2 frequency mode (2/fOSC2 )–5 (2/f OSC2 )+5 ns Remark f OSC : External input clock frequency (×1 frequency mode) (MHz) fOSC2 : External input clock frequency (×2 frequency mode) (MHz)

µPD6467 Data Sheet S14455EJ1V0DS00 Command Successive Input Permissible Time Successively input commands under the following timing conditions: (TA = –20 to +75 °C, VDD = 2.0 to 3.6 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Command successive T1 Common to all commands 2.0 µs input enable time T2 Video RAM write Display ON LC oscillation Note 1 µs command External clock Note 2 Display OFF Note 3 µs Notes 1. (1) 2.0 + (14/fOSC ) × S1 + 19/fOSC + (1/fOSC ) × S2 + tHWL S : Character size (×1 (MIN.) to ×4) S1 : Horizontal character size before Hsync S2 : Horizontal character size before Hsync tHWL : Hsync width Because the clock is not supplied to the internal circuitry during LC oscillation and Hsync, if Hsync is input while the video RAM write command is executed, the width directly influences the execution time (1). If Hsync is not input in the middle, the execution time is as (2) above. Whether (1) or (2) is longer in time depending on the horizontal character size before and after Hsync and Hsync width is not known. The longer time is the permissible minimum time. 2. 2.0 + 31/f OSC or 2.0 + 62/fOSC2 (S = 1) 3. 2.0 + 19/fOSC or 2.0 + 38/fOSC2 Remark fOSC : LC oscillation frequency or external input clock frequency (when ×1 frequency mode is selected) (MHz) fOSC2 : External input clock frequency (when ×2 frequency mode is selected) (MHz) The restriction of T2 is not applied to the commands other than the video RAM write command if the clock cycle for control satisfies the specifications. DATA Hi-Z Hi-Z Hi-Z CLK

µPD6467 Data Sheet S14455EJ1V0DS00 7. APPLICATION CIRCUIT EXAMPLE CLK CS DATA PCL VDD CMDCT OSC OUT OSC IN TEST GND Hsync Vsync VB VG VR VBLK VC2 BLK2 VC1 BLK1 Note 4(BBLK ) Note 4(GBLK ) Note 4(RBLK ) PD6467GRµ Output Inputs a negative Hsync or Vsync signal 7Note 3 8Note 3 Connected to microcomputer VDD 10 Fµ 100 kΩ 10 Fµ Note 1

0.01 Fµ+

33 Fµ 5 to 30 pF 30 pF MSB first LSB first LC module pin No. 1 LC module pin No. 3 Notes 1. CR constant must be satisfied with Power-ON Clear Specification (refer to 6. ELECTRICAL CHARACTERISTICS ). 2. This circuit can reduce the number of external components and facilitates the adjustment of oscillation frequency, using LC module (part number: Q285NCIS-11181, manufactured by Toko, Inc., pin connection: Figure A.) 3. Connect these pins as follows when inputting external clock: OSC IN pin: external clock input, OSCOUT pin: open 4. Signals in ( ) are set by using an initial status setting command (RGB + RGB compatible blanking). 5. When this connection is open, LSB first is selected. Figure A. Q285NCIS-11181 Pin Connections (Bottom View)

6 GND

µPD6467 Data Sheet S14455EJ1V0DS00 8. PACKAGE DRAWING 20 11 11 0 M

20 PIN PLASTIC SHRINK SOP (225 mil)

A F G E C D M N B K L H I J ITEM MILLIMETERS INCHES A B C D E F G H I J 0.65 (T.P.) 1.8 MAX. 1.5–0.1 6.4–0.2 0.575 MAX. K L 0.10 0.5–0.2 4.4–0.1 0.15 M 0.15 0.22 0.1–0.1 N +0.10 –0.05 0.023 MAX. 7.00 MAX. 0.276 MAX. 0.009 0.004–0.004 0.071 MAX. 0.252–0.008 0.059–0.004 0.173–0.004 0.020–0.008 0.006 0.004 0.006 0.026 (T.P.) +0.004 –0.002 +0.004 –0.002 +0.10 –0.05 3°+7° −3° NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition.

µPD6467 Data Sheet S14455EJ1V0DS00 9. RECOMMENDED SOLDERING CONDITIONS When soldering this product, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL” (C10535E). Surface mount devices µPD6467GR-xxx: 20-pin plastic shrink SOP (225 mil) Process Conditions Symbol Infrared ray reflow Peak temperature: 235 °C or below (Package surface temperature), IR35-00-2 Reflow time: 30 seconds or less (at 210 °C or higher), Maximum number of reflow processes: 2 times. VPS Peak temperature: 215 °C or below (Package surface temperature), VP15-00-2 Reflow time: 40 seconds or less (at 200 °C or higher), Maximum number of reflow processes: 2 times. Partial heating method Pin temperature: 300 °C or below, – Heat time: 3 seconds or less (Per each side of the device). Caution Apply only one kind of soldering condition to a device, except for “partial heating method”, or the device will be damaged by heat stress.

µPD6467 Data Sheet S14455EJ1V0DS00 NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.

µPD6467 [MEMO]

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