D602 SIGE | Alldatasheet
Document overview
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Technical content
Features
Low Phase Noise, -141dBc/Hz at 1kHz offset Single Supply Voltage, 2.7 - 4.0 V Low Power Consumption, 42mW Power Down Mode, 0.2µA Compatible with common PLL synthesizer ICs 8-Pin Plastic SOIC Package
Ordering Information
The D602 is a SiGe divi de-by-2 lo w noise static prescaler ca pable of op eration up to 6.0 GHz. The D602 operates over a wide range of input frequ encies and l evels, a nd prov ides d ifferential outp uts for lo w noise o peration with th e c ommon P LL st yle fre quency synthesizer ICs. The static nature of the pre scaler pr events spurio us generation. The D602 prescaler c an operate from e ither a s ingle positive or single neg ative supp ly with p ower do wn mode for low standby power consumption. Functional Block Diagram fIn fOut In Out Out In VCC VEE VEE PWD 20-DST-01 Rev 5.0 Sept/01 1 of 8
3V, 6GHz Divide-by-2 Static Prescaler Final Pin Out Diagram In Out Out In VEE VEE PWDVCC D602 Pin Out Description Pin No. Name Description
1 VCC Power Supply Voltage Input
2 In Prescaler Input (internally-biased)
3 In Prescaler Complementary Input (internally-biased)
4 VEE Ground for Input (pins 4 and 5 must be connected to the same potential)
5 VEE Ground for Output (pins 4 and 5 must be connected to the same potential)
6 Out Complementary Output (open-collector)
7 Out Output (open-collector)
8 PWD Power Down high impedance CMOS input. When PWD is high, the part is powered down. Absolute Maximum Ratings Operation in excess of any one of above Absolute Maximum Ratings may result in permanent damage. This device is a hi gh performance RF int egrated a nd is ESD se nsitive. The RF inp uts on th is d evice ar e C lass 0 ESD r ated; therefore suitable precaution should be taken during handling, assembly and testing. Symbol Parameter Min. Max. Unit Supply Voltage -0.3 +4.3 V Voltage on any pin with respect to VEE -0.3 VCC + 0.3 V Differential input voltage -2.0 +2.0 V Storage Temperature -65 +150 °C 20-DST-01 Rev 5.0 Sept/01 2 of 8
3V, 6GHz Divide-by-2 Static Prescaler Final
Electrical Characteristics
Conditions: V CC = 3.0V, -40°C < TA < 85°C unless otherwise specified Symbol Parameter Note Min. Typ. Max. Unit VCC Supply Voltage 2.7 3.0 4.0 V TA Operating Temperature 1 -40 25 85 °C ICC Supply Current 14 18 mA ICC – PWDN Power-Down Supply Current (VPWD = High) 0.2 1.0 µA fIn(U) Upper Limit of Input Frequency 2 5.8 6.4 GHz fIn(L) Lower Limit of Input Frequency 2 0.6 1.0 GHz fOsc Self Oscillation Output Frequency 3 1.0 GHz PIn(U) Upper Limit of Input Power 0 3 dBm PIn(L) Lower Limit of Input Power -20 -10 dBm POut Output Power 4 -15.0 0 dBm VIH High-Level PWD Input Voltage VCC - 0.2 V VIL Low-Level PWD Input Voltage 0.2 V IIH High-Level PWD Input Current -100.0 100.0 nA IIL Low-Level PWD Input Current -100.0 100.0 nA PN Residual Phase Noise at 1kHz offset from a 2.5GHz (fOut) carrier -141 dBc/Hz Notes: (1) Sample Tested (2) For a sine-wave input (3) Since the input signal is AC coupled, in the absence of an RF input, the prescaler may self oscillate and provide an output at this freq uency. Self oscillation can be eliminated by powering down the prescaler, or applying a differential DC input voltage (a 47kΩ resistor placed between pin 3 and VCC). (4) This power is delivered to a 50Ω load. It excludes the power dissipated in the external pull-up resistors. Test Circuit D602 100p 100n VCC 51 51 1n1n Signal Generator
50 Ohm
20-DST-01 Rev 5.0 Sept/01 3 of 8
3V, 6GHz Divide-by-2 Static Prescaler Final Typical Performance Characteristics Supply Current vs Supply Voltage Supply Voltage [V] Supply Current [mA] 5.5 5.7 5.9 6.1 6.3 6.5 6.7 6.9 Upper Limit of Input Frequency vs Supply Voltage PIn = – 10dBm Supply Voltage [V] Input Frequency [GHz] -40 -30 -20 -10 Input Power Limits vs Input Frequency Input Frequency [GHz] Input Power [dBm] PIn(U) PIn(L) -12 -11 -10 Output Power vs Supply Voltage fIn = 5.0 GHz Supply Voltage [V] Output Power [dBm,] -15 -10 Output Power vs Input Frequency Output Power [dBm] Input Frequency [GHz] 5.7 5.8 5.9 6.1 6.2 6.3 6.4 6.5 6.6 6.7 -40 -20 0 20 40 60 80 Upper Limit of Input Frequency vs Temperature Input Frequency [GHz] Temperature [°C] 3.0V 2.7V 20-DST-01 Rev 5.0 Sept/01 4 of 8
3V, 6GHz Divide-by-2 Static Prescaler Final 2.05 2.1 2.15 2.2 -40 -20 0 20 40 60 80 Minimum Required Supply Voltage vs Temperature (fIn = 5.0 GHz) Supply Voltage [V] Temperature [°C] -6.5 -5.5 -4.5 -3.5 -40 -20 0 20 40 60 80 Output Power vs Temperature (fIn = 5.0 GHz) Output Power [dBm] Temperature [°C] 13.3 13.4 13.5 13.6 13.7 13.8 13.9 -40 -20 0 20 40 60 80 Supply Current vs Temperature Supply Current [mA] Temperature [°C] Residual Phase Noise 20-DST-01 Rev 5.0 Sept/01 5 of 8
3V, 6GHz Divide-by-2 Static Prescaler Final Typical Application Information D602 +3V 10p 10p 10p PLL Frequency Synthesizer 47k VCO 10p Ref. RF * The 47kΩ resistor provides a DC offset that disables self oscillation in the absence of an RF input. Cascading D602 Prescalers D602 prescalers can be casc aded to achieve division ratios other than 2. For example two D602 prescalers can be used as shown in the following diagram to perform frequency division by 4. D602 +3V 10p 10p 10p 10p D602 10p 1n 10p PWD In Out 20-DST-01 Rev 5.0 Sept/01 6 of 8
3V, 6GHz Divide-by-2 Static Prescaler Final
Package Information
Package dimensions in millimeters (inches) 8-Lead Plastic SOIC SiGe D602 XXXXXXX Packing Details Note : Refer to JEDEC MS-012 for additional information 20-DST-01 Rev 5.0 Sept/01 7 of 8
3V, 6GHz Divide-by-2 Static Prescaler Final http://www.sige.com Headquarters: Canada Phone: +1 613 820 9244 Fax: +1 613 820 4933
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