UPD485505 NEC | Alldatasheet
Document overview
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Technical content
Features
- 5,048 words by 8 bits
- Asynchronous read/write operations available
- Variable length delay bits; 21 to 5,048 bits (Cycle time: 25 ns) 15 to 5,048 bits (Cycle time: 35 ns)
- Power supply voltage VCC = 5.0 V ± 0.5 V
- Suitable for sampling one line of A3 size paper (16 dots/mm)
- All input/output TTL compatible
- 3-state output
- Full static operation; data hold time = infinity
Ordering Information
Part Number R/W Cycle Time Package µPD485505G-25 25 ns 24-pin plastic SOP µPD485505G-35 35 ns (11.43 mm (450)) µPD485505 LINE BUFFER 5K-WORD BY 8-BIT The mark shows major revised points.Document No. M10059EJ7V0DSJ1 (7th edition) Date Published December 2000 N CP(K) Printed in Japan The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
µPD485505
2 Data Sheet M10059EJ7V0DS00
Pin Configuration (Marking side) 24-pin plastic SOP (11.43 mm (450)) [µPD485505G] D OUT0 D OUT1 D OUT2 D OUT3 RE RSTR GND RCK D OUT4 D OUT5 D OUT6 D OUT7 D IN0 D IN1 D IN2 D IN3 WE RSTW V CC WCK D IN4 D IN5 D IN6 D IN7 D IN0 - DIN7 : Data Inputs D OUT0 - DOUT7 : Data Outputs WCK : Write Clock Input RCK : Read Clock Input WE : Write Enable Input RE : Read Enable Input RSTW : Reset Write Input RSTR : Reset Read Input V CC : +5.0 V Power Supply GND : Ground Remark Refer to 5. Package Drawing for the 1-pin index mark.
µPD485505 3Data Sheet M10059EJ7V0DS00 Block Diagram D IN0 D IN1 D IN2 D IN3 D IN4 D IN5 D IN6 D IN7 WE RSTR WCK D OUT0 D OUT1 D OUT2 D OUT3 D OUT4 D OUT5 D OUT6 D OUT7 RCK RSTW RE VCC GND Write Address Pointer Read Address Pointer Input Buffer Output Buffer Memory Cell Array 40,384 bits (5,048 words by 8 bits)
µPD485505
4 Data Sheet M10059EJ7V0DS00
- Input/Output Pin Function Pin Pin Symbol Pin Number Name 24 - 21 D IN0 Data | Input 16 - 13 D IN7 1 - 4 D OUT0 Data | Output 9 - 12 D OUT7
19 RSTW Reset
6 RSTR Reset
20 WE Write
5 RE Read
17 WCK Write
8 RCK Read
In Write data input pins. The data inputs are strobed by the rising edge of WCK at the end of a cycle and the setup and hold times (t DS , tDH ) are defined at this point. Out Read data output pins. The access time is regulated from the rising edge of RCK at the beginning of a cycle and defined by t AC . In Reset input pin for the initialization of the write address pointer. The state of RSTW is strobed by the rising edge of WCK at the beginning of a cycle and the setup and hold times (t RS , tRH ) are defined. In Reset input pin for the initialization of the read address pointer. The state of RSTR is strobed by the rising edge of RCK at the beginning of a cycle and the setup and hold times (t RS , tRH ) are defined. In Write operation control signal input pin. When WE is in the disable mode (“H” level), the internal write operation is inhibited and the write address pointer stops at the current position. In Read operation control signal input pin. When RE is in the disable mode (“H” level), the internal read operation is inhibited and the read address pointer stops at the current position. The output changes to high impedance. In Write clock input pin. When WE is enabled (“L” level), the write operation is executed in synchronization with the write clock. The write address pointer is incremented simultaneously. In Read clock input pin. When RE is enabled (“L” level), the read operation is executed in synchroniza- tion with the read clock. The read address pointer is incremented simultaneously.
µPD485505 5Data Sheet M10059EJ7V0DS00 2. Operation Mode µPD485505 is a synchronous memory. All signals are strobed at the rising edge of the clock (RCK, WCK). For this reason, setup time and hold time are specified for the rising edge of the clock (RCK, WCK).
2.1 Write Cycle
When the WE input is enabled (“L” level), a write cycle is executed in synchronization with the WCK clock input. The data inputs are strobed by the rising edge of the clock at the end of a cycle so that read data after a one- line (5,048 bits) delay and write data can be processed with the same clock. Refer to Write Cycle Timing Chart. When WE is disabled (“H” level) in a write cycle, the write operation is not performed during the cycle which the WCK rising edge is in the WE = “H” level (tWEW ). The WCK does not increment the write address pointer at this time. Unless inhibited by WE, the internal write address will automatically wrap around from 5,047 to 0 and begin incrementing again.
2.2 Read Cycle
When the RE input is enabled (“L” level), a read cycle is executed in synchronization with the RCK clock input and data is output after tAC . Refer to Read Cycle Timing Chart. When RE is disabled (“H” level) in a read cycle, the read operation is not performed during the cycle which the RCK rising edge is in the RE = “H” level (tREW ). The RCK does not increment the read address pointer at this time.
2.3 Write Reset Cycle/Read Reset Cycle
After power up, the µPD485505 requires the initialization of internal circuits because the read and write address pointers are not defined at that time. It is necessary to satisfy setup requirements and hold times as measured from the rising edge of WCK and RCK, and then input the RSTW and RSTR signals to initialize the circuit. Write and read reset cycles can be executed at any time and the address pointer returns zero. Refer to Write Reset Cycle Timing Chart, Read Reset Cycle Timing Chart. Remark Write and read reset cycles can be executed at any time and do not depend on the state of RE or WE.
µPD485505
6 Data Sheet M10059EJ7V0DS00
Operation-related Restriction Following restriction exists to read data written in a write cycle. Read the written data after an elapse of 1/2 write cycle + tWAR since the write cycle ends (see Figure 2.1). If tWAR is not satisfied, the output data may undefined. Figure 2.1 Delay Bits Restriction Timing Chart Remark This timing chart describes only the delay bits restriction, and does not defines the WE, RE, RSTW, RSTR signals. 0123 012 0123 0123 WCK RCK D IN D OUT 1/2 write cycle tWAR tAC High impedance High impedance
µPD485505 7Data Sheet M10059EJ7V0DS00 3. Electrical Specifications All voltages are referenced to GND. Absolute Maximum Ratings Parameter Symbol Condition Rating Unit Voltage on any pin relative to GND V T –0.5Note to VCC + 0.5 V Supply voltage V CC –0.5 to +7.0 V Output current I O 20 mA Operating ambient temperature T A 0 to 70 ˚C Storage temperature T stg –55 to +125 ˚C Note –3.0 V MIN. (Pulse width = 10 ns) Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Recommended Operating Conditions Parameter Symbol Condition MIN. TYP. MAX. Unit Supply voltage V CC 4.5 5.0 5.5 V High level input voltage V IH 2.4 VCC + 0.5 V Low level input voltage V IL –0.3Note +0.8 V Operating ambient temperature TA 07 0 ˚ C Note –3.0 V MIN. (Pulse width = 10 ns) DC Characteristics (Recommended Operating Conditions unless otherwise noted) Parameter Symbol Test Condition MIN. TYP. MAX. Unit Operating current I CC 80 mA Input leakage current I I VI = 0 to VCC , Other Input 0 V –10 +10 µA Output leakage current I O VO = 0 to VCC , –10 +10 µA D OUT : High impedance High level output voltage V OH IOH = –1 mA 2.4 V Low level output voltage V OL IOL = 2 mA 0.4 V Capacitance (TA = 25 ˚C, f = 1 MHz) Parameter Symbol Test Condition MIN. TYP. MAX. Unit Input capacitance C I 10 pF Output capacitance C O 10 pF
µPD485505
8 Data Sheet M10059EJ7V0DS00
AC Characteristics (Recommended Operating Conditions unless otherwise noted)Notes 1, 2, 3 Parameter Symbol µPD485505-25 µPD485505-35 Unit Notes MIN. MAX. MIN. MAX. Write clock cycle time t WCK 25 35 ns Write clock pulse width t WCW 11 12 ns Write clock precharge time t WCP 11 12 ns Read clock cycle time t RCK 25 35 ns Read clock pulse width t RCW 11 12 ns Read clock precharge time t RCP 11 12 ns Access time t AC 18 25 ns Write data-read delay time t WAR 470 470 ns Output hold time t OH 55 n s Output low-impedance time t LZ 5 18 5 25 ns 4 Output high-impedance time t HZ 5 18 5 25 ns 4 Input data setup time t DS 71 0 n s Input data hold time t DH 33 n s RSTW/RSTR Setup time t RS 71 0 n s 5 RSTW/RSTR Hold time t RH 33 n s 5 RSTW/RSTR Deselected time (1) t RN1 33 n s 6 RSTW/RSTR Deselected time (2) t RN2 71 0 n s 6 WE Setup time t WES 71 0 n s 7 WE Hold time t WEH 33 n s 7 WE Deselected time (1) t WEN1 33 n s 8 WE Deselected time (2) t WEN2 71 0 n s 8 RE Setup time t RES 71 0 n s 9 RE Hold time t REH 33 n s 9 RE Deselected time (1) t REN1 3 3 ns 10 RE Deselected time (2) t REN2 71 0 n s 1 0 WE Disable time t WEW 00 m s RE Disable time t REW 00 m s Write reset time t RSTW 00 m s Read reset time t RSTR 00 m s Transition time t T 3 35 3 35 ns
µPD485505 9Data Sheet M10059EJ7V0DS00 Notes 1. AC measurements assume tT = 5 ns. 2. AC Characteristics test condition Input Timing Specification Output Timing Specification Output Loads for Timing 4. tLZ and tHZ are measured at ±200 mV from the steady state voltage. Under any conditions, tLZ ≥ tHZ . 5. If either tRS or tRH is less than the specified value, reset operations are not guaranteed. 6. If either tRN1 or tRN2 is less than the specified value, reset operations may extend to cycles preceding or following the period of reset operations. 7. If either tWES or tWEH is less than the specified value, write disable operations are not guaranteed. 8. If either tWEN1 or tWEN2 is less than the specified value, internal write disable operations may extend to cycles preceding or following the period of write disable operations. 9. If either tRES or tREH is less than the specified value, read disable operations are not guaranteed. 10. If either tREN1 or tREN2 is less than the specified value, internal read disable operations may extend to cycles preceding or following the period of read disable operations. 1.8 kΩ 1.1 kΩ D OUT VCC 5 pF (tLZ, tHZ ) 1.8 kΩ 1.1 kΩ D OUT VCC 30 pF (tAC , tOH ) 3.0 V 0 V tT = 5 ns t T = 5 ns
1.5 V Test points
0.8 V
2.0 VHigh impedance High impedance
µPD485505
10 Data Sheet M10059EJ7V0DS00
Cycle n Cycle n+1 Cycle n+2 Disable Cycle Cycle n+3 tWCW tWEN1 tWES tWEW tWEH tWEN2 tWCP tWCK tDS tDH (n+1)(n) tDS tDH (n+2) (n+3) WCK (Input) WE (Input) D IN (Input) Remark RSTW = “H” level Read Cycle Timing Chart Cycle n Cycle n+1 Cycle n+2 Disable Cycle Cycle n+3 tRCW tREN1 tRES tREW tREH tREN2 tRCP tRCK (n+1)(n) tAC tOH (n+2) (n+3) tHZ tLZ tAC tLZ High impedance RCK (Input) RE (Input) D OUT (Output) High impedance Remark RSTR = “H” level
µPD485505 11Data Sheet M10059EJ7V0DS00 Write Reset Cycle Timing Chart (WE = Active) Cycle n Reset Cycle Cycle 0 Cycle 1 tRN2tRHtRSTW NotetRStRN1 “L” Level tDS tDH tDS tDH (1)(0)(n)(n–1)D IN (Input) WE (Input) RSTW (Input) WCK (Input) Note In write reset cycle, reset operation is executed even without a reset cycle (tRSTW ). WCK can be input any number of times in a reset cycle. Write Reset Cycle Timing Chart (WE = Inactive) Cycle n Disable Cycle Cycle 0 tRN2tRHtRSTW NotetRStRN1 tDS tDH tDS (0)(n)(n–1)D IN (Input) WE (Input) RSTW (Input) WCK (Input) Reset Cycle tWEW tWEN1 tWES tWEH tWEN2 Note In write reset cycle, reset operation is executed even without a reset cycle (tRSTW ). WCK can be input any number of times in a reset cycle.
µPD485505
12 Data Sheet M10059EJ7V0DS00
Read Reset Cycle Timing Chart (RE = Active) Cycle n Reset Cycle Cycle 0 Cycle 1 tRN2tRHtRSTR NotetRStRN1 “L” Level tAC tOH tAC tOH (1)(0)(n)(n–1)D OUT (Output) RE (Input) RSTR (Input) RCK (Input) tOH tACtAC (0) Note In read reset cycle, reset operation is executed even without a reset cycle (tRSTR ). RCK can be input any number of times in a reset cycle. Read Reset Cycle Timing Chart (RE = Inactive) Cycle n Disable Cycle Cycle 0 tRN2tRHtRSTR NotetRStRN1 tHZ tAC (0)(n)(n–1)D OUT (Output) RE (Input) RSTR (Input) RCK (Input) tLZ tREH tAC Reset Cycle tREN1 tRES tREW tREN2 High impedance tOH tOH Note In read reset cycle, reset operation is executed even without a reset cycle (tRSTR ). RCK can be input any number of times in a reset cycle.
µPD485505 13Data Sheet M10059EJ7V0DS00 4. Application 4.1 1 H Delay Line µPD485505 easily allows a 1 H (5,048 bits) delay line (see Figure 4.1). Figure 4.1 1 H Delay Line Circuit WCK D IN WE RSTW RCK D OUT RE RSTR
40 MHz Clock Reset
Figure 4.2 1 H Delay Line Timing Chart tWCK tRCK Cycle 0 Cycle 1 Cycle 2 1 H (5,048 Cycles) Cycle 5,047 Cycle 0’ 2 H (5,048 Cycles) tWCW tRCW tWCP tRCP tRS tRH tDH tDS tDH tOHtAC (0) (1) (2’) (3’) (2) (3) WCK/RCK (Input) RSTW / RSTR (Input) D IN (Input) D OUT (Output) tDS Cycle 1’ Cycle 2’ Cycle 3’Write Cycle 0Read Cycle 1 Cycle 2 Cycle 3 Remark RE, WE = “L” level
µPD485505
14 Data Sheet M10059EJ7V0DS00
4.2 n Bit Delay It is possible to make delay read from the write data with the µPD485505. (1) Perform a reset operation in the cycle proportionate to the delay length. (Figure 4.3) (2) Shift the input timing of write reset (RSTW) and read reset (RSTR) depending on the delay length. (Figure 4.4) (3) Shift the address by disabling RE for the period proportionate to the delay length. (Figure 4.5) n bit: Delay bits from write cycle to read cycle correspond to a same address cell. Restrictions Delay bits n can be set from minimum bits to maximum bits depending on the operating cycle time. Refer to 2. Operation Mode Operation-related Restriction. Cycle time MIN. MAX. 25 ns 21 bits 5,048 bits 35 ns 15 bits 5,048 bits Figure 4.3 n-Bit Delay Line Timing Chart (1) tWCK tRCK Cycle 0 Cycle 1 Cycle 2 1 H (n Cycles) Cycle n–1 2 H (n Cycles) tWCW tRCW tWCP tRCP tRS tRH tDH tDS tDS tDH tOHtAC (0) (1) (2’) (3’) (2) (3) WCK/RCK (Input) D IN (Input) D OUT (Output) tRS tRH (2) RSTW / RSTR (Input) Cycle 0’Write Cycle 0Read Cycle 1’ Cycle 1 Cycle 2’ Cycle 2 Cycle 3’ Cycle 3 tWAR Remark RE, WE = “L” level
µPD485505
16 Data Sheet M10059EJ7V0DS00
4.3 Double-speed Conversion
Figure 4.6 shows an example timing chart of double-speed and twice reading operation (fR = 2fW , 5,048 by 2 cycle) for a write operation (fW = 5,048 cycle). Caution The read operation collide with the write operation on the same line, last n bits output data (5,048–n to 5,048) in the first read operation will be undefined (see Figure 4.6 Double-speed Conversion Timing Chart). Undefined bits mentioned above depend on the cycle time. Read cycle time Undefined bits 25 ns 21 bits 35 ns 15 bits Figure 4.6 Double-speed Conversion Timing Chart Remark RE, WE = “L” level (5,048 Cycle) (5,048 Cycle) 0 1 2 5046 5047 0' 1' 2' 5046' 5047' 0" 0 1 2 5046 5047 0' 1' 2' 5046' 5047' 0" (5,048 Cycle) First read cycle (5,048 Cycle) Second read cycle (5,048 Cycle) First read cycle n bits output data will be undefined. n bits output data will be undefined. 012 5046 5047 012 5046 5047 0' 1' 2' 5046' 5047' 0' 1' tAC WCK (Input) RSTW (Input) D IN (Input) RCK (Input) RSTR (Input) D OUT (Output)
µPD485505 17Data Sheet M10059EJ7V0DS00 5. Package Drawing 24 13 1 12 K F G P detail of lead end M S A J H I L E C D M B SN ITEM B C H 24-PIN PLASTIC SOP (11.43 mm (450)) A J D E F G I K L MILLIMETERS 1.27 (T.P.) 1.27 MAX. 12.2±0.3 15.5±0.2 1.9±0.2 0.42±0.08 0.1±0.1 2.0 2.1±0.2 8.4±0.2 0.17+0.08 −0.07 0.9±0.2 0.12M NOTE Each lead centerline is located within 0.12 mm of its true position (T.P.) at maximum material condition. N 0.10 5°±5°P P24GM-50-450A-4
µPD485505
18 Data Sheet M10059EJ7V0DS00
- Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the µ PD485505. Type of Surface Mount Device µPD485505G: 24-pin plastic SOP (11.43 mm (450)) 7. Example of Stamping Letter E in the fifth character position in a lot number signifies version E, letter K, version K, letter P, version P, and letter L, version L. JAPAN D485505 Lot number
µPD485505 19Data Sheet M10059EJ7V0DS00 NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and trans- ported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
µPD485505 [MEMO] M8E 00. 4 The information in this document is current as of December, 2000. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products and/or types are available in every country. Please check with an NEC sales representative for availability and additional information. No part of this document may be copied or reproduced in any form or by any means without prior written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document. NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of NEC semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC or others. Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in NEC semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. NEC semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard":Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness to support a given application. (Note) (1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries. (2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for NEC (as defined above).