D482235LE70

UPD482235 NEC | Alldatasheet

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Technical content

Features

Dual port structure (Random access port, Serial access port) + Random access port (262, 144-word x 8-bit structure) uPD482234 ee Fast page mode cycle time 40ns (MIN) | 45ns (MIN) _ | uPD482295 J roars roar] Hyper page mode cycle time 30 ns (MIN.) [36 ns (min) | * Flash write functionNote * Block write function (4 columns)Nete + Mask write (Write-per-bit function) + 512 refresh cycles /8 ms + GAS before RAS refresh, RAS only refresh, Hidden refresh Note Write-per-bit can be specified. ‘The information in this document is subject to change without notice. See Document No. M1 1098&s4VODSUt

NEC pPD482234, 482235 + Serial access port (612 words x 8 bits organization) + Serial readiwrite cycle time uPD482234-60, 482235-60 | uPD482294-70, 482235-70 + Serial data read/write - Split buffer data transfer + Binary boundary jump function Version B, A, F, and E There are four versions, B, A, F, and E, toboth the .PD482234 and uPD482235. This data sheet canbe applied to the versions B and A. + How to identity each version Each version is identified with its lot number (Refer to 7. Example of Stamping).

Ordering Information

P P: ns (MAX.) | uPosazcaaceco | 60 | 4pin plastio SOV (400m) Fast page mode uPD482234G5-60 [ 6 ~—si«t 44-pin plastic TSOP (Il) uPD482234G6-70 ‘{400mi) uPD482235LE-60 [60 | —_40-pin plastic SOU (400mil) Hyper page mode | weoseazasas-co | 60 | tpn plastic TSOP (In PD48223605-70 (400m)

NEC HPD482234, 482235 Pin Configurations (Marking Side) 40-pin plastic SOU (400 mil) Voo © 1 40/-— 6nd sco 2 30 © SiO7 $100 O- 3 38 O Si06 $1010 4 7 O SIOS $102 O 5 36 O Sio4 ‘S103 O 6 35 0 SE OTE O 7 34 © Ww7ilo7 WO/O0 O- 8 33 ‘O WE/NO6- W101 O 9 Es 32 ‘O W5NOS w21l02 © 10 g at © wario4 W3/l03 O W f i 30 © GND __GNO ° 12 h i 29 © DSF WBME © 13 28 © NC RAS O 14 ar © CAS ABO 16 26 © QSF A70 16 25 © A0 ABO 7 24 OA 450 18 23 O a2 A400 19 22 OAs Voc O 20 2 © GND AO to A8 : Address inputs WO to W7/I00 to 107: Mask data selects/Data inputs and outputs $100 to S107 : Serial data inputs and outputs RAS : Row address strobe CAS : Column address strobe DTOE : Data transfer/Output enable WEAWE + Write-per-bit Write enable SE : Serial data Input/Output enable sc 2 Serial clock QsF + Special function output DSF : Special function enable Voc : Power supply voltage GNO : Ground NoNote : No connection Note Some signals can be applied because this pin Is not connected to the inside of the chip.

NEC . pPD482234, 482235 44-pin plastic TSOP (il) (400 mil) VecO 1 O 444 —o GND sco 2 43}-—~0 sio7 s1000 3 42}. —-0 si06 $1010 4 41 © sios 81020 5 40}-—~0 sio4 81030; 6 39) 0 SE DTMOEO 7 38}-—-O W7/107 Wiil01 © 9 a 96 © W5/IOS walle O 10 i i 35 © waio4 W8/030 13 a8 32}— GND ‘@NDO 4 31 O psF WBWEO 15 20] O NC RASO 16 2 © CAS ABO 7 ) © QSF 70 18 27+-—O A0 460 19 26}-—O At AsO 20 25) O A2 MO a 24-—O a3 VooO 22 O 23}—O GND AO to AB : Address inputs WO to W7/I00 to 107: Mask data selects/Data inputs and outputs $100 to SIO7 : Serial data inputs and outputs RAS : Row address strobe CAS : Column address. strobe DI/OE : Data transfer/Output enable ‘WB, WE : Write-per-bitWrite enable ‘SE : Serial data input/Output enable sc : Serial clock QsF + Special function output DSF + Special function enable Veo : Power supply voltage GND : Ground NCNote : No connegtion Note Some signals can be applied because this pin is not connected to the inside of the chip.

NEC 482234, 482235 [MEMO] PAGE(S) INTENTIONALLY BLANK

NEC 1D482234, 482235 Block Diagram RAS. os i wo/loo w7o7 wore —]E | a comnonae oF (8 bits) Voc—— GND-—— 8 Ea [eT eamowee de] ry 512 columns x 8 im n—| 5 H |s é i ‘Memory Cell Array Aa 8 (512x512 x8) z wlél WG i ‘AG: AT: 1 As J A010 AB CES ee cs asF S100 si07 118 M@™§ 6427525 0063809 993 me

NEC UPD482234, 482235 1. Pin Functions This product is equipped with the RAS, CAS, WB/WE, DT/OE, AO to A8, DSF, SC, SE inputs, QSF output, and WO to W7/I00 to 107, S100 to S107 input/output pins. (1/3) Inputl Pit ee RAS This signal latches the row addresses (AO to A8), selects the corresponding (Row address strobe) word line, and activates the sense amplifier. It also refreshes the memory cell array of the one line (4,096 bits) selected from the row addresses (AO to A8). It also serves as the signal which selects the following operations. + Write-per-bit + Flash write + TKS before RAS refresh + Split data transfer CAS This signal latches the column addresses (AO to A8), selects the digit line (Column address connecting the sense amplifier, and activates the output circuit which strobe) outputs data to the random access port. It also serves as the signal which selects the following operations. + Read/write + Block write + Color register set + Mask register set AD to AB These are the address input pins, TAP register input pins, and STOP (Address inputs) register input pins. Address input This is a 9-bit address bus, It inputs a total of 18 bits of the address signal, starting from the upper 9 bits (row address) and then followed by the lower 9 bits (column bits) (address multiplex method). Using these, one word Memory cells (8 bits) are selected from the 262,144 words x 8 bits memory cell array. During use, specify the row address, activate the RAS signal, latch the row address, switch to the column address, and activate the CAS signal, After activating the RAS and CAS signals, each address signal is taken into the device. For this reason, the address input setup time (tasa, tasc) and hold time (tran, tan) are specified for activating the RAS and CAS signals. TAP Register Input Inthe datatransfer cycle, this TAP register input pin functions as the address input pin which selects the memory cell for transferring (9 bits are latched at the falling edge of RAS) and the TAP register data input pin which specifies the start addresses of the serial read/write operation after data transfer (9 bits are latched at the falling edge of the CAS). ‘STOP Register Input This pin functions as the STOP register input pin when the STOP register is set (STOP register data (9 bits) are latched at the falling edge of the RAS.) 119 M@ 6427525 0063810 b05 mm

NEC pPD482234, 482235 (2/3) ee el Output DT/OE These are the data transfer contro! signal and read operation control signal (Data transter! respectively. They have different functions in the data transfer cycle and output enable) tead cycle. Data transfer control signal (In data transfer cycle) The data transfer cycle is initiated when a low level is input to this pin at the falling edge of RAS. Read operations control signal (In read cycle) Read operation is performed when this signal, and the RAS and CAS signals are activated. The input/output pin is high impedance when this signal is not activated. When the WB/WE signal is activated while the BT/GE signal is activated, the DT/OE signal is invalid in the memory and read operations cannot be performed. WBIWE These are the write operation control signal and mask write cycle (write-per- (Write-per-bit/ bit function) mask data input control signal, respectively. Write enable) When this signal, RAS and CAS signals are activated, write operations or mask write can be performed. These mode are determined by the level of WBIWE at the falling edge of RAS. DSF This signal controls the selection of functions. (Special function The selection of functions is determined by the level of this signal at the enable) falling edge of the RAS and CAS. The functions will change as follows when this signal is high level. + The data transfer cycle changes to a split data transfer cycle. + The readiwrite cycle of each RAS clock changes to the flash write cycle. + The write cycle of each CAS clock changes to the block write cycle. WO to W7/I00 to 107 These are normally 8-bit data bus and are used for inputting and outputting (Mask data selects/ data. (100 to 107). Data inputs, outputs) Function as the mask data input pins (WO to W7) in the mask write cycle (write-per-bit function). Write operations can be performed only for WO to W7 that are input with a high level at the falling edge of RAS (new mask data). Functions as the column selection data input pin in the block write cycle. 120 MB 6427525 0063811 54)

NEC LPD482234, 482235 (3/3)

7 Input’ 5

sc This pin inputs the clock which controls the serial access port operation. (Serial clock) Serial Read The data of the data register which is synchronized with the rising edge of the SC are output from the S100 to SIO7 pins and kept until the next SC rising edge. Serial Write The data from the S100 to SIO7 pins are latched at the rising edge of the SC and written in the data register. SE This is a control pin for the serial access port input/output buffer. (Serial data input It controls data output during serial reading and controls data input during output enable) serial writing. By inputting the serial clock, the serlal pointer will operate even if SE has not been activated (high level input). S100 to SIO7 ‘These are the serial data input and output pins of the serial access port. (Serial data inputs/ outputs) QsF This is a position discrimination pin of the serial pointer (upper side or lower (Special function side). output) Which side is being serial accessed (upper side or lower side) can be discriminated according to the output of this pin. 121 MH 6427525 0063812 488 oe

NEC pPD482234, 482235 _ 2. Random Access Port Operations The operation mode is determined by the CAS, DT/OE, WEIWE, and DSF level at the falling edge of RAS and DSF level at the falling edge of CAS. Table 2-1. Operation Mode RAS Falling Ed, CaS aiing 9° Falling Edge Operation Mode [ems BSE WAVE ORF | sr | rete te [ep | bepe pe pet 8 Cae eC PH [A | & | & [| 4 || Block mask write cycle (New mask/Old mask)Nol * Peep [| § [entre xc Pepe te fet fefefoue fe] x | E | Single write data transfer cycle (New mask/Old mask)Note * fuH[e fetal «x | | split write data transfer cycle (New mask/Old mask)Nete 1 CAS RAS i Note 1,2 fefx|[=« felt =x | A GAS before RAS refresh cycle (Option reset)" x {oH [| x é cas fore RAS retresh cya (No reset) Petx[ et [u[ = | 8 | CAS before RAS refresh cycle (STOP register set)Note 2 Notes 1. Observe the following conditions when using the new mask data or old mask data in these cycles. (1) Old mask data Can be used after setting the mask data using the write mask register set cycle. (2) New mask data Can be used after setting the mask data using the CAS before RAS refresh cycle (Option reset cycle). 2. The STOP register is set to “FFH (11111111)" by the optional reset cycle. Remark H : High level, L: Low level, x: High level or low level 122 WM b4275e5 0063813 314

NEC uPD482234, 482235 2.1. Random Read Cycle This product has a common 8-bit input/output pin. To output data, specify the address using the RAS and CAS clocks and then set DT/OE to low level. The data output will be kept until one of the following conditions is set. (1) Set RAS and CAS to high level (2) Set DT/OE to high level (3) Set WB/WE to low level The read cycle and data transfer cycle are differentiated according to the level of DT/OE at the falling edge of the RAS clock. If DT/OE is set to low level at the falling edge of-the RAS clock, data transfer cycle operations will be initiated. Therefore, to set the read cycle, input a high level above ton (MIN.) to DT/OE from the falling edge of the RAS clock, and then input a low level. Caution Set the DSF to low level at the falling edge of RAS. if set to high level, the memory cell data cannot be output. 2.1.1, Extended Read Data Output (uPD482235) The uPD482235 adopt the hyper page mode cycle which is a faster read/write cycle than the fast page mode of the uPD482234 (Hyper page mode cycle time: 30 ns (MIN.)).. With this cycle, the read data output can be kept until the next GAS cycle, and because the output is extended, the minimum cycle can easily be used. For example, by fixing DT/OE at low level after dropping RAS and executing the hyper page read cycle, each time the column address is latched at the falling edge of CAS, the data output will be updated and kept until the next falling edge of CAS. As a result, the output will be extended only during CAS Precharge time (tcr) as compared to the normal fast page mode. Figure 2-1. Extended Data Output of Hyper Page Mode RAS (Input) tor tor “ yan nye Ol peed YVVY YYY VYYVVYVYVVY Address (Input) ( X> KXXXXX __ XXX K_ XXXXXXXXXKX TOE (Input) TIT tt [ete] Note [Notes [Note [Note 1] Note? | ig = Notes 1. Time during which the output data is kept in the fast page read cycle. 2. Time during which the output data is kept in the hyper page read cycle ( [i] part: Extended data output). 123 Mi 6427525 0063814 250

NEC pPD482234, 482235

2.2 Random Write Cycle (Early Write, Late Write)

There are three types of random write cycles-the early write and late write. To use these cycles, activate the RAS and CAS clocks and set WE/WE to low level. The WB/WE also controls the mask data for the write-per-bit function (mask write cycle). Therefore, when performing the normal write cycle which does not use the write-per-bit function, set this pin to high level at the falling edge of the RAS clock.

2.2.1 Early Write Cycle

The early write cycle controls data writing according to the CAS clock. To execute this cycle, set WE/WE to low level earlier than the CAS clock. The write data is taken into the device at the falling edge of the CAS clock.

2.2.2 Late Write Cycle

The late write cycle controls data writing according to the WE clock. To execute this cycle, set WB/WE to low level later than the CAS clock. The write data Is taken into the device at the falling edge of WB/WE. To set the output to high impedance at this time, keep DT/OE at high level until WE/ WE is input.

2.3 Read Modity Write Cycle

The read modify write cycle performs data reading and writing in one RAS and CAS cycle. To execute this cycle, delay WB/WE from the late write cycle by trwo (MIN.), two (MIN.), and tawo (MIN.). Follow the toez and toeo specifications so that the output data and input data do not clash in the data bus. The data after modification can be input after more than toeo (MIN.) from the rising edge of DT/OE. 124 M™@ 6427525 0063815 197

NEC uPD482234, 482235

2.4 Fast Page Mode Cycle (uPD482234)

The uPD482234 adopt the fast page mode. This mode accesses memory cells in the same row array in about 1/3 of the time taken by the normal random read/write cycle. This fast page mode cycle is executed by repeating the CAS clock cycle more than two times while the AAS clock is being activated. in this mode read, write and read modify write cycles are available for each of the consecutive CAS cycles within the same RAS cycle.

2.5 Hyper Page Mode Cycle (uPD482235)

The uPD482235 adopt a hyper page mode cycle which is a faster read/write cycle than the fast page mode of the uPD482234 (Hyper page mode cycle time: 30 ns (MIN.)). In this cycle, because the read data output is kept until the following CAS cycle and as a result, the output is ‘extended, the minimum cycle can easily be used. The output is extended compared to the normal fast page mode of uPD482234, Refer to 2.1.1 Extended Read Data Output,

2.5.1 Setting the Output to the High Impedance State

The hyper page mode can use one of three methods of setting the output pin to the high impedance state depending on the version; these methods are WE control and OE control (latched control). M™ 6427525 OOb38lb O23 125

NEC uPD482234, 482235

2.6 Flash Write Cycle

This cycle writes the color register data in a 4,096-bit memory cell in one cycle. The memory cell range for one flash write cycle is 512 columns on the same row address (512-column x 8 - IO = 4,096 bits). 2.6.1. Execution of Flash Write Cycle To execute the flash write cycle, set WE/WE to low level at the falling edge of RAS. By using the write-per-bit function (new mask data/old mask data), only the required W/IO can be selected and written Figure 2-4. Memory Cell Range That Can be Written with Flash Write Cycle Sty Ve yOR Yoon al / | Gi 8 512 Columns: 1 Remark is the memory cell range that can be written in one flash write cycle. M@™@ 6427525 0063818 ITb 27

NEC pPD482234, 482235

2.7 Block Write Cycle

This cycle writes the color register data in 32-bit memory cell in one cycle. The memory cell range in which data can be written in one block write cycle is four continuous columns on one row address (4-column x 8 - 10 = 32 bits). Any column of the four columns can be selected and writing prohibited. Determine whether to write or prohibit writing according to the data selected for column. 2.7.1. Free Column Selection Determine which column to select according to the W/IO pin to which the data selected for the column is to be input. ‘The four columns (1st to 4th) correspond to WO to W3/100 to 103 to which the data selected for column will be input (The following table shows the 1st to 4th columns specified by AQ and Ai and the corresponding WIIO pins to which the data selected will be input.).

2.7.2 Column Select Data

Input column select data for every four columns at the 32 bits (4-column x 8-10). The data will be written if the column select data is “1”. Writing will be prohibited if the column select data is “0”.

2.7.3 Execution of Block Write Cycle

At the falling edge of the slowest signal (CAS, WE/WE), input the “1” column select data or “0” column select data to WO to W3/I00 to 103 corresponding to columns 1st to 4th. By using the write-per-bit (new mask data/old mask data) function, only the required W/IO can be selected and written, Table 2-2. 1/0 Pins input with Column Select Data Corresponding to Columns 1st to 4th Column Address and Corresponding Selected 4 Columns Wao Pin Column Select Data prem fp

128 WB 6427525 0063819 632 mm

NEC pPD482234, 482235 Figure 2-5. Memory Cell Range That Can be Written in Block Write Cycle

512 Rows|

9812 Columns Ey,

4th Columns (W3/I03) 3rd Columns (W2/102) ‘2nd Columns (W1/101) 1st Columns (WO/100) Remarks 1. is the memory cell range that can be written in one block write cycle. 2. ( is the W/IO pin input with the column select data.

2.8 Register Set Cycle (Color Register, Write Mask Register)

This cycle writes data in the color register and write mask register. To execute the register set cycle, set CAS, DT/OE, WB/WE and DSF to high level at the falling edge of RAS. Determine which register to select according to the DSF level at the falling edge of CAS. The register set cycle also serves as the RAS only refresh cycle. Table 2-3. Register Selection DSF level at GAS falling edge Caution After selecting the write mask register and writing the mask data, the write-per-bit function In the mask write cycle will be set for the old mask register. Refer to 2.9.1 Write-Per-Bit Function. 620 554 a 129 mM 6427525 00b3

NEC HPD482234, 482235

2.9 Mask Write Cycle

Cycles that use the write-per-bit function during the random write cycle, flash write cycle, block write cycle, write data transfer cycle, are called mask write cycles. In the fast page/hyper page mode write cycle, the mask data cannot be changed during the GAS cycle,

2.9.1 Write-Per-Bit Function

The write-per-bit function writes data using the mask data only in the required !0-pin. It writes when the mask data is “1” and prohibits writing when the data is “0”. Table 2-4. Mask Data Selection www

2.9.2 Selecting Mask Data

There are two ways of selecting mask data. One is the new mask data method and the other is the old mask data method. With the new mask data method, new mask data is set in the cycle writing. With the old mask data, mask data set in the write mask register is used. (1) New Mask Data Method This method is usable in all versions. To switch to the mode using new mask data, set the DSF to low level at the falling edge of CAS in the CAS: before RAS refresh cycle. As a result, the write-per-bit function can be used using the old mask data from the next mask write cycle. (2) Old Mask Data Method To switch to the mode using old mask data, set the DSF to low level at the falling edge of CAS in the write mask register set cycle, and write the mask data in the write mask register. As a result, the write-per-bit function can be used using the old mask data from the next mask write cycle.

2.9.3 Execution of Mask Write Cycle

To execute the write-per-bit function, select the new mask data method or old mask data method, and set WB/WE to low level at the falling edge of RAS of each write cycle. At this time, input the mask data to the W pin in the write cycle using the new mask data. In the write cycle using the old mask data, as the mask data set to the write mask register will be used, there is no need to input the mask data to the W pin. This function is valid only at the falling edge of RAS. In the fast page/hyper page mode write cycle, the mask data determined in the first RAS cycle for moving onto the next fast page/hyper page mode will be valid while the fast page/hyper page mode write cycle continues. 130 @@ 6427525 0063821 450

NEC uPD482234, 482235

2.10 Refresh Cycle

The refresh cycle of this product consists of the CAS before RAS refresh cycle and refresh cycle using external address inputs (RAS only refresh and read/write refresh). The refresh period is the same as the DRAM (Standard), 512 cycles/8 ms. 2.10.1. Refresh Cycle Using External Address Input (RAS Only Refresh and Read/Write Refresh) By specifying the row address using the 9 bits between AO to A8 at the falling edge of RAS, setting CAS and DT/OE to high level, and keeping CAS at high level while RAS is low level, the memory cells on the specified row address (612 x 8 bits) can be refreshed. At this time, refresh is executed, WO to W7/100 to 107 pins are kept at high impedance, and information such as memory contents, register data, function settings, etc. are all also kept. At the falling edge of RAS, all cycles whose CAS are high level input the external address. Therefore, in addi- tion to the read/write cycle operations, etc. refresh operations similar to the RAS only refresh operations will be performed. For this reason, in systems in which addresses in the memory are always increased or decreased, it may not be necessary to perform refresh again. When several devices exist on one bus, data will clash in the bus during the above read/write operations unless each device is equipped with a buffer. Consequently, as it is necessary to set the /O line to high impedance beforehand during refresh, normally the RAS only refresh operation is used.

2.10.2 CAS Before RAS Refresh Cycle (Including Hidden Refresh)

When GAS is set to low level at the falling edge of RAS, the refresh address is supplied from the internal refresh address counter. The internal refresh address counter is increased automatically each time this refresh cycle is executed, During this refresh cycle, functions of random access port and serial access portare selected as follows according to the DSF and WB/WE levels at the falling edge of RAS. (1) When DSF is low level: Optional reset All STOP register data become "1" and the mask write cycle switches to the new mask data method. (2) When DSF is high level and WB/WE is low level: STOP register set The STOP register data is input from the AO to A7 pins at the falling edge of RAS. (3) When DSF, WB/WE is high level: No reset Only refresh operations are performed and the function selection state is kept. In all cases, the W/IO pin is kept at high impedance. When CAS and DT/OE are kept low level while the mode is changed to the CAS before RAS refresh cycle following the read cycle, and RAS is activated, the hidden refresh cycle will be initiated. In this cycle, the W/IO pin does not become high impedance and the data read in the former read cycle will be kept as itis. Because internal memory operations are equivalent to CAS before RAS refresh, no external addresses are required. Like GAS before RAS refresh, in the hidden cycle, functions will be selected according to the level of DSF, WBAWE at the falling edge of RAS. Operations are guaranteed when DSF is low level and when DSF, WB/WE are high level. 131 @@ 6427525 00b38ee 327

NEC a a ____ HPD482234, 482235 3. Serial Access Port Operations There are two types of data transfer cycles-data transfer from the random access port to the serial access port (read data transfer) and data transfer from the serial access port to the random access port (write data transfer). There are also two types of data transfer methods-single data transfer and split data transfer. To set the data transfer cycle, input high level to CAS and input low level to DT/OE at the falling edge of RAS. The data transfer type differs according to the input levels of WB/WE, and DSF at the falling edge of RAS. Table 3-1. Serial Access Port Operation Mode — — Data Transfer T) GAS |DTIGE OSF ype Transfer Source Transfer Destination pute ufe | Single read data transfer Random access | Serial access Pow fe Tw [et | spitread data ranster per pert } H | t [ t | | Single mask write data transterNot | Serial access | Random access | + | ct [ t | # | Splitmask write data transterNote | Port port Note Write-per-bit function can be specified. Remark H: High level, L: Low level 132 M™ 6427525 0063823 cb3

NEC uPD482234, 482235 - 3.1. Single Data Transfer Method With this method, 512 words x 8 bits (whole memory range of serial access port) data is transferred at one time. This method can be used in both write data transfer and read data transfer. 3.1.1. Single Read Data Transfer Cycle This cycle transfers the 4K-bit (512 words x 8 bits) data of the random access port to the serial access port in one cycle. {a) Setting of Single Read Data Transfer Cycle To set the data transfer cycle, input a high level to CAS and WB/WE and low level to DI/OE and DSF at the falling edge of RAS. Using the row address input to AO to A8 at the falling edge of RAS, the memory cells (512 words x 8 bits) of the transfer source of the random access port can be selected. The address data input to AO to A8 at the falling edge of CAS will be latched as the TAP register data of serial access port. Refer to 3.4 TAP Register. {b) Execution of Single Read Data Transfer Cycle To execute the data transfer cycle, set the single read data transfer cycle and then input a high level to DT/ OE and RAS. When SC is active (edge control), data transfer will be executed at the rising edge of DT/OE. When SC is inactive (self control), it will be executed at the rising edge of RAS. At the same time, the serial address Pointer jumps to the start column (TAP) of the next serial read cycle, and the TAP register will be set the empty state. After the transfer is completed, the new serial access port data is output after tsca following the rise of the SC clock that occurs after tsow if the SC is active, and after tsonn if SC is inactive. Caution When the single read data transfer cycle is executed while the serlal access port Is performing serial write operations, the serial access port will start serial read operations at the rising edge of RAS. Refer to 4. Electrical Characteristics Read Data Transfer Cycle (Serial Write + Serial Read Switching) Timings. 133 WM 6427525 0063824 LTT

NEC uPD482234, 482235

3.4.2 Single Mask Write Data Transfer Cycle

This cycle transfers 4K-bit (512 words x 8 bits) data of the serial access port to the random access port in one cycle. Because WBIWE is low level at the falling edge of RAS, the write-per-bit function always functions in this. transfer cyole. Refer to 2.9 Mask Write Cycle. (a) Setting of Single Mask Write Data Transfer Cycle To set this cycle, latch the data to be transferred to the serial access port, and then input a high level to CAS and low level to DT/OE, WB/WE, and DSF at the falling edge of RAS. Because the write-per-bit function functions in this transfer operation, for the new mask data method, the mask data must be supplied to WO to W7 at the falling edge of RAS, and for the old mask data method, there is no need to control the mask data. The memory cells (512 words x 8 bits) of the transfer destination of the random access port are selected using the row address input to AO to A8 at the falling edge of RAS. The address data input to AO to A8 at the falling edge of CAS is input as the TAP register data of serial access port. Refer to 3.4 TAP Register. (b) Execution of Single Mask Write Data Transfer Cycle To execute this cycle, set the single write data transfer cycle and then input high level to RAS. Data will be transferred at the rising edge of RAS. At the same time, the serial address pointer jumps to the start column (TAP) of the next serial write cycle, and the TAP register will be set the empty state. After the transfer is completed, the new serial access port data is latched at the rising edge of the SC clock that occurs after tsoHr. Caution 1. When the single mask write data transfer cycle is executed while the serial access port is performing serial read operations, the serial access port will start serial write operations at the rising edge of RAS. Refer to 4. Electrical Characteristics Write Data Transfer Cycle (Serial Read — Serial Write Switching) Timings. 2. Always make CAS low level in the write data transfer cycle and latch TAP. If write data transfer is performed without setting TAP, serial access port operations cannot be ensured until elther one of the following points. If the SC clock is input during this time, the serial register value also cannot be guaranteed. + Until the falling edge of C.S during the write data transfer cycle + Until the read data transfer cycle is executed again Figure 3-1. Single Write Data Transfer and TAP Operation Before transfer After transfer Random Access Port Yi Random Access Port TAP register TAP registe’ ies Serial Access Por [SESE z a TAP 134 M@™ 6427525 0063825 036

NEC uPD482234, 482235

3.2 Split Data Transter Method

With this method, the 512 words x 8 bits (whole memory range of serial access port) data is divided into the lower column (0 to 255) and upper column (256 to 511), each consisting of 256 words x 8 bits. Because the columns are divided into upper and lower columns with this method, data transfer can be performed ‘on lower column (or upper column) while performing read/write operations in the upper column (or lower column). For this reason, transfer timing design is easy. This transfer method can be used in both write data transfer and read data transfer.

3.2.1 Split Read Data Transfer Cycle

This cycle divides the 4K-bit (512 words x 6 bits) data of the random access port into the lower and upper columns and transfers them to the serial access port. In this cycle, the serial read/write can be performed in the columns to which data is not transfer. (a) Setting of Split Read Data Transfer Cycle To set this cycle, input a high level to CAS, WB/WE and DSF, and low level to DT/OE at the falling edge of RAS. The memory cells (512 words x 8 bits) of the transfer source of the random access port are selected using the row address input to AO to A8 at the falling edge of RAS. And the address data input to AO to A7 at the falling edge of CAS is latched as the TAP register data of serial access port. Refer to 3.4 TAP Register. There is no need to control address data input to A8). (b) Execution of Split Read Data Transfer Cycle To execute this cycle, set the split read data transfer cycle and then input the high level to RAS. Data will be transferred at the rising edge of FAS. Data is transferred from the random access portto the serial access port automatically at the column side (Column not pointed to by the serial address pointer) where serial access portis inactive. To confirm the transferred column side, check the output state of the QSF pin. Refer to 3.3.3 QSF Pin Output. When the serial address pointer comes to the jump source address specified by the STOP register, the serial address pointer jumps to the start column (TAP) of the serial read/write cycle at the inactive column side, and the TAP register will Be set the empty state. 135 M@™ 6427525 0063426 T72

_ NEC uPD482234, 482235

3.2.2 Split Mask Write Data Transfer Cycle

This cycle divides the 4K-bit (512 words x 8 bits) data of the serial access port into the lower and upper columns and transfers them to the random access port. In this cycle, serial read/write can be performed for columns to which data is not transferred. Because WB/WE is low level at the falling edge of RAS, the write-per-bit function always functions in this transfer cycle. Refer to 2.9 Mask Write Cycle. (a) Setting of Split Mask Write Data Transter Cycle To set this data transfer cycle, input a high level to CAS and DSF and low level to DT/OE, WE/WE at the falling edge of RAS. Because the write-per-bit function functions in this transfer operation, for the new mask data method, the mask data must be supplied to WO to W7 at the falling edge of RAS, and for the old mask data method, there is no need to contro! the mask data. The memory cells (612 words x 8 bits) of the transfer destination of the random access port are selected using the row address input to AO to A8 at the falling edge of RAS. The address data input to AO to A7 at the falling edge of CAS is input as the TAP register data. Refer to 3.4 TAP Register. There is no need to control address data input to A8. (b) Execution of Split Mask Write Data Transfer Cycle To execute this cycle, set the split write data transfer cycle and then input high level to RAS. Data will be transferred at the rising edge of RAS. Datais transferred from the serial access port to the random access port automatically at the column side (Column not pointed to by the serial address pointer) where the serial ‘access portis inactive. To confirm the transferred column side, check the output state of the QSF pin. Refer to 3.3.3 QSF Pin Output. When the serial address pointer comes to the jump source address specified by the STOP register, the serial address pointer jumps to the start column (TAP) of the serial read/write cycle at the inactive column side, and the TAP register will be set the empty state. 136 @@ 6427525 0063827 505

NEC uPD482234, 482235 Figure 3-2. Split Mask Write Data Transfer and TAP Operations Before transfer (Upper colurnn) After transfer (Upper column) Random Access Port ri Random Access Port TAP register TAP register Serial Access Port [_] Serial Access ~C— TAP data 1 Soria write start Before transfer (Lower column) After transfer (Lower column) Random Access Port =a Random Access Port | Z sesteation TAP register Z ee TAP register S| || few] Serial Access Port Ges Serial Access ror T | — TAP data 2 ‘Serial write start (TAP data 1)

3.3 Serial Read/Write

The serial access port (512 words x 8 bits) is independent from the random access port and can perform read and write operations. The serial access port performing single data transfer and split data transfer can not perform read and write operations independently. Caution When the power is turned on, the serial access port sets into the Input (write) mode and the SIO pin is the high impedance state. 137 M@ 6427525 0063828 84S mw

NEC _ HPD482234, 482235

3.3.1 Serial Read Cycle

To set the serial read cycle, perform the single read data transfer cycle (The mode will not change in the split read data transfer cycle.). Execute the single read data transfer cycle and latch the data and TAP data. By inputting a clock signal to the SC pin and inputting a low level to the SE pin, data will be output from the serial address pointer specified by TAP register. The data synchronizes with the rising edge of the SC clock and is output from the SIO0 to SIO7 pin, and the data is kept until the next rising edge of the SC clock. (a) Reading-Jump The SE pin controls the SIO pin output buffer independently from the SC clock. By setting the SE pin to high level even while inputting the SC clock, SIO0 to SIO7 pins become high impedance. But the operations of serial address pointer will be continued while the SC clock is being input even though reading has been prohibited from SE pin. Reading-jump of the column can be performed using this function.

3.8.2 Serial Write Cycle

To set the serial write cycle, perform the single write data transfer cycle (The mode will not change in the split write data transfer cycle.). To prevent the transfer data from being written in the memory cell of the random access port, set all bits of the mask data to “O" and control the mask data. Exeoute the single write data transfer cycle and set the serial write cycle. By inputting the clock signal to the SC pin and inputting a low level to the SE pin, data can be latched from the serial address pointer specified by TAP register. The data synchronizes with the rising edge of the SC clock and is input from SIO0 to SIO7 pins. Be sure to follow the specifications for the setup time (tses) and hold time (tsex) of SE pin for the SC clock. {a) Writing-Jumps (Intermittent Writing) The SE pin controls writing operations independently from the SC clock. By setting the SE pin to high level even while inputting the SC clock, writing will not be executed. But the operations of serial address pointer will be continued while the SC clock is being input even though writing has been prohibited from SE pin. These functions enable writing-jumps (intermittent writing) to be performed. The masked data is kept as the old data.

3.8.3 QSF Pin Output

QSF pin determines whether the serial address pointer is at the upper column side (addresses 256 to 511) or the lower column side (addresses 0 to 255) at the rising edge of the following SC clock during serial read or write. in other words, it outputs the uppermost bit (A8) of the column address of the serial address pointer. During split data transfer cycle, data is transferred at the column side where serial access port is inactive. The following table shows the QSF pin output state and the access pointer of following SC clocks. 138 Mi 6427525 0063829 74)

NEC 1482234, 482235

3.4 TAP (Top Access Point) Register

The TAP register is a data register which specifies the start address (first serial address point = TAP) of the serial read or serial write. Set data to this register each time a transfer cycle is executed.

3.4.1 Setting of TAP Register

The data input to AO to A8 (AQ to A7: Split data transfer) at the falling edge of CAS during the setting of a transfer cycle is set as the TAP register data. By executing the transfer cycle, the start address of the following serial read (or write) operations is specified by the data of the TAP register and the TAP register will be kept in the empty state until the TAP register is set again. In the split data transfer cycle, because the inactive serial access port column addresses are specified by the data of the TAP register automatically, there is no need to control the AS data. Caution When the TAP register is empty, the address following the 511 serial address point will be 0. Inaddition, because the serial address pointer will not jump to the column specified by the STOP register, the binary boundary jump function cannot beused. Refer to 3.6 Binary Boundary Jump Function.

3.5 STOP Register

The STOP registers a data register which determines the column of the jump source when jumping to a different column side (lower column or upper column) in the split data transfer cycle. Five types of columns can be selected for starting jump (jumping is possible at 2, 4, 8, 16, and 32 points). The following table shows the correspondence between the column at the jump source and data of the STOP register. Once set, the STOP register data is kept until it is set again. 3.5.1. Setting of STOP Register To set the STOP register, set WBAVE to low level at the falling edge of RAS in the CAS before AS refresh cycle. The data input to AQ to A7 will be input as the STOP register data. 139 MB 6427525 0063830 4T3

___NEC | a __ PD 482234, 482235 0 Table 3-2. STOP Register Data and Jump Source Column STOP Register Data Jump § Bit Column (Decimal Number : jource Bit Column (Decimal Nu [a7 [As].A5 4 [a9 1 a0 ve eure one 127, 255 1 14 319, 383, 447, 511 + lane 31, 63, 95, 127, 159, 191, 223, 255 287, 319, 351, 383, 415, 447, 479, 511 1, 31, 47, 63, 79, 95, 111, 127, 143, 159, 175, 191, 207, 223, 239, 255 271, 267, 303, 319, 335, 351, 367, 383, 399, 416, 431, 447, 463, 479, 496, 511 Remark A8: Don't care. Caution When the power Is supplied, all STOP register data will be undefined.

3.6 Binary Boundary Jump Function

This function causes the serial address pointer jump to the TAP specified by the TAP register when the pointer moves to a column specified by the STOP register (split data transfer). This function cannot be used when the jump destination address is not set (TAP register is empty). This function facilitates tile map application which divides the screen into tiles and manages data for each tile.

3.6.1 Usage of Binary Boundary Jump Function

After setting the STOP register, execute the single read (or write) data transfer and initialize the serial access port, The initialization process will switch the serial access port read (or write) operations, set TAP, set the serial access port data, and set the TAP register to empty. By inputting the serial clock in this state, the serial access port will read (or write) operations from TAP in ascending order of address. Because the TAP register is in the empty state, the address at the jump source set by the STOP register will be ignored, and the serial address pointer will move on. When the column to be jumped approaches, execute split data transfer and set new TAP data in the TAP register. The serial pointer will jump at the desired jump source address. Jump can be controlled freely by repeating these operations. 140 M@™® 6427525 0063831 337 mw

NEC uPD482234, 482235

3.7 Special Operations

3.7.1. Serial Address Set Operations Because the serial address counter is undefined when the power up, the serial access port operations when the SC clock is input are not guaranteed. Execute single read (or write) transfer after turning on the power. The serial access port will be initialized, enabling serial access port operations to be performed.

3.7.2 Lap Around Operations

Mall the data of the registers read (write) during data transfer while the serial read (write) cycle is being executed, the serial pointer will repeat 0 to 511.

3.7.3 Cycle After Power On

After supplying power, initialize the internal circuitry by waiting for atleast 100 ys after Vcc 2 4.5 V, then supplying at least 8 RAS clock cycles. The RAS clock only requires that tao, tras, and tre are satisfied; there is no problem if other signals are in any state. Note however that if the signal supplied to RAS, CAS, DT/OE, and WE/WE is high at power-on, the serial access port and each register have the following values. @ Mask register crn All" @TAP register nnn Undefined @STOP register... Undefined @® 6427525 0063832 27b 1

NEC ___ pPD482234, 482235 4. Electrical Characteristics Absolute Maximum Ratings [Frans [Sma [as SC [output curent Te Ps [Powe despain | id Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits in the operational sections of this characteristics. Exposure to Absolute Maximum rating conditions for extended periods may affect device reliability. Recommended Operating Conditions [———Paraior Sym [wan [VP [ wa [on] [simvwince de “| as | so | ss |v [ih evetinutviage | vw [ea | [ss | v_| Operating ambient temperature [ Ta | o | | 70 | °c_| 142 M@ 6427525 0063833 102

NEC 'D482234, 482235 DC Characteristics 1 (Recommended operating conditions unless otherwise noted) Input leakage current Vin = 0 V to 5.5 V, -10 +10 | pA Other inputs are 0 V Output leakage current fou W/O, SIO, QSF are inactive, | -10 +10 | WA Vour = 0 V to 5.5 V Random access port Von (R) v high level output voltage Random access port Vou (R) fou (R) = 2.1mA v low level output voltage Serial access port Vou (S) v high level output voltage Serial access port Vo (S) Vv low level output voltage Capacitance (Ta = 25 °C, f = 1MHz) [Pernt [Sm [ —_—Tetcoaone a [96 Jun] va] Input Capacitance RAS, CAS, WB/WE, DT/OE, DsF,se,sc[ | | 6 | was Cet [ove capestace [cose | tp 7 for] 143 Me 6427525 0063834 O45

NEC uPD482234, 482235 DC Characteristics 2 (Recommended operating conditions unless otherwise noted)Not 1 (uPD482234) Random Access Port [ standoy [active | ‘Symbol [wn [wax [mn] wax_| Conditions te = a MIN}, f= Om | fof Tf ws] | | Da = high impedance a Pt EY [fel= {tf [ml BiB cye O88 <n ea ee te re (MIN) | folie [| ss P| | ft oc Nee be tn), a de feces et tet pet ett a See et fet tet te = a a 2 fete ef | ese tet peer ne ee Notes 1. Noload on W/IO, SIO, QSF. The current consumption actually used depends on the output load and ting fr f each pin. 3. RAS, CAS, and SE remain at Vin > Voc - 0.2 V, and AO to A8, WE/WE, DT/OE, DSF, SC remain at Vin 2 Veo ~ 0.2 V or Vi. s GND + 0.2 V. 4, hen the acress input is set wo ‘Vi or Vit during the tras period. 5. Value when the address in tec one cycle is changed once when tec = tec (MIN.). 144 WM 6427525 0063835 Tas mm

NEC uPD482234, 482235 DC Characteristics 2 (Recommended operating conditions unless otherwise noted)Note + (uPD482235) ee eae Renter Acer Pot | ry [rc] [nT wa] Ont oo te (MIN) fo = Oma | fof Tf se | Pou = high impedance ee ee = ee a Ss RAS only refresh cycle | o | [ee [ [ono [| ns | See Sper ereyer [fof tee [fv [Tes | i 2 a ne Sse St et ee tec = tac (MIN.) [| fofee [we TPs] ecm feb fet Pet pert tne = tre (MIN.) | fofen [Pe [Pe] TT Pema fet fet pet = bal ee Notes 1. No load on W/IO, SIO, QSF. The current consumption actually used depends on the output load and operating f f each pin. 2A change inrow adtresses cst not occur more than once in tac = tac (MIN.).. 3. RAS, CAS, and SE remain at Vin > Voc — 0.2 V, and AO to A8, WE/WE, DT/OE, DSF, SC remain at Vin 2 Veo ~ 0.2 V or Vu < GND + 0.2 V. 4. When the address input is set to Viv or Vit during the tras period. 5. Value when the address in thec one cycle is changed once when tuec = tec (MIN.).. M@™ 6427525 O0b383b 911 “se

NEC pPD482234, 482235 AC Characteristics (Recommended operating conditions unless otherwise noted) + All applied voltages are referenced to GND. + After supplying power, initialize the internal circuitry by waiting for at least 100 us after Voc 2 4.5 V, then supplying at least 8 RAS clock cycles. The RAS clock only requires tac, tras, and tre are satisfied; there is no problem if other signals are in any state. + Measure at tr = 5 ns + AC characteristic measuring conditions (1) Input voltage, timing (2) Output voltage determined -- 3.0V Vuipen #24 V Tf X Vowsm «20 <-===" Vous) = O.8V = —nn an i X+ov Voummxy 2 0.8V --===-- atte tre5ns tr=5ns (3) Output load conditions Random Access Port Serial Access Port Ves Vee 1,838.2 1,838.2 wid sio “80 pF 30 pF a al 993.0 a t 993.0 146 M@™ 6427525 0063837 658 a

NEC 482234, 4822395 (Common) (1) Parameter Symbol ‘uPD482235-60 HPD482235-70 Conditions jm LS |] [Random read or write oycletime [tre | 120 [| 40 | [me] +4 cess te von RAS [ me | [|e aces tine om cour aioe [iw [| so [as Pp ee [Access time trom OE [toe | | ts | | 20 ps | id RAS pectage ime [we [ep CAS precharge time [ee a al rama | = 1°] | *t [et | (Fast page/Hyper page mode) [oxS nono RAS ow peste el ww | 8 [|e [RAS high to CAS ow precharge time| we | 10 | | 10 | ||| [RAS pulse width (Non page moae) [ws | 60 | 10,000 70 | 10,00] ns | + [revssetope pecan | > | © [se] frme[ m [| (Fast page/Hyper page mode) [EAS puise with teas [16 | 10000[ 20 | 10000] ms | _*d| [EAS pulse with [eas [10 [10,000 [10 | 10,000 ns | _—*d We conmanseusewan | we [ve Pe PP PF [RAS hoistime Tee | te || to | CUd s | C*d |cAShoidime ftom | oo [| | Up | Cd [Row address setup time [wan | 0 | | 0 | ns | +d [Row address holdtime [tm | 10 | ‘| 10 | |r| ~+4 [Column adcress sewn time | wwe | o | | o | [ns] | [Column address holdtime [tom | 10 | | 10 | [re] +4 [Read command setuptime | ms | o | | o | [ns] | [Datainsetuptime | tos | 0 | Cd 0 | —~*d ne | Note | [Datainhoidtime | tm | 2 | | 2 | +d ns | Notoa | JOT rionsewptme we fo | | o | [mm] 4 [tion seme [tow | oP Jwrterpersit setuptime [ws | 0 | | 0 | dt rs | Sd Witeserstbo ine [tw [fo [ [er JOSF setup time tomas | ws | o | | 0 | [ns |_| JOsF hoidtimetrommas [wm | 1 | | 1 | [nm || JOSE setuptime rom GAS [wes | 0 | | o | | =| +d [DSF hoidtimefrom Gas [wen | 10 | | @ | ||| ME L427525 0063838 794 mm “7

NEC pPD482234, 482235 (2/2) uP0482234-60 | uPD482294-70 Parameter ‘Symbol |__#P0482235-60 #PD482235-70_| Unit [a [ woe [ne [na | Writeper-biteclection setuptime [ws [0 [ [oT [ins [| Wrte-perbit selection hoid time [tm | 10 [| to [ [ns [| Foolumn address to RAS ead tne [tw [20 | | 35 | [=] | [wie command to RASead ime [tom [20 | | 0 | [|_| lwite conmandio CAS tead time [em [6 | | | [m=] | RAS to column adress dlaytine | two | 16 | 90 | 18 | 6 | vs [owt | Output disable time rom AAS high | tm | 0 [15 [0 [15 | ns [Notes 4 | Ouput disable tine fom GAStigh | torr _[ 0 | 15 [0 | 16 | os [Nowss4 | Output disable time from CAS high (Hyper page mode) Output disable time from OE high | tex [0 | 16 | o | 16 [ns | Notwsa,4 | Output dsabe tine om WEAVE ow] wer | 0 | 16 | 0 | 18 | ns | Notes | lite command puse wath [wx | 10 | | 12 | | ns [Nota | Notes 1. For read cycle, access time is defined as follows: imo we WAR) ard veo SR TWAKT | toe wR | we OO | trap > taro (MAX.) and taco < taco (MAX.) | taa (MAX.) tran + tas (MAX.) ie A) trao (MAX.) and treo (MAX.) are specified as reference points only; they are not restrictive operating parameters. They are used to determine which access time (trac, tea, tcxc) is'to be used for finding out data will be available. Therefore, the input conditions tao 2 trao (MAX.) and trop 2 treo (MAX.) will not cause any operation problems. 2. These parameters are referenced to the following points. (1) Early write cycle : The falling edge of CAS (2) Late write cycle : The falling edge of WB/WE: (3) Read modify write cycle : The falling edge of WEAVE 3, tsez, toez, twez, torr, torr, and torc define the time when the output achieves the condition of high impedance and is not referenced to Vor of Vou.

148 M@™ 6427525 0063839 620 a

NEC uPD482234, 482235 4. Control pins RAS, CAS, DT/OE, WEVWE to set pin W/IO to high impedance. Because the timings at which RAS, TAS and DT/GE are set to high level and WB/WE is set to low level affect the high impedance state, the specifications will change as follows. Controlling by RAS is usable in hyper page mode (uPD482235). Fast page mode (uPD482234) a ee a Hyper page mode (uPD482235) Jie [eon Te a Dee [oe Pe a Remark H : High level L : Low level x : Don't care +: Transition 149 M@™@ 6427525 0063840 342

NEC yPD482234, 482235 (Read cycle) Parameter PD482235-60 | _uPD482235-70 | Unit | Conditions [van Twas [a | max. | [Random read orwrte yoletime [two [tao [| 40 [ [ns | [Fastpagemodecyolotime | we | ao | | 4s | [ns | [Hyper page mode cyetetime | we | ao | | a | [ns | | [Access timetromRAS | twe | | 60 | [70 | ns [Nows | [Access timeiromGas|_tow [| 16 | [20 [ne [Notes | [Access ime trom coturm adaress | tm | | so [| 35 | ns [Notes | [Access timetromOE | toe | | 18 [20 [me | | [Access tine trom GAS waling edge | ter [| a5 | [4 [no [| [GE tAASinactive seuptime | toes [0 | | o [ fet | Ea i a RAS high Regen fe tet Te lei | CAS high loupurodimeronGrs | we [a | [8 | [=] | [output dsabie time tom RASTigh [| te [0 | 6 [0 | 16 | ns | Wowon| [output esate time tom CRStigh | tow [0 | 15 | 0 | 16 | ns | Notose a Oa a (Hyper page mode) [ouput disable tine om GEmgh | ox [0 | 1s | 0 | 1 | ws [noweae | [ouput disabio tno fom WAIWE Tow] —twez [| 0 [| 16 | 0 | 16 | no | Noteosa | wee conmenapuse with [we] | | @ | [vm [mows | Notes 1. For read cycle, access time is defined as follows: trao (MAX.) and taco (MAX,) are specified as reference points only; they are not restrictive operating parameters. They are used to determine which access time (trac, tas, tcac) is to be used for finding out data will be available. Therefore, the input conditions trao > tran (MAX.) and taco 2 taco (MAX.) will not cause any operation problems. 2. Either tac (MIN.) or tar (MIN.) should be met in read cycles. 3. tsez, toez, twez, tore, tor, and torc define the time when the output achieves the condition of high impedance and is not referenced to Vou or Vot.

150 M@™@ 6427525 0063841 289 a

_ NEC uPD482234, 482235 4. Control pins RAS, CAS, DT/OE, WEVWE to set pin W/IO to high impedance. Because the timings at which RAS, CAS and DT/OE are set to high level and WB/WE is set to low level affect the high impedance state, the specifications will change as follows. Controlling by RAS is usable in hyper page mode (uPD482235). Fast page mode (uPD482234) a ee Hyper page mode (uPD482235) [ee [eon |e Tea [ee fe ee a Remark H : High level L : Low level x : Don't care — : Transition M@ 6427525 00b3842 115 mm ‘51

NEC pPD482234, 482235 Read Cycle (uPD482234) tee : a : SS SSO GAS (mou) ye I ec pe | Across rout) Ye eT co) ae = 7 WEE tno) Ye acme Lf tons [tora] mr = BTHOE teow Yo | CMM | es a ters || tran 8 trou it~ om Remark Because the serial access port operates independently of the random access port, there is no need to control the SC, SE, SIO pins in this cycle.

182 M§ 6427525 0063843 O51

NEC uPD482234, 482235 Read Cycle (Extended data output: .PD482235) tac te S™~S Ben ee eS rooms toa Ye IRR) io 05, a es Ph Ta oY TIA LZ , MN — DTIOE (i a = eg ae ters tere ose WN VIZPTTTTTTTTTTETTITTTTTTTTTTT Remark Because the serial access Port operates independently of the random access port, there is no need to control the SC, SE, SIO pins in this cycle. Me 6427525 0063844 T98 153

NEC uPD482234, 482235 Fast Page Mode Read Cycle (1PD482234) | te tee tron i ton taco vu- Y = FP VVY¥ YVV¥ = VYVVYYVVYVVYYY Adress (Iau) yu — XY co ¥, C cons KXXX) { cou.2" KXXX) XXXXXKAAAA Ll it AEs . PP er wane oopan = 777/17 ul L ‘7d bees he \\ [cr | [her >| “e mroewoe tT | NL NE 7 "|! Pa LE] | : i: = ; | ‘tr tern ose YW MITTEE LLL Remark Because the serial access port operates independently of the random access port, there is no need to control the SC, SE, SIO pins in this cycle.

154 WM 6427525 0063845 924 me

NEC uPD482234, 482235 Hyper Page Mode Read Cycle (Extended data output: uPD482235) tre es | Smo Yor ( {eee es | -— -— pa oss mou) Ya~ YX ROW WME coun WKY cou KKK) couw KXXKXKKKEKK [AE ss .| [Le F wee anoun Ye 777 /7/ a [| lll wr ae ey Ley |) Peo TOE tone Ye Ne is ae WL. es ae Color Oeemyg anaea fae BE na AXXoatacure KX vara curry }-- snd | uo ose ce) ON MITT TT LTT TL Remark Because the serial access port operates independently of the random access port, there is no need to control the SC, SE, SIO pins in this cycle. M™ 6427525 0063846 860 mm 188

NEC P48 2234, 482235 Hyper Page Mode Read Cycle (WE controlled) (Extended data output: »PD482235) to tres] Joon es Address input) \\— KX { row X) {cous KYXKM cove KXXY) Ec KAAAANAANK Pee ee eal ee: Pres is BTIOE (mewn Y= WA AL/7 ese ere ONT LL 1 Remark Because the serial access port operates independently of the random access port, there is no need to control the SC, SE, SIO pins in this cycle. 186 M@™ 6427525 0063847? 777?

__ NEC uPD482234, 482235 Hyper Page Mode Read Cycle (OE controlled: Latched control) (Extended data output: uPD482235) tre wae w ———s rr na mal sass tro) i. YY FOW KN cous YXXXY cove: KKKXY Cou KKK KXXKKKKK a CT | nl le Ce wawe ino) Yi" 77/77 | Es ea yf tons| wer ts | = CE eereae AIR NNNNY a /, ters| |tran 0s re) YON TTT TTL LT 7 Remark Because the serial access port operates independently of the random access port, there is no need to control the SC, SE, SIO pins in this cycle. MH 6427525 0063848 633 Mm 187

— NEC PD 482234, 482235 (Write cycle) Parameter ‘Symbol HPD482235-60 #PD482235-70 Conditions Pm om ee [Random read or write cycle time | te [120 [| 40 fins | [Fastpage mode cycletime [tre [40 | [45 | [ns | [Hyper page mode cycletime twee 0 | | 35 [fins | [Write command setuptime | tws_ | o [ [| o | [ins | Note | [write command holdtime | twen_ | to | [2 [fins [| |OE high hold time atter WEAWE low | tom [ o [| | o T [ns [ | |writeper-it setup time | twee | oo | fo [fas [| [writepertithoidtime [twee to To [fas [| [Write-per-bt selection setup time [ws [0 [ [ o [ [ne | | [writeperbit selection hoidtime | tw [10 [ [10 [ns | | Note twcs 2 twes (MIN.) is the condition for early write cycle to be set. Dour becomes high impedance during the cycle. trwo 2 trwo (MIN.), tewo 2 tewo (MIN.), tawo 2 tawo (MIN.), are conditions for read modify write cycle to be set. The data of the selected address is output to Dour. If any of the above conditions are not met, pin W/IO will become undefined.

158 MB 6427525 0063849 57T

_ NEC uPD482234, 482235 Early Write Cycle/Early Block Write Cycle tre FAS roa o> {7 a = cn SS tay Y~ ——— tase coy Va- YYV | al WYVWVVVVVVVVVVYVVVVVYVYVVYVV acaress trout) ye- XXX) ROW} 14, K co} COOXOXXXXXXXEXXAXEXKR KAN ‘es Pa a Ve- WV f= all ie wane crown Ve— XX PRwewseer A VTL mle | STE crow Y= 777 a tws ton Paes ae roorerar Ome Yi XXX wea KX oaraiwcou. sect KXKKXXXXRAXXLMKKK " Ly el o osF tmpuy Y= YY MU Note toas for the uPD482234 tuoas for the ¢PD482235 Remarks 1. When DSF is high level : Block write cycle ‘When DSF is low level : Write cycle 2. WPB: Write-per-bit 3. When block write cycle is selected, input the column selection data to DATA IN. 4. Because the serial access port operates independently of the random access port, there is no need to control the SC, SE, SIO pins in this cycle. 159 @™ 6427525 9063850 291 me

NEC uPD482234, 482235 Late Write Cycle/Late Block Write Cycle tre sma RAS (Input) yy | theo tis os a Vem acsress mou Vi XXX ROW KKK OL KXXXXXXXXXXXXXXKXXK = Vu- YY ;— | Y we wenn trou ye XX) X/ ITIL 11 tows | fos Vee | BHOE two) 7/7 VA ws ton WO to W7/ Vu- YY —— VVYVVVVY VVVVVVVVVVY romrowr Cro) Y= XX mat ean KXXXXXXX) KAMARA ose crew Ye= WAN, LXXX set nsses XXYXXXXXXXXKKXXXXXXXAKK Note teas for the wPD482234 tucas for the wPD482235 Remarks 1. When DSF is high level : Block write cycle When DSF is low level: Write cycle 2. WPB : Write-per-bit 3, When block write cycle is selected, input the column selection data to DATA IN. 4. Because the serial access port operates independently of the random access port, thereis noneed to control the SC, SE, SIO pins in this cycle. 160 M@@ 6427525 0063851 128

_NEC uPD482234, 482235 Fast Page, Hyper Page Mode Early Write Cycle/Fast Page, Hyper Page Mode Early Block Write Cycle vs | meme YQ | tec, type Note 1 tec, tec Note t trash tone tes trco, ior | [Ttcas, tacas Mew a] cr by sami $e= BX mom KY Sx” KER MEO ERR) co KIREKLINR twas | - two — Vii = ware tron yo Km KX YN OY NI V7777777 — | [| at as —— Ve — aTIoE rou Ye- Z7 |] AAA Wororor tooud) yr XYf wan XXX PA os KKK Bee KKK ee KXXKKKKKK Te pany pdms pm DSF (put) Ye - LXXX Bes west KX Beresster KKK Bertessr KX XKKKKKK Notes 1. tec for the uPD482234 tec for the uPD482235 2. tcas for the wPD482234 tucas for the uPD482235 Remarks 1. When DSF is high level : Block write cycle When DSF is low level : Write cycle 2. WPB: Write-per-bit 3. When block write cycle is selected, input the column selection data to DATA IN. 4, Because the serial access port operates independently of the random access port, there is no need to control the SC, SE, SIO pins in this cycle. 161 MM 6427525 0063852 Ob

NEC pPD482234, 482235 Fast Page, Hyper Page Mode Late Write Cycle/Fast Page, Hyper Page Mode Late Block Write Cycle frase tre troo _[TTens, tacas Rem? 3,0 ice] [Stcas, trons Note F) Tow CAS (input) ye Lan, | y ve TA AF a WVVY F TW VVVVVVVVVY pcdress mow ye KY ROW KL cours KXXN cou-er KKK OL KKXXXXXKKAK sie] feed) [el fe pay Pa ee wenn Se- Kom NS WS YS wh rn ave tron Y= Tf | ERPS: (ii ts | | to + pl = = sowrordeouy Va YK wae XXX NOX NOX NPM XXXAKX Ele ale ple cor Wt pf mnms KERR KR mem KOR Notes 1. tec for the uPD482234 tuec for the ¢PD482235 2. toas for the uPD482234 twos for the zPD482235 Remarks 1. When DSF is high level : Block write cycle When DSF is low level : Write cycle 2. WPB: Write-per-bit 3. When block write cycle is selected, input the column selection data to DATA IN. 4. Because the serial access port operates independently of the random access port, there is no need to control the SC, SE, SIO pins in this cycle. 162 M@™@ 6427525 0063853 TTC

_ NEC uPD482234, 482235 Flash Write Cycle tre | tom v ee | GAS nou Yo | ANNAANNANANAANANANAANANANANNN tsal | thaw vee Dy TV YY VV YY YY LY YY YY VV YY YYYYYYY accress (rou) ye” XXXN_ ROW _KXXXXXXXXXXXKXXXKXXXKAXKKXKAKAAN twas 7 vase wm Y= WW\\_|| Y2ZZ7ZZITTITTITTTITIIITTT IT ole ore won Y= L77 | ANAANAANAANAAAANAAANAANANNANNNY tws| | tw Pir ieorwror a) Yi AXKYL wanes KXXXXXXKKXXAKAXRKKAKAAXKAXKAXKLAAN tens | tran ose enoun Ye [77 ANNNAANANAANANNANUANAAANNANNNANT Remark Because the serial access port operates independently of the random access port, there is no need to contro! the SC, SE, SIO pins in this cycle. MB 6427525 0063854 937 me ©

NEC HPD482234, 482235 (Read modify write cycle) [Readmoaty wito etme | we [ies | | vs | [we] | Cd lal al write cycle time eae TT write cycle time [coe ine ton OAS valng ape [use [| = || © [m= | | [acess tine rom previous CRS tee | | 00] | |_| wow | [acess tine rom previous WEWE | twe | | ss | eo] | Noto | [witeerst soup ine | wes fo [| 0 | | m |] [witeperntnaigtne | wm | 10 || | [we | | lwitepertit seston supine [ws [0 || 9 | [me |] lwite-portitseeton rine [wm | 10 | | vo | [me | | [OE Woh oi tine ater WEAWE ow | wom [0 | | 0 | [m= |] [CAS 0 WEIWE diay me | ow | 0 | | | | ne | now | [RAS c WEE slay ime | _owo | a5 | | oo | |e | now _| a a al al delay time [SE nono detain aetp dayne | wes 8 | | [| Notes 1. In the hyper page mode, the hyper page mode read modify write cycle, the hyper page mode read modify block write cycle, this parameter is valid when the read cycle changes to the write cycle. 2. twes2 twcs (MIN.) is the condition for early write cycle to be set. Dour becomes high impedance during the cycle. ‘tawo 2 tawo (MIN.), towo 2 towo (MIN.), tawo 2 tawo (MIN.), are conditions for read modify write cycle to be set. The data of the selected address is output to Dour. If any of the above conditions are not met, pin W/IO will become undefined. 164 mm 6427525 0063855 673

NEC uPD482234, 482235 Read Modify Write Cycle/Read Modify Block Write Cycle te v eae [——_ jaa aS ee Across op) Y= XX) son KX con _KXXOXKXKXXXAXNXXXXKX

4 Ey fas ——— | PS

Wave crown Ve= XfwraseeaX VT \\ ar a BTE trout) Ve~ | WSS Wii Pen LTT we || TRE} Ite, tal | tm Sane Rem O, Occ es mmm mas 9. ¢, Wee 0 0,0,0.0,0,0,0,0,0,0 W7/, 100 oez te tres tery Fos tron Vor — osFimeuy ye NN YE Note tcas for the uPD482234 tucas for the uPD482235 Remarks 1. When DSF is high level : Block write cycle When DSF is low level : Write cycle 2. WPB: Write-per-bit 3. When block write cycle is selected, input the column selection data to DATA IN. 4. Because the serial access port operates independently of the random access port, there is no need to control the SC, SE, SIO pins in this cycle. 165 M™ 6427525 0063856 707 me

NEC #PD482234, 482235 Fast Page Mode Read Modify Write Cycle (uPD482234)/ Fast Page Mode Read Modify Block Write Cycle (uPD482234) trase: tre cme YY RAS (Input) yy treo si fe tors Ve = 4 Les. a Ke me Se es eee Aasress tout) VI= XY pow YK cour KXXXXNYK oou-= KXXKKKN Oo KXXXXKAKK a vee WAS] = | jie | =| pa bisa WME on Ye "Eee eh a thes —tus| ami to [oes] poten ol foes pete foe — ta _ ovoewen Y- Z7 | KN UL UL tons] |town toez toez io I TT) a, niger Vor — 1Z. } High-Z. P Z Wo (coupuy Vg --n---} HOR.) Crp -fftiaee. fork None ff Bite 100 ua | toe toe bw to pas - - on : tea lt, trea | von trot osr ame) Ye= KN VE Beet XXXXXM aes” KXXXXKOK neat” KEXXKKXKK Remarks 1. When DSF is high level : Block write cycle When DSF is low level : Write cycle 2. WPB: Write-per-bit 3. When biock write cycle is selected, input the column selection data to DATA IN. 4. Because the serial access port operates independently of the random access port, there is no need to control the SC, SE, SIO pins in this cycle.

166 MB 6427525 0063857 bub Me

NEC uPD482234, 482235 Hyper Page Mode Read Modify Write Cycle (Extended data output: 1PD482235)/ Hyper Page Mode Read Modify Block Write Cycle (Extended data output: .PD482235) wwe ve + berwe tHPRW tan taco, a rey oe tc ——) -— a TAS (row) Ye +h" Hf me, [oe] se} I] 22s se [ie ana i Le j,i pr} reseas oan ¥e7 YD oie) AXXXKX) or, XXX) Cou XXXXXXKKK rae fe IE a fo ' v | ed ie | | Pree be [|e bg ber move FY ilk ill AAC MU Mate tons] | tora | | oT" ltoce {ot | toez Il | — wo ftoupuy YOrT nae tine I Pals diem ey ll one. i et ET te Wii, | ton 5 tow ‘6 FS k KI h ters] |trAM, tres) | tron tres) | tron, ‘Tecs) | tron Vin he Book osF copay Y= faces CXXXXXN Seer KXXXXXN Sea KXXXXKKKK Remarks 1. When DSF is high level : Block write cycle ‘When DSF is low level : Write cycle 2. WPB : Write-per-bit 3. When block write cycle is selected, input the column selection data to DATA IN. 4. Because the serial access port operates independently of the random access port, thereis no need to control the SC, SE, SIO pins in this cycle. 167 M™@ 6427525 0063856 582 a

NEC yPD482234, 482235 (Refresh cycle) wPD482234-60 | yPD482234-70 Parameter Conditions [wn [wax wn. | wax | [Retech pared ———s~dt sr | | 8 | | 8 [me] [RAS high to CAS ow precharge ime] wwe [10 | | 70 | [|_| CAS setup time Bercmecn |= |= f Tt Tl | (tor CAS before RAS refresh cycle) [SC seuptimetom AAS | te [10 | | 1 | | ve [Nowe nad [SCrhald time tom RAS | ww [10 | | 10 | | ve [Wows | Notes 1. The tsrs and ts in the hidden refresh cycle, CAS before RAS refresh cycle (STOP register set cycle and optional reset cycle) are specified to guarantee the serial port operations until the transfer cycle is executed after the STOP register value is changed, When the STOP register value is not to be changed, or when the binary boundary jump function is not used (when the TAP register is empty), tsrs and tsa will not be specified. 2, tssc(split read data transfer cycle) and ters (split write data transfer cycle) are specified at the rising edge of SC which reads/writes the address of the jump source in the binary boundary jump function. tsoxe (split read data transfer cycle and split write data transfer cycle) is specified at the rising edge of SC which reads/writes the address of the jump destination in the binary boundary jump function. The rising edge of these SCs cannot be input in periods (1) and (2). (1) Split read data transfer cycle: Period from the rising edge of the SC specifying tssc to that of the SC specifying tsonn (Refer to Note 2 at the Split Read/Write Data Transter Cycle Timing Chart.) (2) Split write data transfer cycle: Period from the rising edge of the SC specifying tsrs to that of the SC specifying tsoun (Refer to Note 2 at the Split Read/Write Data Transfer Cycle Timing Chart.) 3. Restrictions to the split read data transfer cycle during serial write operation (1) If split read data transfer is attempted for an address which is already involved in serial write, normal operation is not guaranteed, except for a period in which no serial write has been performed, that is from when SE goes low at the rising edge of SC to just before the serial write begins. (2) If split read data transfer is attempted when an address invoived in serial write is the boundary address specified by the STOP register, normal operation is not guaranteed, except for a period in which no serial write has been performed, that is from just after the mask write or mask split write transfer cycle is executed to just before the serial write is started by setting SE to a low level at the rising edge of SC. 168 M@™ 6427525 0063459 419 a

NEC uPD482234, 482235 RAS Only Refresh Cycle ras wow > a a GAS (Input) Vor~ | V/ rasvoas Y= KYRK now KRXKORRKKKKKK KKK KKK Sie BTOE crown Y- 7} | ANNNNAANAAAAAAAAAANANAANNNNNANNN Wee Oupst) VO" wenneeeencedyeeeeeeecce enna tHE. ee eee een eeeee eee cceeeereeee eee ose ime f'- AN TTT. Remarks 1. WB/WE : Don't care 2. Because the serial access port operates independently of the random access port, there is no need to control the SC, SE, SIO pins in this cycle. M™® 6427525 0063860 130 a 69

__ NEC 482234, 482235 TAS Before RAS Refresh Cycle (Optional Reset) te __ A | tw WOW oupuy Yor ee ceeeeeeeeeceeceeeee ters tern vero sont tsps tsan SC (Input) YM } \\ } \\ Remarks 1. Address, WB/WE, OT/OE : Don't care 2. Because the serial access port operates independently of the random access port, there is no need to control the SE, SIO pins in this cycle.

170 M@™@ 6427525 OOb38b) O77

NEC uPD482234, 482235 CAS Before RAS Refresh Cycle (STOP Register Set) ae — L tare a a resressimou) Ve KXXXXXAK sounoany cove XXKXXXKKKKXAKMXAKMXKKRNK wamewen Ye TON WITTE. pad oe <a as ves _||_ om seamen YLT F | ANNNAAAAAAAAANAANAAAA tens srw SC (Input) Y= / \\ | \\ Remarks 1. DT/OE: Don't care 2. Because the serial access port operates independently of the random access port, there is no need to control the SE, SIO pins in this cycle. ME 6427525 0063862 TO3 me ™

NEC uPD482234, 482235 TAS Before RAS Refresh ‘Cycle (No Reset) TAS input) Yee— —_ ware won Y2 Z7777ZZF | AWK osr wes *t- ZZ) ANNNAANNANUNARUAUNAAANI mel t Aone, HOE : conn operates independently of the random access port, there is no need to control the SC, SE, SIO pins in this cycle.

172 MH 6427525 0063863 TUT

NEC uPD482234, 482235 Hidden Refresh Cycle (uPD482234) tre tre toe Je | — = he pana Una cr address (rout) Y"~ XY i eel i POR Ol Tet Te Lf wane moun Y- 7777 TP , A . aa ear Pr SHOE tron \\e- Z77 ) Ws | | La [| tere HighZ = 5 High-Z tess || em tes | Vin VVYVVVV¥ WVVVVVVVVVVVVVYVVV OSF (Input) y, — NY YP XXXXXXN, Resetselect_ KXXXKXXKXKKXKAXNAK tsrs | ts SC (Input) Yet . Remarks 1. When DSF is high level : Reset select = No Reset When DSF is low level : Reset select = Optional Reset 2. Because the serial access port operates independently of the random access port, there is no need to contro! the SE, SIO pins in this cycle. ME 6427525 O0b38b4 3ab 79

NEC pPD482234, 482235 Hidden Retresh Cycle (Extended data output: 1PD482235) te tne PAS emo) Ym oa. wf em [ee tao see |_| aetsoss moun) ye KXY ROW KX co. KXXXXXXXXXXXXMMAMAKAKAKAKA Pinna Vee i P| wean wou Y= 77/77/77 \\ AAA os | Ee] | ee aS YT mrtonn t= 777 NY Cle Pe _ LT yw 7 [tae | 2 [toes | ma Highz an = lL. | Vin = VWYYVVY — LIVVVVVYVYYVWVWVWVWVVVV OSF (input) yy. — \\ PREXXKX Reset setect_“KXXXKKXXKXXKKXXKX $C (nput) Yt Remarks 1. When DSF is high level : Reset select = No Reset When DSF is low level: Reset select = Optional Reset 2. Because the serial access port operates independently of the random access port, there is noneed to control the SE, SIO pins in this cycle. 174 M@™ 6427525 0063865 712

NEC uPD482234, 482235 {Register set cycle) #PD482234-60 | —uPD482234-70 Parameter Symbol | _#PD482235-60 HPD482235-70 | Unit | Condition [ win. max. [min Tax. | RAS high to CAS low precharge time] twe [10 [ [to [as [| Write command setup time ee Note twcs 2 twcs (MIN.) is the condition for early write cycle to be set. Dour becomes high impedance during the cycle. ‘trwo 2 trwo (MIN.), towo 2 towo (MIN.), tawo 2 tawo (MIN.), are conditions for read modify write cycle to be set. The data of the selected address is output to Dour. If any of the above conditions are not met, pin W/IO will become undefined. 175 M™ 6427525 0063866 655

NEC yPD482234, 482235 Register Set Cycle (Early Write) tre ao a vu- YYVY 1 i VVVVVVVVVVVVYVVYYYVYYVYYYYYY YY VY YY YY cress (mou) ye XXX) Xrownesh KX AX twas, eee Eee wae wows Y= 777 ar ston D) por | OTE tron Y= 777 i tow =p — wow mma i> XXXXXXXXXM vara XXXKXXXKXXXKXXXKX le, pln osF anew Y= 77 ZX Fesistr sect KX XK XXXKXXXKXXKXXX Notes 1. tcas for the uPD482234 tioas for the xPD482235 2. Refresh address (RAS only refresh) Remarks 1. When DSF is high level : Register select = Color Register Select When DSF is low level : Register select = Write Mask Register Select 2. Because the serial access port operates independently of the random access port, there is no need to control the SC, SE, SIO pins in this cycle. 176 @™ 6427525 00b38b7 595

NEC uPD482234, 482235 Register Set Cycle (Late Write) tre a | — —siee | [_teas, teas Hee | 3S trou V*~ | I Va- YYV = [_ ee Access cinout) ye XXX) frowmens} KAXKAX MAA XAMAXA ARERR eon wane wow Ve 77 Ma — VITAL tons town _ Vee nama nama ore mew VIZ ZZ) |. ANANANAANNAANANNANY tH ton BBR ww %2= SXKREXRRRKRRNC enon YERKNEKKERKK ose nou Y= 777 (We Peso some KXXXXXKXKKARXKKRKKKNK Notes 1. tcas for the uPD482234 twcas for the yPD482235, 2. Refresh address (RAS only refresh) Remarks 1. When DSF is high level : Register select = Color Register Select When DSF is low level : Register select = Write Mask Register Select 2. Because the serial access port operates independently of the random access port, thereis no need to control the SC, SE, SIO pins in this cycle. M@ 6427525 0063868 42]

— NEC P482234, 482235 (Data transfer cycle) [Serial ciockcycietime | tesco [te fT a2 Ts | sere! ouput soos inoom S| wm || we | | 7 tre] | seen err from SC to QSF a from RAS to QSF fmtecor™ T= | Le | Te let from CAS to QSF eae = ft T=t tt from DT/OE to QSF a from RAS high to QSF [Serial input enable time from RAS | tom | 20 | | 20 [ [ns | | [sc prechargetime | we Ts | ts [fs | | |scpuce wih Tee Ps Ts ffm [DT high pulse width | toe [a0 fT 20 Ts | [OT iow sewptine | ims | oo | To Ps [Serial output hold time after SC high toon [3 [| os | [ns | | |Seriaidatainsetuptime [tes [0 [fo Ts | [Seriatdatainhoidtime | tw [10 | To [fs | [Sc setup tne rom RAS | we | 10 [| 10 | | ro |Wowe n 2.9 [DT low hold time after RAS low | tam [658 | | 65 | [ns [Notes | [OT iow hold time after RAS iow | trove [vo | [26 [| | ne [notes | [OT low hold time after CASiow | tom | 15 [| 20 | [ne [Notes | [OT iow hoidtime after address | too | 20 | [26 [| ns [Notes | [SC ow raltine ater OT hon [tm [<0 | | «0 | | no [Nowa | [SC low hoidtine ater OT igh [too [40 [ [4s [| ne [Notes 2,4 | |scrightoGaSiow | tese_| 10 | | to || ns [Notes 28,4] JSC high to DT high | tooo fo [To || ns [Notes | [DT hgh to RAS nigh doy ime | tom | 0 [| 0 | | rw [Nowa | [Serial input aisabie tine tromso | tz | 0 | [ o | [ns [| [Serial output disable time rom RAS] tore | 0 fT oT nsf

178 MH 6427525 0063869 368 mm

NEC uPD482234, 482235 Notes 1. The tsas and tsrx in the hidden refresh cycle, CAS before RAS refresh cycle (STOP register set cycle and optional reset cycle) are specified to guarantee the serial port operations until the transfer cycle is executed after the STOP register value is changed. When the STOP register value is not to be changed, or when the binary boundary jump function is not used (when the TAP register is empty), tsrs and tsri will not be specified. 2. tssc (split read data transfer cycle) and tsas (split write data transfer cycle) are specified at the rising edge of SC which reads/writes the address of the jump source in the binary boundary jump function. {sour (split read data transfer cycle and split write data transfer cycle) is specified at the rising edge of SC which reads/writes the address of the jump destination in the binary boundary jump function. The rising edge of these SCs cannot be input in periods (1) and (2). (1) Split read data transfer cycle: Period from the rising edge of the SC specifying tssc to that of the SC specifying tsonr (Refer to Note 2 at the Split Read/Write Data Transfer Cycie Timing Chart.) (2) Split write data transfer cycle: Period from the rising edge of the SC specifying teas to that of the SC specifying tsoua (Refer to Note 2 at the Split Read/Write Data Transfer Cycle Timing Chart.) 3. Restrictions to the split read data transfer cycle during serial write operation (1) If split read data transfer is attempted for an address which is already involved in serial write, normal operation is not guaranteed, except for a period in which no serial write has been Performed, that is from when SE goes low at the rising edge of SC to just before the serial write begins. (2) If split read data transfer is attempted when an address involved in serial write is the boundary address specified by the STOP register, normal operation is not guaranteed, except for a period in which no serial write has been performed, that is from just after the mask write or mask split write transfer cycle is executed to just before the serial write is started by setting SE to a low level at the rising edge of SC. 4. One of the following specifications will be valid depending on the type of read data transfer method used, (1) DT/OE edge control: Satisfy the following specifications. + For DT/OE edge inputs : taps, tcox, tao, torr + For SC inputs : ts00, tsoH (2) Self control: Satisfy the following specification. + For DT/OE edge inputs : troxs + For SC inputs : tesc, tsonn 179 MH 6427525 0063870 O8T

NEC 482234, 482235 Read Data Transfer Cycle (SC Active) a =| ee | Address (Input) XXX A {com MAMAMAAAMALKA i wane wou Y= [77 Sa . ee sistem Ye TN _| ——_ ANNNAANI os neu Ye ANN VTTTTTTILLTLTTMLLTTTLLLT LLL LLL SE tnpuy YR | 0010807 up Yo ne etn) = LL et “ SF (Outpuy YT X Note tcas for the #PD482234 tueas for the wPD482235

180 M™ 6427525 006387] Tle

NEC uPD482234, 482235 Read Data Transfer Cycle (SC Inactive) a | sne| —— ee ton raseesonoa) Y= KRY row] of See : 2 a WE tne Y= 777 [le - a | sroewe = WY || ee os ona Yi \\\\N, MMU | tp so0scr oun Yor" mt \\¢ i a (¢ <) Note tcas for the uPD482234 tucas for the uPD482235 M™ £u27525 0063872 952 i nl

NEC pPD482234, 482235 Read Data Transfer Cycle (Serial Write + Serial Read Switching) SS RS tro) Ye a | Le SCS—~S | a | = sam os) Yo YO) =O ION Fe e777 aI NNNNNNAAANNNANANNAAANNARANANUNT _ | ee! | seen we Y | ANNANNNANANARUNNANY oor coun Yo x el ee SS [[ tm (350 = a5 Fr High-Z cous Ya~ nn--&oara KRERRR KR RRKRRRI foo lh z| - (Output) VOW weeannneeee eewneennnn nnn ne ME ee weeeeeeedm Note tcas for the ¢PD482234 tuoas for the zPD482235

182 MM 6427525 0063873 899 a

_ NEC uPD482234, 482235 Split Read Data Transfer Cycle * ———) a tone | | tess tasa| sp=, te save vo) Yt aa «R00 KARRI ‘twas: sf | | wae wows Y2= 77) LS orceomn Ye TY | a oe = * mfp ee tres. tran Sane // MA NNNNNNNNNNANNNNNAANANUUUNNAAAANNNI = - tscc Note 2 sooo eo A F twin Vex CoaTaiw KNX owraw KNX oaraw KR owTaw KRY ovraw KY) sion ee i | | . miter En cco cuca CEN ones ® Notes 1. tcas for the uPD482234 ‘tueas for the uPD482235 2. Do not perform the following two serial read/write during this period. + Serial read/write of jump source address set to the STOP. register of the data register which does not perform the data transfer cycle. + Serial read/write of last address of data register (Address 255 or 51 1) MM 6427525 0063874 725 a 163

NEC uPD482234, 482235 Write Data Transfer Cycle sexe | {rer f= ale nanos ~ TERR P00) OOO to > 7 —— BTR eos Yo a Wor WT! anput) V8 KXXKK se KXXKKXXKRXXXARRARAARARRARAAAAK barn Ye ——— soo Ye [| = - ; ale 5° to Ye = IID Conan) Note toas for the uPD482234 thoas for the uPD482235 te4 M™ 6427525 0063875 bb) a

NEC PD482234, 482235 SPD 482234, 482235 Write Data Transfer Cycle (Serial Read — Serial Write Switching) aS row Yn , = | ——— en FS tap) Ve~ aa she al ces apt) Y~ saat Aloe ies emenaaee WATE trou) Y= Se ee BTIOE tnpuy Y= wh LITTLE tws: a Boeiby mou) Yr Se a DSF (nowt) Y= so ee aa, te -— a soon ef ratnomremanee I ee sior a tro Note tcas for the uPD482234 thas for the ¢PD482235 MH 6427525 0063876 STS 185

NEC uPD482234, 482235 Split Write Data Transfer Cycle FAS tro > yj) Aacress (rout) V7 = WNTE (nou) Y= ow ee BTIOE (mow) Ye — a te Woror meu Y= XXX wale AOXXXXXXXXXKXXAXAXAXAXAAAA AAA -_ i osF crow) i= TP ANANNAANANARANANNRANNUR NN SE (mpuy Ve~ ir sc (input) Ye f{. —f —f —f F| woe Ye Hs Pig Sia Sigh = | ey eye 0 (eo is [se i foo an samo kR Xora KRY a oor KRM oa oor KRYO OWT KR) SF (Output ee

186 MH 6427525 0063877 434 me

NEC uPD482234, 482235 _ Notes 1. tcas for the uPD482234 thoas for the ¢PD482235 2. Do not perform the following two serial read/write during this period. * Serial read/write of jump source address set to the STOP register of the data register which does not perform the data transfer cycle. + Serial read/write of last address of data register (Address 255 or 611) 187 MB 6427525 0063878 370

NEC pps 2094, 482285 (Serial read, write cycle) Parameter uPD482235-60 | _4PD482235-70 Condition te foe a lSerarcickoycetme | we [ve | | 2 | [w=] _| Serer ouput access ime rom SE [ww || | | 7 [mf | Serr ouput access tne rom So-| won| [16 || 7 fms | a from SC to QSF [sc prechargetime | tx | 58 ff 6 Pfs [SE prechargetime | tse | os [Ts fs | [sc puisewiath tse Ps fs Ts TT [SE puicewisth | twee Ps Ts Ts TT |SEsetuptime | toes | oo To Ts fT [SE tide fon 66 | we [| |p | [Serial data in eetuptime | toe [| 0 [fo [fs | | [serar dia noidine [tw | vo | | 0 | [| [srt cupu had tne ater SoHo wow [9 | [5 [|| [ouput able ine tom S€wgh [tex [0 |e | 0] we | me | now J aid ll time Note tsez, tocz, twez, torr, tora, and torc define the time when the output achieves the condition of high impedance and is not referenced to Vow or Vou. 188 M™ 6427525 0063879 co?

NEC uPD482234, 482235 Serial Read Cycle ter teee se Mi SE (input) yi te [__ tsa ‘eo tsa. tec fee, | \\ — -_ ;— SC (Input) Yi i f | ce S100 Von = High-Z THE, V7 V7 rv

97 Oe vow TT CLE ontaour__ FX 9 pxaanb>--

Vou~ QSF (Output) Ye Notes 1. Last address of data register (Address 255 or 511) 2. Starting address of data register newly read (address is ‘specified in the data transfer cycle). Remark Because the random access port operates independently of the serial access port, there is no need to control the FAS, CAS, Address, WE/WE, DT/OE, WI/O, DSF pins in this cycle. Serial Write Cycle tsoo tscc met teoc Nom 2 soo Ye a OA tses| | tse tees | |tsen tees) j tees tees] | teen jana sla si00 Vor- 7\\¥ VVVVVYVYVYVVYVVYYVV VY YVVVVY VY 337K Va OROATANKXXXXXXXXXXAAKKKOM ows KKOKKXKAN ora KKK to QSF (Output) Yor~ y put) YorT x Notes 1. Last address of data register (Address 255 or 511) 2. Starting address of data register newly read (address is specified in the data transfer cycle). Remark Because the random access port operates independently of the serial access port, there is no need to control the RAS, CAS, Address, WB/WE, DT/OE, WI/O, DSF pins in this cycle. 189 M@™ 6427525 0063880 Teo

NEC yPD482234, 482235 5. Package Drawings

40 PIN PLASTIC SOJ (400 mil)

B Ftetetatatetatetetatatatatatetatatatata L -——} F E a aE aE a | > ol 4 Seca —)) T si an |, _| M OT ee line is located within 0.12 mm (0.008 inch) of 1TEM_MALIMETERS INCHES _ itsttue postion (TP) at maximum material eondtion. 8 2020282 103679008 © To1e ——aa G11 16502 oaetaO GOs E10820.15 0.04349908 ay G 3,520.2 0.13820.008 24802” oco4? 9008 7 O8MIN. 0.037 MIN. a CN TTR) — 8 gROT M 0.400.100.0768. 888 a aS a F—3a0n0 700 57050 08 Taos 0.006 aR rin a00n

190 MH 6427525 0063881 965 Ml

NEC uPD482234, 482235 7

44 PIN PLASTIC TSOP(II) (400 mil)

D + “ wb a 1 2 A H J t a [_N | 8 L 08M @) NOTE STEM MILLIMETERS INCHES D 032908 oo1340.003 E 0.120.05, 0.00420.002 F712 MAX 0.048 MAX. Te 57 0038 TO ™ e202 0.46320 008 T™10 1620.1 0.40020.000- J 08202 _0.03179.208 K _0.145¢2025 0.00620.001 LC 05201 0.02028 08 a A TN 000.004 Pp artle athe ‘$44G5-80-7JF4 191 M@@ 6427525 0063882 &Tl

NEC uP 482234, 482235 [MEMO] PAGE(S) INTENTIONALLY BLANK

1 Mi 6427525 0063483 738

NEC uPD482234, 482235 6. Recommended Soldering Conditions Please consult with our sales offices for soldering conditions of the #PD482234, uPD482235. Types of Surface Mount Device HPD482234LEx ——: 40-pin plastic SOU (400 mil) HPD482235LE-xx —: 40-pin plastic SOJ (400 mil) HPD482234G5 x ——_:_44-pin plastic TSOP (II) (400 mil) HPD482235G5-xx ——: 44-pin plastic TSOP (Il) (400 mil) 7. Example of Stamping Letter B in the fifth character position in a lot number signifies version B, letter A, version A, letter F, version F, and letter E, version E. NEC sara (0482235 XX XXEUXx xX Lot number 193 WM 6427525 0063884 b74