D4168

UPD4168 NEC | Alldatasheet

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8,192 x 8-BIT NEC Electronics Inc. NMOS XRAM Revision 1 Description Pin Configuration The NEC pPD4168 is an 8,192 word by & bit NMOS XRAM designed to operate from a single +5V power supply. weRC 0D) Yee The NEC pPD4168 is termed an XRAM because It incor- ar "rp “= porates some of the best features of both SRAMs (Non- ads 2b a, multiplexed addresses, simple interface requirements) ads ub a and DRAMs (the one-transistor core ceil provides high ads 2D a,, density at low cost). The negative voltage substrate bias aad? £ wzbe is internally generated and provides automatic and ee ie g " a i 4,ae¢ s transparent operation. t,o eb 10, The incorporation of an internal refresh address counter wo, G0 PD 10, and refresh multiplexer allows the user to select one of 0, GV 7p W9, three refresh modes. The self-refresh mode provides ona 1" “rE ee transparent refresh without system overhead. Intemal > latches for address, data, and chip select allow for use — in systems incorporating multiplexed address/data buses. Pin identification No. Symbol Function Features i FSH ineernal retresh 0 8,192 words by 8-bit organization 2-10, 21, AerAyp Address inputs CO Single +5V+10% power supply 23-25 C] On-chip substrate bias generator 11-13, 5-19 1/Qy-1/07 Detain out C] Fast access times -— C Low power dissipation: {ee 28mW max-Standby 20 Chip enable 19 MW max-Seif refresh 22 OE Output enable . © TTL-compatible 26 cs Chip select C) 28-pin SRAM/ROM/EPROM compatible package 7. WE Witeenae © Built-in refresh multiplexer and refresh address Cee EET anr nT nETUEE SennnnnnnnnnnnEEE counter 2 Nog SV power supp) (1 Power-down self-refresh mode © Automatic precharge allows cycle time to be inde- Pin Functions pendent of system skews RESH resh

1 Latched address, CS, and OE functions allow use RFSH (Ref input)

on multiplexed address/data bus A built-in refresh control circuit enables this input. Two 1) Read, early write, late write, external refresh, pulse refresh modes are available: pulse refresh, using the refresh, and self-refresh cycles RFSH input as a clock input, and power-down self- refresh, using the RFSH input as logic level input. RFSH Performance Ranges is high (inactive) during normal read and write cycles. Device tona ‘ona te lees Paveae-12 120ns 45ns—-220ns—~—«S MA Ag-A12 (Address Inputs) pPD4168C-15 1S0 ns 55 ns 260 nes 60 mA The uPD4168 requires 13 address inputs to select a word Sr. rwrolnee~C—*‘é‘é Os data. eects: theese aires inputs are internally. weoai6ac-20200ns Ons 330ns_ Sm stead onto the chip at the falling edge of a CE clock pulse, the CE clock determines their address setup and hold times. Inputs Ap-Ag perform external refresh. 6-1

1/O9-1/07 (Data Inputs / Outputs) CS (Chip Select) Common 1/0 pins require WE and OE to control data. © When CSis high (active) while the CE clock is enabled, The CEclock and WE determine the data setup and hold the u.PD4168 can perform read/write operations. If CS is times (tosc, toxic, tosw. toHw) for these pins during a —_—latched low (inactive) while the CE clock is enabled, memory write cycle; OE determines the access time 1/O9-1/O7 remain in the high-impedance state, regard- (toga) during a read cycle. less of the status of WE and OE. GND (Ground) WE (write Enable) All voltages are referenced to GND. WE controls read/write operations. WE input timing de- termines whether a write cycle is an early write or alate CE (Chip Enable) write. The chip enable clock initiates read/write cycles and Power external refresh cycles. It allows addresses, CS, and Vec ( Supply) (during an early write cycle) data inputs to be internally +5V power supply. read onto the chip. OE (Output Enable) OE controis the output timing for MQg-1/07. Access time (tcEA, toga) is determined by the CE clock or by the OE input, according to OE input timing. uPD4168 Functional Modes Mode RFSH cE cs WE oe uo Comments Read cycle H C’ H # L Qata out OE. low logic bevel or clock pulse Early write 4 c’ H L kK Data in Late Write H C’ H H Data in External retresh H C’ H H H High-Z H Cc’ L K x High-Z Standby Pulse retresh c' H x K x High-Z c' ¢’ H H H Htigh-2 After external refresh cycle Cc Cc’ M4 H L {Note 1) After read cycle c’ c’ “ L rr Data in Atter early write cycle c’ c’ 4 c H Data in After late write cycle Power down self-retresh L H x x x High-Z Standby 4 H x x x High-Z Ho Vg, Ley. C’ = negative edge of dock pulse, X= Vigg OF Vy Note: {})} Depends on previous cycie 6-2

| | “ = “, Pt a _ “ a ee | Seen ja Aer : i An “ ee ——— , rr ON? Absolute Maximum Ratings DC Characteristics Voltage on any pin relative to GND 1,010 +7.0V Ta =O 10 +70°C Vog =5V 20% Operating temperature, Torr, Oto +70°C a ae Test Storage temperature, Tsrg “SS aisc |= Purameter Symbol Min’ Typ Mex Unit’ Conditions Short circuit output current, Ips Soma © SUBPIYoliage Voc 45 5.05.5 Referenced tp GND Power dissipation, Py IW ee. ViL -10 0.8 V_ Relerenced to GND Comment: Exposing the device to stresses above those listed in Abso- lute Maximum Ratings could cause permanent damage. The device Is ro ee. Vin 2.4 5.5 V__ Relerenced toGND not meant to be operated under conditions outside the limits de OM : scribed in the operational sections of the specification. Exposure to Output voltage, Voge LU 0.4 Vi lope 2ma absolute maximum rating conditions for extended periods may affect low device reliability. ——— 6-3

DC Characteristics (cont) Capacitance or Ta = Oto +70°C, Vog =5.0V 20% Parameter Symbol Min. ‘Typ Max Unt Conditions ae Tost Oapavollage, Von 24. Voc Odgu=-imA Parameter Symbol Min Typ Max Unit Conditions high Input C; 10 pF f= 1 MHz wwerage Voc een 65 mA igw220ns ee eupeny carrer, $0 mA tem 260ns Data I/ 140 D = 1 MHz Standby current icc? +) mA EDVin am. > Viq min Sett-retresh locs 3.58 mA RFSH< Vic max average current inputieakage ly; = - 0 10 A Vin 0 105.5V; current ohers=0V Output leakage ing, -2 10 yA Voy7=05.5V; current Dour = High-Z AC Characteristics Ta @O0t0 +70°C, Voc = SV 210% ee h04108-12 PD4168-15 uPD4168-20 Test Parameter Symbol Min Max Min Max Min Max Unit Conditions Average Vos supply current, active lect 65 60 55 mA to=le (min) Read, write, or refresh cycle time & 220 260 3H ns Access time from CE EA 120 1% 200 as (Note 5) Oata off time from CE tcez Ki] % 45 ns (Note 6) Aocass time trom OE tea 45 55 70 ns (Note 5) Data off time trom TE toez 0 35 45 ns {Note 6} CE pulse width tos 120 10000 160 10000 200 000 as CE precharge time tp 90 100 120 ns Address setup time to TE tasc 0 0 0 ns Address hold time from CE Cane 35 45 55 ns CS setup tine to CE se 0 ) 0 ns CS hold time from CE tHe k) 45 55 ns Data setup time to CE, early write tose -” ~10 -” ns Data hold time from TE, early write tHe 90 100 120 ns Data setup time to WE. late write tosw 0 0 0 ns Data hold time trom WE. ite write toww 50 60 70 as WE hole time from CE, early write twac 90 100 125 ns itpkeanon to oo v0 4.8} © €E hola time from WE, tate write tonw % 05 135 ns Wowimutledge ‘ws 0 0 4O| 8. WE hold time trom TE, read cycle tacx 0 0 0 ns Gnvintmthedge to +5 » 4©© «s . BE setup time to CE, write cycle loes 0 0 0 ns Gndintontwingu tex 0 0 +O | 6-4

N:; E C uPD4168 ee eee eee AC Characteristics (cont) Ta 2=0to 470°C, Voc #6 V 4 10% SSS tints SSS PD4168-12 yPD4168-15 wPD4168-20 Test Parameter Symbol Min Max Win Max Min Wax Unit Conditions CE delay to AFSH, pulse seiresh torp 50 65 # ng RFSA pulse width, pulse retresh tape 50 4000 65 4000 80 4000 ns RFSH recovery tims, uise refresh tapa 90 100 120 ns RFSH pulse width, seit retresh tans 40 49 40 ys {Note 8) AFSH recovery time, sell retresh tase 2 2 2 ps TE hotd time trem AFSH, self retresh = tesw 40 40 40 ys CE setup time to RFSH, setfretresh tog k) 40 50 as Fansition time, rise anc ait tr 3 50 3 50 3 50 aS (Note 4) Refresh period trey 2 2 2 ms RSH precharge time tap 90 100 120 ns OE lead time to retresh cycle tos. 170 20 260 ns WE lead time to retresh cycle twee 170 210 260 ns RFSH setup time to CE tac 280 320 410 ns Note: (1) All voltages referenced to GND (0 ¥). (2) An initial pause of 2ms is required atter power wp, followed by any 8 CE cycies and 64 RFSH cycles before proper device operation Is achieved. Read, write, and external refresh cycles may be used as CE dummy cycles for initialization. The 64 refresh dummy cycles can be performed before or after the 8 CE dummy cycles. Both dummy cycles must be within AC parameters. See figure 1, below. () AC measurements assure ty = Sn. (4) Vy min) and Vp, (max) are reference levels for measuring input signal timing. Transition times are measured between Vi ONE Vi. (5) Load = 2 TTL loads and S0pF. (6) togz (max) and togz (max) define the time at which the output achieves the open circult condition and are not referenced to Vox OF VOL: 6 {7} tyes twee (in), the cycle Is a late write cycle, #8) A power down selt-refresh cycle is initiated when the AFSH input Is active low tor a period of 40;6. The refresh interval is about 15.6ys. Figure1. Power-up Dummy Cycles am Veo 4sV | 64 cycles = / Iu # cycles a a | Na|y Sores 6-5

Read Cycle Early Write Cycle i Tee Wir } tape wei or ——$—— he a mm bg ee ee = | Address SOOOX || COCO SOOOCOOOL NN SOOO OOOO A C8 OO hace | RIAA AANA cs OO XXXXNXXXAXKXKARXRXKEARAKAS bw we wi e: y toe ve loez rer J vo U Gote-out Vaid) rr) Hoos. mocuz264 Late Write Cycle External Refresh Cycle wn Te L ec --- wn - ey asenwn SEK — Tl KRRRRRER EERE IERIE aseenn ZRRK | As - Ad KERERERERRERREKERRERERRERES seibees tose oot temo cs KY MAK AKAAK KAKA KAR RAAA RRA AAA cs OO | IKICOOCOOOODIIOUO OO ee we oes 1 we || FoF art | ot ss | ae ‘ow te #0 | Ostain Vaid id ane27a 80-0072: Pulse Refresh Cycle after Read Cycle Complete Pulse Refresh Cycle after Early Write Cycle Complete Retresh Cyc we tute Refresh Cycle Read Cycle & — po— ty - AFR NS; hai Re COS ANNNNNNY SO - mame Egg —— oP — an Se oN (TT LT) Addeess OOF |] JODOOOO OO OOOO OOOOOOX Agmess OOF) JODOOOOOOOO OOOO OOOOOX nsepele—eons | PP xep—iocg cs Y || CRRA oes cs YY SOV OOOO tec ee hoses we « V -_ | ee co 7 lees cE i ; - - 1 0)-0022234 Data aid HOO 6-6

Timing Waveforms (cont) Pulse Refresh Cycle after External Pulse Refresh Cycle after Late Write Cycie Complete Refresh Cycle Complete Late External Pues Pulse t Verne Cycie = ~—Retresh Cycle Retresh Cyc ar ane ane q o— bare —> we a fe] m Se sl ae : f ce 4 7 “ +4 ene gee . . > a ¥ FOF AAT VY aces % oe OOS Aaorese 4 i “a mM <'c'n"a's"s's"e'sha"s'a'n's CEOTEES co tng REAR OX KKK cs X eee Scenes DOO? lool locos —_ ‘ —- we we lo : a — ve tome _ foww } _— vo roe ‘Dale Vard #0007304 SORTA Power-down Self Refresh rH ‘aos ease % a -O22DA 6-7