D41464

UPD41464C-10 NEC | Alldatasheet

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Technical content

65,536 x 4-Bit NEC Electronics Inc. Dynamic NMOS RAM Description Pin Configurations The 1PD41464 is a 65,536-word by 4-bit dynamic RAM —_4g-Pin Plastic DIP designed to operate from a single + 5-volt power sup- ply and fabricated with a double polylayer, N-channel ad ah ono silicon-gate process for high density, high perfor- vo, G2 175 v4 mance, and high reliability. A single-transistor storage vo. U3 46) cas cell and advanced dynamic circuitry ensure minimum Wes § 151 v3 power dissipation, while an on-chip feature internally RSS = 14D A generates the negative voltage substrate bias—au- Ase g 13 Ay tomatically and transparently. As q7 12D Ag =< Aas The three-state /O is controlled by GAS independent of wee wpa RAS. After a valid read or hidden refresh cycle, data is held by holding CAS low. Data input and_output is returned to high impedance by returning CAS high. . Hidden refreshing allows CAS to be held low to main. _18-Pin Plastic Leaded Chip Carrier (PLCC) tain output data while RAS is used to execute RAS-only 3b refresh cycles. owes Refreshing may be accomplished by means of a CAS before RAS cycle that internally generates the refresh ee address, by means of RAS-only refresh cycles, or by v2 3 16 [0 CAS normal read or write cycles on the 256 address combi- wedse % Dw, nations of Ap through A7 during a 4-ms refresh period. MSs x5 4D A Features As d7 12D Ag © 65,536-word by 4-bit organization © Single + 5-volt +10% power supply Bgre S_ CAS before RAS internal refreshing > aonesiim © Multiplexed address inputs © On-chip substrate bias generator © Low power dissipation — 28 mA max (standby) —440 mW (active, tac = tac min) © Nonlatched, TTL-compatible inputs and outputs © Low input capacitance © 256 refresh cycles every 4ms © Standard 18-pin plastic DIP and PLCC packaging

Ordering information

PartNumber Row Access Time (max) Package uPD41464C-80 80 ns 18-pin plastic DIP C10 100 ne cre 120 ns PD41464L-20 80 ns 18-pin PLCC to 100 ns Lia 120 ns exore 3B-1

Pin Identification Absolute Maximum Ratings Name Funetion ‘Veltage on any pin relative to GND =O te +70V eA ‘Address inputs Operating temperature, Topa Ot +700 70, -O, Data inputs and outputs Storage temperature, Tera 55 to +125°C oS Column address strobe Short-cireult output current, los SO mA rod Output enable Power dissipation, Pp 1.0W FS Row address strobe Exposure to Absolute Maximum Ratings for extended periods may We Write enable affect device reliability; exceeding the ratings could cause permanent BD Gear damage. The device should bo operated within the limits epected GND Ground nddor DG and AC Characteristics, Veo -+5-volt power supply No No connection Recommended Operating Conditions capaci Parameter Symbol Min Typ Max Unit apacitance Iputvoltega high VAC ‘ apact ANCE te Input voltage, high Vig 24 Veo+! Vv Parameter Symbol Max Unit Pine Under Test ‘(MPutwoltage,ow V1 input capacitance Gr SPF Agthrough Ay Supplyvotage Nog 4550 SV See pF PAE. CAS, WEE Mnblent Temperature Te 0 7 °C inpuvoutput capacitance Co 7 pF _WO4 through VO, Block Diagram Generator Generator - ee | sss | al Gonerator FAS Below RAS | Internal Reresh Generator voy so Counee 14 Decode Dat Ao Ate Ape RANRHUAL Aes Ase i ae ar ssnas0 3B- 2

N. FE C uPD41464 DC Characteristics Ta = 0 to +70°C; Veo = +50V #10% Parameter Symbol Min Max Unit ‘Test Conditions ‘Standby current loc2 5.0 mA RAS = CAS = Vin Input leakage current hy 10 10 HA Vin = OV to Veg; all other pins not under test = 0V Output leakage current low =10 10 HA VO Is high-2; Vyo = 0V to Voc Output voltage, low Vou ° 04 v lon = 42 mA Output voltage, high Vou 24 Voo v lon = -S mA AC Characteristics Ta = Oto +70°C; Voo = +50V +10% ‘#PD41464-80 wPD41464-10 wPD41464~12 Parameter Symbol Min Max Min Max Min Max Unit Test Conditions Operating current, average leet 85 80 71S mA _— RAS, CAS cycling; RF tro rn Bt Operating current, refrosh cycle, lees 70 65 60 = mA_—-RAS cycling; CAS = Viyi average tre = tac min (Note 5) Operating current, page cycle, average = loca 60 55 50 mA RAS = Vy; CAS cycling; tec = tpg min (Note 5) Operating current, CAS before RAS lees 70 70 65 = mA_—-RAS cycling; CAS = Vy; tetreah cycle average te tg min Note 5) Random read orwriteoyeetime tag e020 Read-write cycle time trwo 230 270 300 ns (Note 6) Page oyele time tre 70 100 120 no (Note 6) Roftesh period thE 4 4 4 me ‘Access time from RAS trac 80 100 120 ns (Notes 7, 8) Access time from CAS. toac 40 50 60 ns (Notes 7, 9) Ouput butter turnoff dolay toFF 0. 2 oO 2 0 9 ne (Note 10) Rise and tall transition time tr 3. 8 3 50 38 50 ns (Notes2,3) FAS precharge time tae 70 90 90 ns RAS pulse width tras 80 10000 100 10000 120 10000 ns RAS hold time tasH 40 50 60 ns ‘GAS pulse width toas 40 10000 50 10000 60 —10000_—ons CAS hold time tos 80 100 120 ns RAS to CAS delay time treo 2 40 2 50 2 60 ns (Notett) TKS to RAS precharge time tone 10 10 10 ns (Note 12) CAS precharge time for nonpage cycle tcpn 25 25 25 ns CAS precharge time for page cycle top 30 40 50 ns RAS precharge CAS hold time tapc ° o 0 ns Row address setup time tasr ° ° ° ns Row address hold time tRaH 10 10 15 ns Column address setup time tase. ° ° ° ns ‘Column address hold time toa 15 15 20 ns ‘Column address hold time referenced to tan 55 65 80 ns FR 38-3

—_— AC Characteristics (cont) #PD41464-80 pPD41464-10 pPD41464-12 Parameter Symbol Min Max Min Max Min Max Unit Test Conditions Read commend hold time referenced to FAS tan 10 0 0 ns (Note 13) Read command hold time referenced to TAS tac 0 ° 0 ns (Note 13) ‘Write command hold time won 20 25 30 ns ‘Write command hold time referenced to RAS wor 60 75 90 ne ‘Write command pulse width ‘we 20 15 20 ns ‘Write command to FIAS lead time few. 30 35 40 ns ‘Write command to GAS lead time tm 35 40 ne Datain setup time tos, ° ° ° ns (Note 14) Datain hold time ton 20 25 30 ns (Note 14) Date-in hold time referenced to RAS tour CJ 75 90 ns ‘Write command setup time wes 0 0 0 ns (Note 15) to WE delay tewo 105 130 155 ns (Note 15) TKS to WE delay towo CJ 80 95 ns__(Note 15) ‘Access time from OE tora 20 25 30 ns Data delay time toco 25 30 ns ‘DE command hold time toeH ° 0 0 ns Output turnoff delay from OE fez 0 COOHCCiC OE to RAS Inactive setup time toes 10 10 0 ns Read of write cycle time for counter test cycle trac 186 220 245 ns (Note 16) Read or write cycle time for counter test cycle trrwc 248 280 325 ns (Note 16) TAR st tin or CRS betes FAS rere sh 10 ” ns ~~ le TKS hold time forCAS betore FAS refresh tour 15 20 25 ns cyt 3B-4

Notes: (1) An initial pause of 100 ns (RAS inactive) is required after (10) torr (max) and togz (max) define the time at which the output ‘power-up, followed by any eight RAS cycles, before proper device achieves the open-circuit condition and are not referenced to operation is achieved. Vou oF Voi (2) AC measurements assume tr = 51s. ay Operesion within ‘ taco freed Tok bepiried that fare (man) can be met. t; nax) is speci as a reference point pif (@) Vin (rin) and Vi, (max) are reference levels for measuring the trop [8 greeie than taco (max), access time ee entroved timing of input signals, exchisively by toac. (4) Ai! voltages are referenced to GNO. (12) The tcpp requirement should be applicable for RAS/CAS cycles (©) lect loos: locs: and locs depend on output loading and cycle preceded by any cycle. rates. Specified values are obtained with the output open. Forlot Either: i code K of the pPD41464-18, fa (min) must be 270 ne and loca") than oF tacr must be satisfied fora read cycle, = 60 mA. (14) These parameters are referenced to the leading edge of CAS for rite cycles | ling edge of it (6) The minimum specifications are used only to indicate the cycle Soe ee ta cian na e990 01 WE or delayed wie time at which proper operation over the full temperature range ; (Tq = Oto +70°C) is assured, For lot code K of the xPD41464-15, (18) twos: town, and tawp are restrictive operating parameters in tag (min) must be 270 ns. reachunteftead mocty-anite cycles only. if wos 2 twos (min), ‘the cycle is an early write cycle and the data I/O pins will remain (7) Load = 2TTL loads and 100 pF high impedance throughout the entire cycle. If towo 2 tcwo (8) Assumes that taco < taco (max). If tacp is greater than the (min), tawo = tawo (min), the cycle Is a read-write cycle and the maximum recommended value in this table, taac increases by data /O pins will contain data read from the selected cell. If the amount that tacp exceeds the value shown, For a CAS before neither of the above conditions is met, the condition of the data RAS refresh counter test cycle, tnac is specified a8 trac = tcHn VO pins (at access time and until CAS returns to Vix) is + top + tcac + 2ty and is greater than the maximum specified indeterminate. 3b vahie shown in this table. (16) trac and trawe are applicable for CAS before RAS refresh (9) Assumes that taco = taco (max). counter test cycles. 38-5

pPD41464 N; fx Cc Timing Waveforms RAS ° _ CRP: — tRP: ois same a 0 a {mp =. AB-6

Timing Waveforms (cont) Early Write Cycle tcRP: aor TAP ne DAK «ZI. _| | VTL = CL » TMLK=

Timing Waveforms (cont) OE -Controlied Write Cycle “TT || raines 1] K_ vonrctos KM concen W/L) | [oe TLL VTL _ _— Ul = | a zi a | | © TLL Rv TLL oe |. on 3er8

N; fx Cc pyPD41464 Timing Waveforms (cont) Read-Write/Read-Modlfy-Write Cycle Mn X= NOK = = NUIT 3B-9

Timing Waveforms (cont) Page Read Cycle “TH cm | ‘oe i i be ee CA eee ee mm 'RAH CAH: i rcs, TRRH % — 1 MILL : _ nt t0Ez toez —

Timing Waveforms (cont) Page Write Cycle (Early Write) a “HV 36-11

Timing Waveforms (cont) Page Read-Write/Read-Modity-Write Cycle — ra teas pases (Doe MOK 2 HUTT KLLILLLLLL LLL i yr rl : © TTL RET gt FEMI, 3-12

N; fx Cc uPD41464 Timing Waveforms (cont) RAS-Only Refresh Cycle 3B-13

Timing Waveforms (cont) CAS Betore RAS Retresh Cycle tro: 1RAS. RAS CHR: TAP: tos tRPC: os asross Dont Care WE Don't Care e Don't Care 1, High impedance 3B-14

Timing Waveforms (cont) tasa - se tl as asso Dis NOC AO nn a me ; canna 3B-15

pPD41464 N; fx Cc a CAS Before RAS Retresh Counter Test The uPD41464 provides a method to verify proper oper (1) Write “0” into 256 memory cells with 256 CAS before ation of the internal address counter used in before RAS refresh counter test write cycles. Use the same. RAS refreshing. After a CAS before RAS refresh cycle is column address in each cycle. ila ee ow while Abs Hold tow vo (2) Use a counter test read-modity.-write cycle to read cr), the “0” written in the first cycle of step 1 and then enable read, write, or read-modify-write operation. As write a “1” into that location in the same shown In the appropriate timing waveforms, a refresh Perform this operation 256 times, until a “1” is counter test can ‘be initiated et this Oo ned by the written into each of the 256 memory cells. Continue row and column addresses. The row is sel A interna! address counter, and the column is defined by using the same column address as specitied in step an external address supplied at the second falling edge . of CAS. Test patterns can be generated in several ways; (3) Read each “1” written in step 2 using a counter test the following example is one possibility. Any pattern read cycle. must be preceded by the normal power-up. jure containing a pause of 100 us and then eight FS anos (4) Complement the test pattern and repeat steps 1, 2, to initialize the internal counter. . 38-16

N; fx Cc uPD41464 Timing Waveforms (cont) CAS Betore RAS Refresh Counter Yest Read Cycle os aoa ae al ee MMi 3 RAC: | NOEZ Bie ot 3B17

Timing Waveforms (cont) CAS Before RAS Retresh Counter Test Write Cycle « WW : VILL. 3B18

Timing Waveforms (cont) CAS Betore RAS Refresh Counter Test Read-Modify-Write Cycle TRWC- RAS. TRP: Fas test ICSR: CHR: Ne CAS. ] a | tcPN. rams BORRRMKRMKND, _coverasrn_RROKRORN KARAM? H rewo ‘ama —| a tom. RCS- tCWD- 1 WP- . | e OA tcAc tOEZ 'DH: " i ae a |____ ro betceo-sf-s f-tos 389