D40NF

STD40NF02L STMICROELECTRONICS | Alldatasheet

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Technical content

N-CHANNEL 20V - 0.01Ω - 40A DPAK LOW GATE CHARGE STripFET  POWER MOSFET TARGET DATA n TYPICAL RDS(on) = 0.01Ω n TYPICAL Qg = 35 nC @ 10V n OPTIMAL R DS(on)xQ g TRADE-OFF n CONDUCTION LOSSES REDUCED n SWITCHING LOSSES REDUCED

DESCRIPTION

This application specific Power Mosfet is the third generation of STMicroelectronics unique ”Single Feature Size ” strip-based process. The resul- ting transistor shows the best trade-off between on-resistance and gate charge. When used as high and low side in buck regulators, it gives the best performance in terms of both conduction and switching losses. This is extremely important for motherboards where fast switching and high effi- ciency are of paramount importance.

APPLICATIONS

n SPECIFICALLY DESIGNED AND OPTIMISED FOR HIGH EFFICIENCY CPU CORE DC/DC CONVERTERS INTERNAL SCHEMATIC DIAGRAM 20/01/2000 ABSOLUTE MAXIMUM RATINGS Symbol Parameter Value Unit V DS Drain-source Voltage (VGS =0 ) 2 0 V V DGR Drain- gate Voltage (RGS =2 0k Ω )2 0 V V GS Gate-source Voltage ± 20 V ID (•) Drain Current (continuous) at Tc =2 5 oC2 0 A ID (•) Drain Current (continuous) at Tc =1 0 0oC2 0 A IDM (••) Drain Current (pulsed) 80 A P tot Total Dissipation at Tc =2 5 oC5 5 W Derating Factor 0.37 W/ o C Tstg Storage Temperature -65 to 175 o C Tj Max. Operating Junction Temperature 175 o C (•) Current Limited By The Package (••) Pulse width limited by safe operating area TYPE V DSS R DS(on) ID STD40NF02L 20 V < 0.013 Ω 40 A ADD SUFFIX ”T4” FOR ORDERING IN TAPE & REEL DPAK TO-252 (Suffix ”T4”)

Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max Maximum Lead Temperature For Soldering Purpose 2.73 62.5 300 oC/W oC/W oC ELECTRICAL CHARACTERISTICS (Tcase =2 5oC unless otherwise specified) OFF Symbol Parameter Test Conditions Min. Typ. Max. Unit V (BR)DSS Drain-source Breakdown Voltage ID =2 5 0µ AV GS =0 2 0 V IDSS Zero Gate Voltage Drain Current (VGS =0 ) V DS =M a xR a t i n g V DS =M a xR a t i n g T c =125 oC µ A µ A IGSS Gate-body Leakage Current (VDS =0 ) V GS = ± 20 V ± 100 nA ON (∗) Symbol Parameter Test Conditions Min. Typ. Max. Unit V GS(th) Gate Threshold Voltage VDS =V GS ID = 250 µ A1 2 . 5 V R DS(on) Static Drain-source On Resistance V GS =1 0 V I D =2 0A V GS =5 V I D =2 0A 0.01 0.015 0.013 0.019 Ω Ω ID(on) On State Drain Current VDS >I D(on) xR DS(on )max V GS =1 0V 20 A DYNAMIC Symbol Parameter Test Conditions Min. Typ. Max. Unit gfs (∗)F o r w a r d Transconductance V DS >I D(on) xR DS(on )max ID =20 A 40 S C iss C oss C rss Input Capacitance Output Capacitance Reverse Transfer Capacitance V DS =2 5V f=1M H z V GS = 0 1500 900 200 pF pF pF STD40NF02L

ELECTRICAL CHARACTERISTICS (continued) SWITCHING ON Symbol Parameter Test Conditions Min. Typ. Max. Unit td(on) tr Turn-on Delay Time Rise Time V DD =1 5V I D =2 0A R G =4 . 7 Ω V GS =4 . 5V (Resistive Load, see fig. 3) 170 ns ns Q g Q gs Q gd Total Gate Charge Gate-Source Charge Gate-Drain Charge V DD =1 6V I D =2 0A V GS =1 0V 3 6 45 nC nC nC SWITCHING OFF Symbol Parameter Test Conditions Min. Typ. Max. Unit td(off) tf Turn-off Delay Time Fall Time V DD =1 5V I D =2 0A R G =4 . 7 Ω V GS =4 . 5V (Resistive Load, see fig. 3) ns ns SOURCE DRAIN DIODE Symbol Parameter Test Conditions Min. Typ. Max. Unit ISD ISDM (•) Source-drain Current Source-drain Current (pulsed) A A V SD (∗)F o r w a r d O n V o l t a g e ISD =20 A V GS =0 1 . 2 V trr Q rr IRRM Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current I SD = 20 A di/dt = 100 A/ µ s V DD =1 5V T j =1 5 0oC (see test circuit, fig. 5) T.B.D ns µ C A (∗) Pulsed: Pulse duration = 300µs, duty cycle 1.5 % (•) Pulse width limited by safe operating area STD40NF02L

Fig. 1:Unclamped Inductive Load Test Circuit Fig. 3:Switching Times Test Circuits For Resistive Load Fig. 2:Unclamped Inductive Waveform Fig. 4:Gate Charge test Circuit Fig. 5:Test Circuit For Inductive Load Switching And Diode Recovery Times STD40NF02L

DIM. mm inch A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A2 0.03 0.23 0.001 0.009 B 0.64 0.9 0.025 0.035 B2 5.2 5.4 0.204 0.212 C 0.45 0.6 0.017 0.023 C2 0.48 0.6 0.019 0.023 D 6 6.2 0.236 0.244 E 6.4 6.6 0.252 0.260 G 4.4 4.6 0.173 0.181 H 9.35 10.1 0.368 0.397 L2 0.8 0.031 L4 0.6 1 0.023 0.039 DL2 B E G A C H A1DETAIL ”A” DETAIL ”A” TO-252 (DPAK) MECHANICAL DATA 0068772-B STD40NF02L

Information furnished is believed to be accurate and reliable. However, STMicroelect ronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a trademark of STMicroelectronics  1999 STMicroelectronics – Printed in Italy – All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japa n - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com STD40NF02L