D4066BC

CD4066BC FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

I Wide supply voltage range 3V to 15V I High noise immunity 0.45 VDD (typ.) I Wide range of digital and±7.5 VPEAK analog switching I “ON” resistance for 15V operation 80Ω I Matched “ON” resistance∆R ON = 5Ω (typ.) over 15V signal input I “ON” resistance flat over peak-to-peak signal range I High “ON”/“OFF” 65 dB (typ.) output voltage ratio @ fis = 10 kHz, RL = 10 kΩ I High degree linearity 0.1% distortion (typ.) High degree linearity @ fis = 1 kHz, Vis = 5Vp-p, High degree linearity VDD −VSS = 10V, RL = 10 kΩ I Extremely low “OFF” 0.1 nA (typ.) switch leakage: @ VDD −VSS = 10V, TA = 25°C I Extremely high control input impedance 1012Ω (typ.) I Low crosstalk−50 dB (typ.) between switches @ fis = 0.9 MHz, RL = 1 kΩ I Frequency response, switch “ON” 40 MHz (typ.)

Applications

 Analog signal switching/multiplexing  Signal gating  Squelch control  Chopper  Modulator/Demodulator  Commutating switch  Digital signal switching/multiplexing  CMOS logic implementation  Analog-to-digital/digital-to-analog conversion  Digital control of frequency, impedance, phase, and analog-signal-gain Ordering Code: Devices also available in T ape and Reel. Specify by appending suffix letter “X” to the ordering code. Connection Diagram Schematic Diagram Order Number Package Number Package Description CD4066BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow CD4066BCSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide CD4066BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide

www.fairchildsemi.com 2 CD4066BC Absolute Maximum Ratings (Note 1) (Note 2) Recommended Operating Conditions (Note 2) Note 1: “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. They are not meant to imply that the devices should be operated at these limits. The tables of “Recom- mended Operating Conditions” and “Electrical Characteristics” provide con- ditions for actual device operation. Note 2: V SS = 0V unless otherwise specified. Supply Voltage (VDD ) −0.5V to +18V Input Voltage (VIN) −0.5V to VCC +0.5V Storage Temperature Range (TS) −65°C to +150°C Power Dissipation (PD ) Dual-In-Line 700 mW Small Outline 500 mW Lead Temperature (T (Soldering, 10 seconds) 300 °C Supply Voltage (VDD ) 3V to 15V Input Voltage (VIN) 0V to V DD Operating Temperature Range (TA) −40°C to +85°C Symbol Parameter Conditions −40°C +25°C +85°C Units Min Max Min Typ Max Min Max IDD Quiescent Device Current V DD = 5V 1.0 0.01 1.0 7.5 µA VDD = 10V 2.0 0.01 2.0 15 µA VDD = 15V 4.0 0.01 4.0 30 µA SIGNAL INPUTS AND OUTPUTS R ON “ON ” Resistance R L = 10 kΩ to (VDD − VSS /2) VC = VDD , VSS to VDD VDD = 5V 850 270 1050 1200 Ω VDD = 10V 330 120 400 520 Ω VDD = 15V 210 80 240 300 Ω ∆R ON ∆“ON ” Resistance Between R L = 10 kΩ to (VDD − VSS /2) Any 2 of 4 Switches V CC = V DD, VIS = VSS to VDD VDD = 10V 10 Ω VDD = 15V 5 Ω IIS Input or Output Leakage V C = 0 ±50 ±0.1 ±50 ±200 nA Switch “OFF ” CONTROL INPUTS VILC LOW Level Input V IS = V SS and VDD Voltage V OS = V DD and VSS IIS = ± 10µA VDD = 5V 1.5 2.25 1.5 1.5 V VDD = 10V 3.0 4.5 3.0 3.0 V VDD = 15V 4.0 6.75 4.0 4.0 V VIHC HIGH Level Input V DD = 5V 3.5 3.5 2.75 3.5 V Voltage V DD = 10V (Note 7) 7.0 7.0 5.5 7.0 V VDD = 15V 11.0 11.0 8.25 11.0 V IIN Input Current V DD −VSS = 15V ± 0.3 ± 10−5 ± 0.3 ± 1.0 µA VDD ≥VIS≥V SS VDD ≥VC ≥V SS

3 www.fairchildsemi.com CD4066BC TA = 25°C, tr = tf = 20 ns and VSS = 0V unless otherwise noted Note 3: AC Parameters are guaranteed by DC correlated testing. Note 4: These devices should not be connected to circuits with the power “ON ”. Note 5: In all cases, there is approximately 5 pF of probe and jig capacitance in the output; however, this capacitance is included in C L wherever it is specified. Note 6: VIS is the voltage at the in/out pin and VOS is the voltage at the out/in pin. VC is the voltage at the control input. Note 7: Conditions for VIHC: a) VIS = VDD , IOS = standard B series IOH b) VIS = 0V, IOL = standard B series IOL . Symbol Parameter Conditions Min Typ Max Units tPHL , tPLH Propagation Delay Time Signal VC = VDD , CL = 50 pF, (Figure 1) Input to Signal Output R L = 200k VDD = 5V 25 55 ns VDD = 10V 15 35 ns VDD = 15V 10 25 ns tPZH , tPZL Propagation Delay Time R L = 1.0 kΩ , CL = 50 pF, (Figure 2, Figure 3) Control Input to Signal V DD = 5V 125 ns Output High Impedance to V DD = 10V 60 ns Logical Level V DD = 15V 50 ns tPHZ , tPLZ Propagation Delay Time R L = 1.0 kΩ , CL = 50 pF, (Figure 2, Figure 3) Control Input to Signal V DD = 5V 125 ns Output Logical Level to V DD = 10V 60 ns High Impedance V DD = 15V 50 ns Sine Wave Distortion V C = VDD = 5V, VSS = −5V 0.1 % RL = 10 kΩ , VIS = 5Vp-p, f= 1 kHz, (Figure 4) Frequency Response-Switch V C = VDD = 5V, VSS = −5V, 40 MHz “ON ” (Frequency at −3 dB) R L = 1 kΩ , VIS = 5Vp-p,

20 Log10 VOS /VOS (1 kHz)−dB,

(Figure 4) Feedthrough — Switch “OFF ” VDD = 5.0V, VCC = VSS = −5.0V, 1.25 (Frequency at −50 dB) R L = 1 kΩ , VIS = 5.0Vp-p, 20 Log10, VOS /VIS = −50 dB, (Figure 4) Crosstalk Between Any Two V DD = VC(A) = 5.0V; VSS = VC(B) = 5.0V, 0.9 MHz Switches (Frequency at −50 dB) R L1 kΩ , VIS(A) = 5.0 Vp-p, 20 Log10, VOS(B)/VIS(A) = −50 dB (Figure 5) Crosstalk; Control Input to V DD = 10V, RL = 10 kΩ , RIN = 1.0 kΩ , 1 5 0 m V p-p Signal Output V CC = 10V Square Wave, CL = 50 pF (Figure 6) Maximum Control Input R L = 1.0 kΩ , CL = 50 pF, (Figure 7) VOS(f) = ½ VOS (1.0 kHz) VDD = 5.0V 6.0 MHz VDD = 10V 8.0 MHz VDD = 15V 8.5 MHz CIS Signal Input Capacitance 8.0 pF COS Signal Output Capacitance V DD = 10V 8.0 pF CIOS Feedthrough Capacitance V C = 0V 0.5 pF CIN Control Input Capacitance 5.0 7.5 pF

www.fairchildsemi.com 4 CD4066BC Typical Performance Characteristics “ON” Resistance vs Signal Voltage for TA = 25°C “ON” Resistance as a Function of Temperature for VDD −VSS = 15V “ON” Resistance as a Function of Temperature for VDD −VSS = 10V “ON” Resistance as a Function of Temperature for VDD −VSS = 5V Special Considerations In applications where separate power sources are used to drive VDD and the signal input, the VDD current capability should exceed VDD /RL (RL = effective external load of the 4 CD4066BC bilateral switches). This provision avoids any permanent current flow or clamp action of the VDD supply when power is applied or removed from CD4066BC. In certain applications, the external load-resistor current may include both VDD and signal-line components. To avoid drawing VDD current when switch current flows into terminals 1, 4, 8 or 11, the voltage drop across the bidirec- tional switch must not exceed 0.6V at TA ≤ 25°C, or 0.4V at TA > 25°C (calculated from RON values shown). No V DD current will flow through RL if the switch current flows into terminals 2, 3, 9 or 10.

7 www.fairchildsemi.com CD4066BC Physical Dimensions inches (millimeters) unless otherwise noted 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150 Narrow Package Number M14A

www.fairchildsemi.com 8 CD4066BC Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide Package Number M14D

9 www.fairchildsemi.com CD4066BC Quad Bilateral Switch Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N14A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD ’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com