D2-7XX83_14 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Advanced DAE-6™ Digital Audio Engine™ IC - Pin Compatible and Function/Feature Compatible with the D2Audio® DAE-3™ Device
  • Total System on Chip (SoC) - All Digital Class-D Amplifier Controller - Full 5.1/7.1/9.1-Channel Amplifier Platform Support
  • Enhanced Audio Processing Decoders -D o l b y ® Digital/AC3 -D o l b y® Pro Logic IIx -A A C L C ™ -D T S ® Digital Surround -D T S ® ES -D T S N e o : 6®
  • D 2 A u d i o® SoundSuite™ Enhancement and Virtualization
  • Mark Levinson MightyCat™ Audio Enhancement
  • Expanded On-Chip Memory Capacity
  • Integrated DSP Processing - 12 Channels of Digital Signal Processing (DSP) including Equalizers, Filters, Mixers and Other Common Audio Processing Blocks - Fully Configurable and Routable Audio Signal Paths
  • Flexible Audio Input and Output Configurations
  • Embedded 8-Channel Sample Rate Converter - Sample Rates from 32kHz up to 192kHz
  • Real-Time Amplifier Control and Monitoring - Supports Bridged, Half-Bridged, and Bridge-Tied Load (BTL) Topologies, Using Discrete or Integrated Power Stages from 10W to Over 500W - Complete Fault Protection with Automatic Recovery September 29, 2011 FN7838.2

2 FN7838.2 September 29, 2011

Ordering Information

(Note 2) PART MARKING AUDIO PROCESSING FEATURE SET SUPPORT (Note 1) TEMP. RANGE (°C) PACKAGE (Pb-Free) PKG. DWG. # D2-71083-LR D2-71083-LR Refer to Table 1 -10 to +85 128 Ld LQFP Q128.14x14 D2-74083-LR D2-74083-LR Refer to Table 1 -10 to +85 128 Ld LQFP Q128.14x14 D2-71583-LR D2-71583-LR Refer to Table 1 -10 to +85 128 Ld LQFP Q128.14x14 D2-74583-LR D2-74583-LR Refer to Table 1 -10 to +85 128 Ld LQFP Q128.14x14 D2-71683-LR D2-71683-LR Refer to Table 1 -10 to +85 128 Ld LQFP Q128.14x14 D2MC-72083-LR D2MC-72083-LR Refer to Table 1 -10 to +85 128 Ld LQFP Q128.14x14 D2MC-76083-LR D2MC-76083-LR Refer to Table 1 -10 to +85 128 Ld LQFP Q128.14x14 NOTES: 1. The D2-7xx83 devices support multiple audio processing algorithms and decoders, and support is device-dependent. Refer to Table 1 for the supported features for each device part number. 2. These Intersil Pb-free plastic packaged products employ spec ial Pb-free material sets, molding compounds/die attach materials, and 100% matte tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.

their supported features are shown in Table 1. TABLE 1. DAE-6 DEVICE PART NUMBERS AND FEATURES

2 S/PDIF Digital Inputs

8 Audio Processing Channels with PWM Outputs

  1. 147MHz DSP clock speed represents an actual DSP clock of 147.456MHz, and 160MHz DSP clock speed represents an actual DSP clock

of 159.744MHz, when using a crystal frequency of 24.576MHz.

4 FN7838.2 September 29, 2011 Table of Contents

5 FN7838.2 September 29, 2011

6 FN7838.2 September 29, 2011 Absolute Maximum Ratings (Note 6) Thermal Information Supply Voltage Input Voltage Thermal Resistance (Typical) θJA (°C/W) θJC (°C/W) http://www.intersil.com/pbfree/Pb-FreeReflow.asp Recommended Operating Conditions CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. NOTES: 4. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details. 5. For θJC, the “case temp” location is taken at the package top center. 6. Absolute Maximum parameters are not tested in production. supply currents are measured in full power down configuration. SYMBOL PARAMETER TEST CONDITIONS MIN (Note 10) TYP MAX (Note 10) UNIT VIH Digital Input High Logic Level (Note 7) RVDD = 3.3V (Scales with RVDD) 2.0 - - V V IL Digital Input Low Logic Level (Note 7) RVDD = 3.3V (Scales with RVDD) -- 0 . 8 V VOH High Level Output Drive Voltage (IOUT at - Pin Drive Strength Current, see “Pin Descriptions” on page 12) RVDD - 0.4 - - V VOL Low Level Output Drive Voltage (IOUT at + Pin Drive Strength Current, see “Pin Descriptions” on page 12) -- 0 . 4 V VIHX High Level Input Drive Voltage XTALI Pin 0.7 - PLLVDD V VILX Low Level Input Drive Voltage XTALI Pin - - 0.3 V IIN Input Leakage Current (Note 8) - - ±10 µA CIN Input Capacitance - 9 - pF VOHO High Level Output Drive Voltage OSCOUT Pin PLLVDD - 0.3 - - V VOLO Low Level Output Drive Voltage OSCOUT Pin - - 0.3 V COUT Output Capacitance - 9 - pF tRST nRESET Pulse Width - 10 - ns RVDD/ PWMVDD Typical Digital and PWM I/O Pad Ring Supply (Voltage) 3.0 3.3 3.6 V (Current, Active) - 15 - mA (Current, Power-down) - <1 - mA CVDD Typical Core Supply (Voltage) 1.7 1.8 1.9 V (Current, Active) - 450 - mA (Current, Power-down) - 15 - mA PLLVDD Typical PLL Analog Supply (Voltage) 1.7 1.8 1.9 V (Current, Active) - 25 - mA (Current, Power-down) - 10 - mA

7 FN7838.2 September 29, 2011 ADCVDD Typical ADC Analog Supply (Voltage) 3.0 3.3 3.6 V (Current, Active, Power-Down) - 12 - mA CRYSTAL OSCILLATOR Xo Crystal Frequency (Fundamental Mode Crystal) 20 24.576 24.822 (24.576 + 1%) MHz Dt Duty Cycle 40 - 60 % tSTART Start-up Time (Start-up Time is Oscillator Enabled (with Valid Supply) to Stable Oscillation) -5 2 0 m s PLL FVCO VCO Frequency 80.00 294.912 297.86 MHz FIN Input Reference Frequency 20 - 24.822 (24.576 + 1%) MHz Feedback Dividers (Integer) 4 12 15 PLL Lock Time from any Input Change - 2 - ms 1.8V POWER-ON RESET VEN Reset Enabled Voltage Level - 1.1 1.4 V tREJ POR Pulse Width Rejection - 150 500 (Note 11) µs tDIS POR Minimum Output Pulse Width - 5 - µs 1.8V BROWNOUT DETECTION Detect Level 1.4 1.5 1.6 V tBOD1 Pulse Width Rejection - 100 - ns tO1 Minimum Output Pulse Width 20 - - ns 3.3V BROWNOUT DETECTION Detect Level 2.5 2.7 2.9 V tBOD3 Pulse Width Rejection - 100 - ns tO3 Minimum Output Pulse Width 20 - - ns ADC PERFORMANCE SPECIFICATIONS VREF ADCREF DC Level I REF = 0 1.3 1.4 1.5 V IREF ADCREF Load Current - - ±20 µA RREF ADCREF Source Impedance - 14 - k Ω VAIN Analog Input Level V REF - 0.6 - V REF + 0.6 V Dynamic Range -9 4- d B THD+N - -80 - dB Gain Mismatch -0 . 1- d B Crosstalk - -80 - dB Power Supply Rejection - -70 - dB NOTES: 7. All input pins except XTALI. 8. Input leakage applies to all pins except XTALO. 9. Power-down is with device in reset and clocks stopped. 10. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 11. Limits established by characteriza tion and are not production tested. supply currents are measured in full power down configuration. (Continued) SYMBOL PARAMETER TEST CONDITIONS MIN (Note 10) TYP MAX (Note 10) UNIT

Serial Audio Interface Port Timing (Figure 1) TA = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V. All voltages referenced to ground. FIGURE 1. SERIAL AUDIO INTERFACE PORT TIMING

Two-Wire (I2C) Interface Port Timing (Figure 2) T A = +25°C, CVDD = PLLVDD = 1.8V ±5%, RVDD = PWMVDD = 3.3V ±10%. All grounds at 0.0V. All voltages referenced to ground.

  1. Data is clocked in as valid on next XTALI rising edge after SCL goes low.
  2. Limits established by characterization and not production tested.

FIGURE 2. I 2C INTERFACE TIMING

0.0V. All voltages referenced to ground. FIGURE 3. SPI TIMING

11 FN7838.2 September 29, 2011 Pin Configuration D2-71083, D2-74083, D2-71583, D2-74583, D2-71683, D2MC-72083, D2MC-76083 (128 LD LQFP) TOP VIEW SC20 SRD2 SC21 SCK2 STD2 SC22 MCLK SCK3 STD3 SC32 SC30 SC31 SRD3 STD0 SCK0 CVDD CVDD CGND CGND RGND RVDD SRD0 SC00 SC01 SCK TIO1 MISO MOSI GPIO7 GPIO3 SC02 GPIO2 PWMVDD PWM0 PWM1 PWM2 PWM3 PWMGND PWMVDD PWM4 PWM5 PWM6 PWM7 PWMGND PWMVDD PWM8 PWM9 PWM10 PWM11 PWM12 PWM13 PWMGND PWMVDD PWM14 PWM15 PWM16 PWMGND CVDD CGND RGND RVDD GPIO1 PWM17 PROTECT2 SCL0 SDA0 GPIO0 PROTECT0 PROTECT1 TIO0 nRESET nRSTOUT SRD1 SCK1 STD1 SC10 SC11 SC12 CVDD CGND RGND RVDD nSS nTRST ADCGND AIN0 ADCREF AIN1 PLLAVDD XTALO XTALI PLLTESTA PLLTESTB PLLAGND ADCVDD OSCOUT GPIO4 GPIO5 GPIO6 SDA1 SCL1 PROTECT9 SPDIFRX1 SPDIFTX TEST IRQA IRQB IRQC IRQD TIO2 CVDD CVDD CGND CGND RGND RVDD PUMPHI PSSYNC PWMSYNC PROTECT3 PROTECT4 PROTECT5 PROTECT6 PROTECT7 SPDIFRX0 PSTEMP PSCURR PUMPLO 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 103 102 101 100 104

12 FN7838.2 September 29, 2011 Pin Descriptions PIN PIN NAME (Note 14) TYPE VOLTAGE LEVEL (V) DRIVE STRENGTH (mA) DESCRIPTION 1 SC20 I/O 3.3 8 Serial Audio Interface 2, I 2S0 SCLK 2 SRD2 I/O 3.3 4 Serial Audio Interface 2, I 2S0 SDIN 3 SC21 I/O 3.3 8 Serial Audio Interface 2, I 2S0 LRCK 4 SCK2 I/O 3.3 8 Serial Audio Interface 2, I 2S1 SCLK 5 STD2 I/O 3.3 8 Serial Audio Interface 2, I 2S1 SDIN 6 SC22 I/O 3.3 4 Serial Audio Interface 2, I 2S1 LRCK 7M C L K O 3 . 3 1 6I 2S Serial Audio Master Clock output for external ADC/DAC components, drives low on reset and is enabled by firmware assignment. 8 SCK3 I/O 3.3 8 Serial Audio Interface 3, I 2S3 SCLK 9 STD3 I/O 3.3 8 Serial Audio Interface 3, I 2S3 SDIN 10 SC32 I/O 3.3 8 Serial Audio Interface 3, I 2S3 LRCK 11 SC30 I/O 3.3 8 Serial Audio Interface 3, I 2S2 SCLK 12 SC31 I/O 3.3 8 Serial Audio Interface 3, I 2S2 LRCK 13 SRD3 I/O 3.3 4 Serial Audio Interface 3, I 2S2 SDIN 14 STD0 I/O 3.3 8 Serial Audio Interface 0, I 2S SDAT0 15 SCK0 I/O 3.3 8 Serial Audio Interface 0, I 2S LRCK0 16 CVDD P 3.3 Core power, 1.8V 17 CVDD P 3.3 Core power, 1.8V 18 CGND P 3.3 Core ground 19 CGND P 3.3 Core ground 20 RGND P 3.3 Digital pad ring ground. Internally connected to PWMGND. 21 RVDD P 3.3 Digital pad ring power, 3.3V. This 3.3V su pply is used for all the digital I/O pad drivers and receivers, except for the analog pads. Internally connected to PWMVDD. 22 SRD0 I/O 3.3 4 Serial Audio Interface 0, SDIO, Defaults to input, and may be configured as GPIO by firmware. 23 SC00 I/O 3.3 8 Serial Audio Interface 0, SDIO, Defaults to input, and may be configured as GPIO by firmware. 24 SC01 I/O 3.3 8 Serial Audio Interface 0, I 2S SDAT1 25 SC02 I/O 3.3 8 Serial Audio Interface 0, I 2S LRCK1 26 SCK I/O 3.3 4 SPI clock I/O with hysteresis input. 27 TIO1 I/O 3.3 16 Timer I/O port 1. Operation and assignment is controlled by firmware. Leave unconnected when not in use. 28 MISO I/O 3.3 4 SPI master input, slave output data signal. 29 MOSI I/O 3.3 4 SPI master output, slave input data signal. 30 GPIO7 I/O 3.3 16 General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and assignment is defined by product application's firmware.) 31 GPIO3 I/O 3.3 16 General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and assignment is defined by product application's firmware.) 32 GPIO2 I/O 3.3 16 General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and assignment is defined by product application's firmware.) 33 GPIO4 I/O 3.3 16 General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and assignment is defined by product application's firmware.)

13 FN7838.2 September 29, 2011 34 GPIO5 I/O 3.3 16 General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and assignment is defined by product application's firmware.) 35 GPIO6 I/O 3.3 16 General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and assignment is defined by product application's firmware.) 36 SDA1 I/O 3.3 8 - OD Two-Wire Serial data port 1. Bidirectional signal used by both the master and slave controllers for data transport. 37 SCL1 I/O 3.3 8 - OD Two-Wire Serial clock port 1. Bidirectional signal is used by both the master and slave controllers for clock signaling. 38 PROTECT9 I/O 3.3 4 PWM protection inpu t with hysteresis. (One of 9 protection inputs. Specific function and channel assignment is defined by firmware.) 39 SPDIFRX1 I 3.3 - S/PDIF Digital audio data input 1 40 SPDIFRX0 I 3.3 - S/PDIF Digital audio data input 0 41 SPDIFTX O 3.3 4 S/PDIF Digital audio output. (Audio cont ent and audio processing signal flow is dependent upon firmware, driving stereo output up to 192kHz.) 42 TEST I 3.3 - Factory test use only. Must be tied low. 43 IRQA I 3.3 - Interrupt request port A, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or to ground & High/Low logic status establishes boot mode selection upon de-assertion of reset (nRESET) cycle. 44 IRQB I 3.3 - Interrupt request port B, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or to ground & High/Low logic status establishes boot mode selection upon de-assertion of reset (nRESET) cycle. 45 IRQC I 3.3 - Interrupt request port C, Boot Mode Select . One of 4 IRQ pins. Connects to logic high (3.3V) or to ground & High/Low logic status establishes boot mode selection upon de-assertion of reset (nRESET) cycle. 46 IRQD I 3.3 - Interrupt request port D, Boot Mode Select. One of 4 IRQ pins. Connects to logic high (3.3V) or to ground & High/Low logic status establishes boot mode selection upon de-assertion of reset (nRESET) cycle. 47 TIO2 I/O 3.3 16 Timer I/O port 2. Operation and assign ment is controlled by firmware. Leave unconnected when not in use. 48 CVDD P 3.3 - Core power, 1.8V 49 CVDD P 3.3 - Core power, 1.8V 50 CGND P 3.3 - Core ground 51 CGND P 3.3 - Core ground 52 RGND P 3.3 - Digital pad ring ground. Internally connected to PWMGND. 53 RVDD P 3.3 - Digital pad ring power, 3.3V. This 3.3V su pply is used for all the digital I/O pad drivers and receivers, except for the analog pads. Internally connected to PWMVDD. 54 PUMPHI I/O 3.3 16 Assignable I/O. Function and operation defined by firmware. 55 PUMPLO I/O 3.3 16 Assignable I/O. Function and operation defined by firmware. 56 PSSYNC I/O 3.3 16 Synchronizing output signal to swit ching power supply. (Operates under specification of firmware and resets to high impedance inactive state when not used.) 57 PSTEMP I/O 3.3 4 Assignable I/O. Function and operation defined by firmware. 58 PSCURR I/O 3.3 4 Assignable I/O. Function and operation defined by firmware. 59 PWMSYNC I/O 3.3 16 PWM synchronization port. (Function and operation is defined by firmware.) 60 PROTECT3 I/O 3.3 4 PWM protection inpu t with hysteresis. (One of 9 protection inputs. Specific function and channel assignment is defined by firmware.) Pin Descriptions (Continued) PIN PIN NAME (Note 14) TYPE VOLTAGE LEVEL (V) DRIVE STRENGTH (mA) DESCRIPTION

14 FN7838.2 September 29, 2011 61 PROTECT4 I/O 3.3 4 PWM protection inpu t with hysteresis. (One of 9 protection inputs. Specific function and channel assignment is defined by firmware.) 62 PROTECT5 I/O 3.3 4 PWM protection inpu t with hysteresis. (One of 9 protection inputs. Specific function and channel assignment is defined by firmware.) 63 PROTECT6 I/O 3.3 4 PWM protection inpu t with hysteresis. (One of 9 protection inputs. Specific function and channel assignment is defined by firmware.) 64 PROTECT7 I/O 3.3 4 PWM protection inpu t with hysteresis. (One of 9 protection inputs. Specific function and channel assignment is defined by firmware.) 65 PROTECT2 I/O 3.3 4 PWM protection inpu t with hysteresis. (One of 9 protection inputs. Specific function and channel assignment is defined by firmware.) 66 GPIO1 I/O 3.3 16 General purpose I/O Bidirectional GPIO port. (One of 8 GPIO. Resets to input port. Operation and assignment is defined by product application's firmware.) 67 RVDD P 3.3 - Digital pad ring power, 3.3V. This 3.3V su pply is used for all the digital I/O pad drivers and receivers, except for the analog pads. Internally connected to PWMVDD. 68 RGND P 3.3 - Digital pad ring ground. Internally connected to PWMGND. 69 CGND P 3.3 - Core ground 70 CVDD P 3.3 - Core power, 1.8V 71 PWMGND P 3.3 - PWM output pin ground. Internally connected to RGND. 72 PWM17 I/O 3.3 8 or 16 PWM output pin. (One of 18 PWM ou tput pins. Channel and operation assignment is defined by firmware.) 73 PWM16 I/O 3.3 8 or 16 PWM output pin. (One of 18 PWM ou tput pins. Channel and operation assignment is defined by firmware.) 74 PWM15 I/O 3.3 8 or 16 PWM output pin. (One of 18 PWM ou tput pins. Channel and operation assignment is defined by firmware.) 75 PWM14 I/O 3.3 8 or 16 PWM output pin. (One of 18 PWM ou tput pins. Channel and operation assignment is defined by firmware.) 76 PWMVDD P 3.3 - PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally connected to RVDD. 77 PWMGND P 3.3 - PWM output pin ground. Internally connected to RGND. 78 PWM13 I/O 3.3 8 or 16 PWM output pin. (One of 18 PWM ou tput pins. Channel and operation assignment is defined by firmware.) 79 PWM12 I/O 3.3 8 or 16 PWM output pin. (One of 18 PWM ou tput pins. Channel and operation assignment is defined by firmware.) 80 PWM11 I/O 3.3 8 or 16 PWM output pin. (One of 18 PWM ou tput pins. Channel and operation assignment is defined by firmware.) 81 PWM10 I/O 3.3 8 or 16 PWM output pin. (One of 18 PWM ou tput pins. Channel and operation assignment is defined by firmware.) 82 PWM9 I/O 3.3 8 or 16 PWM output pin. (One of 18 PWM ou tput pins. Channel and operation assignment is defined by firmware.) 83 PWM8 I/O 3.3 8 or 16 PWM output pin. (One of 18 PWM ou tput pins. Channel and operation assignment is defined by firmware.) 84 PWMVDD P 3.3 - PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally connected to RVDD. 85 PWMGND P 3.3 - PWM output pin ground. Internally connected to RGND. 86 PWM7 I/O 3.3 8 or 16 PWM output pin. (One of 18 PWM ou tput pins. Channel and operation assignment is defined by firmware.) Pin Descriptions (Continued) PIN PIN NAME (Note 14) TYPE VOLTAGE LEVEL (V) DRIVE STRENGTH (mA) DESCRIPTION

15 FN7838.2 September 29, 2011 87 PWM6 I/O 3.3 8 or 16 PWM output pin. (One of 18 PWM ou tput pins. Channel and operation assignment is defined by firmware.) 88 PWM5 I/O 3.3 8 or 16 PWM output pin. (One of 18 PWM ou tput pins. Channel and operation assignment is defined by firmware.) 89 PWM4 I/O 3.3 8 or 16 PWM output pin. (One of 18 PWM ou tput pins. Channel and operation assignment is defined by firmware.) 90 PWMVDD P 3.3 - PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally connected to RVDD. 91 PWMGND P 3.3 - PWM output pin ground. Internally connected to RGND. 92 PWM3 I/O 3.3 8 or 16 PWM output pin. (One of 18 PWM ou tput pins. Channel and operation assignment is defined by firmware.) 93 PWM2 I/O 3.3 8 or 16 PWM output pin. (One of 18 PWM ou tput pins. Channel and operation assignment is defined by firmware.) 94 PWM1 I/O 3.3 8 or 16 PWM output pin. (One of 18 PWM ou tput pins. Channel and operation assignment is defined by firmware.) 95 PWM0 I/O 3.3 8 or 16 PWM output pin. (One of 18 PWM ou tput pins. Channel and operation assignment is defined by firmware.) 96 PWMVDD P 3.3 - PWM output pin power. This 3.3V supply is used for the PWM pad drivers. Internally connected to RVDD. 97 OSCOUT P 1.8 - Analog oscillator output to slave D2-71x 83 devices. OSCOUT drives a buffered version of the crystal oscillator signal from the XTALI pin. 98 PLLAGND P 1.8 - PLL Analog ground 99 PLLTESTB O 1.8 - Factory test use only. Must be tied low. 100 PLLTESTA O 1.8 - Factory test use only. Must be tied low. 101 XTALI P 1.8 - Crystal oscillator analog input port. An external clock source would be driven into the this port. In multi-D2-71x83 systems, the OSCOUT from the master D2-71x83 would drive the XTALI pin. 102 XTALO P 1.8 - Crystal oscillator analog output port. When using an external clock source, this pin must be open. XTALO does not have a drive strength specification. 103 PLLAVDD P 1.8 - PLL Analog power, 1.8V 104 ADCVDD P 3.3 - Analog power for internal ADC, 3.3V 105 AIN1 I 3.3 - Analog input 1 to internal ADC 106 ADCREF O 3.3 - Analog voltage reference output. Must be de-coupled to analog ground with 1µF capacitor. 107 AIN0 I 3.3 - Analog input 0 to internal ADC 108 ADCGND P 3.3 Analog ground for internal ADC 109 nTRST I 3.3 - Factory test only. Must be tied high at all times. 110 nSS I/O 3.3 4 SPI slave select I/O. 111 RVDD P 3.3 - Digital pad ring power, 3.3V. This 3.3V su pply is used for all the digital I/O pad drivers and receivers, except for the analog pads. Internally connected to PWMVDD. 112 RGND P 3.3 - Digital pad ring ground. Internally connected to PWMGND. 113 CGND P 3.3 - Core ground 114 CVDD P 3.3 - Core power, 1.8V 115 SC12 I/O 3.3 8 Serial Audio Interface 1, LRCK 116 SC11 I/O 3.3 8 Serial Audio Interface 1, SDAT3 Pin Descriptions (Continued) PIN PIN NAME (Note 14) TYPE VOLTAGE LEVEL (V) DRIVE STRENGTH (mA) DESCRIPTION

16 FN7838.2 September 29, 2011 117 SC10 I/O 3.3 8 Serial Audio Interface 1, data (Assignment by firmware control.) 118 STD1 I/O 3.3 8 Serial Audio Interface 1, SDAT2 119 SCK1 I/O 3.3 8 Serial Audio Interface 1, SCK 120 SRD1 I/O 3.3 4 Serial Audio Interface 1, data (Assignment by firmware control.) 121 nRSTOUT O 3.3 16 - OD Active low open dr ain reset output. Pin drives low from POR generator, 3.3V brown out detector going active, or from 1.8V brown out detector going active. This output should be used to initiate a system reset to the nRESET pin upon brownout event detection. 122 nRESET I 3.3 - Active low reset input with hysteresis. Acti vates system level reset when pulled low, initializing all internal logic and program operations. System latches boot mode selection of the IRQ input pins on the rising edge. 123 TIO0 I/O 3.3 16 Timer I/O port 0. Operation and assignment is controlled by firmware. Leave unconnected when not in use. 124 PROTECT1 I/O 3.3 4 PWM protection inpu t with hysteresis. (One of 9 protection inputs. Specific function and channel assignment is defined by firmware.) 125 PROTECT0 I/O 3.3 4 PWM protection inpu t with hysteresis. (One of 9 protection inputs. Specific function and channel assignment is defined by firmware.) 126 GPIO0 I/O 3.3 16 General purpose I/O Bidirectional GPIO po rt. (One of 8 GPIO. Resets to input port. Operation and assignment is defined by product application's firmware.) 127 SDA0 I/O 3.3 8 - OD Two-Wire Serial data port 0. Bidirectional signal used by both the master and slave controllers for data transport. 128 SCL0 I/O 3.3 8 - OD Two-Wire Serial clock port 0. Bidirectional signal is used by both the master and slave controllers for clock signaling. NOTES: 14. Unless otherwise specified all pin names are active high. Those that are active low have an “n” prefix. 15. All power and ground pins of same names are to be tied together to all other pins of their same name. (i.e., CVDD pins to be tied together, CGND pins to be tied together, RVDD pins to be tied together, and RGND pins to be tied together.) CGND and RGND are to be tied together on board. RGND and PWMGND pins are also internally connected and are to be tied together. Pin Descriptions (Continued) PIN PIN NAME (Note 14) TYPE VOLTAGE LEVEL (V) DRIVE STRENGTH (mA) DESCRIPTION

12 Channel Pulse Width Modulator

4 Serial Audio Interface Ports

FIGURE 4. D2-7xx83 IC FUNCTIONAL BLOCK DIAGRAM

18 FN7838.2 September 29, 2011 Introduction The DAE-6 family of ICs provide the core functionality, amplifier control, and complete audio signal processing for D2Audio’s Class-D amplifier solutions. A variety of Reference Designs from Intersil D2Audio Corporation include specific signal flows designed for their applications, supporting today’s design features. Support is also provided for future planned features, with little or no additional hardware or logic to enable new features. The signal flow, digital audio I/O, and amplifier hardware control support is handled completely by the DAE-6 firmware. The products are targeted at high-volume Home Theater in a Box (HTiB), Multimedia, Soundbar, and similar solutions, where rich features and cost-effective quality audio are required to meeting demands of current consumer electronics markets. The DAE-6 devices are completely pin-compatible with the DAE-3 devices, allowing full flexibility for function vs cost trade-off, providing cost-effective solutions for applications of varying end-user features and capabilities. Target Performance Typical systems built around the DAE-6 support performances that includes or exceeds:

  • >110 dB SNR/Dynamic Range System Support
  • <0.06% THD+N at Full Scale at 1kHz
  • 20Hz to 20kHz Audio Frequency Response
  • Scalable Amplifier Power Control Capability
  • Discrete Component and Integrated Power Stages using Full-Bridge, Half-Bridge, and BTL Output Topologies
  • Encrypted Code Loads and Unique Decryption for each IC Part Number
  • Support for all Standard Audio Data Delivery Formats and Protocols Employed in the Target Markets
  • T h e D e l i v e r y F o r m a t s I n c l u d e : I 2S, Left-Justified, Time-Division Multiplexed (TDM), S/PDIF, DSD, HDA, 2-Channel Analog Application Markets The powerful DSP coupled with flexible peripherals and excellent signal processing hardware results in a chip for solutions that cover many markets. All are characterized by the need for complex signal processing and high audio channel count. Typical applications include a wide variety of cost sensitive but feature-demanding performance such as in:
  • Multimedia Speaker Solutions
  • Multi-Driver (Bi-Amp, Tri-Amp) Speaker Arrays
  • Home Theater Systems with Compressed Audio Decoder
  • Soundbar System Solutions
  • Set-Top Box Solutions
  • Low-Cost Virtualized Stereo, 5.1, 7.1, and 9.1 AVR Systems
  • MRDA distributed and networked audio systems with multiple powered channels
  • Aftermarket/OEM Automotive Amplifiers System Features and Support The DAE-6 enables multiple solutions consisting of a Class-D amplifier system built around internal audio processing functional blocks. Features include:
  • Flexible Audio Input and Output Configurations - 4 Independent Asynchronous I2S Digital Inputs - Support of 8 Audio Channels of HDMI -H D A u d i o ( H D A ) - Direct Stream Digital™ (DSD) Input Support - Integrated high-performance stereo ADC - Dual Multiplexed S/PDIF™ Digital Audio Inputs (Linear IEC-61958 PCM or Compressed IEC-61937 Audio) - S/PDIF Digital Audio PCM Output - Line-level Outputs (Left, Right, Subwoofer) using passive or active output filter stages
  • Flexible DSP Clock Speed and DSP Memory Capacity Options - 147.456MHz DSP Clock Speed Devices, with 24k X and Y Memory and 32k P Memory Capacity - 159.744MHz DSP Clock Speed Devices, with 24k X and Y Memory and 32k P Memory Capacity
  • Real-Time Amplifier Control and Monitoring - Supports Bridged, Half-Bridged, and Bridge-Tied Load (BTL) Topologies, using Discrete or Integrated Power Stages from 10W to Over 500W - Graceful Protection and Recovery - Complete Fault Protection with Automatic Recovery
  • Serial Control Interface via I 2C, HDA, SPI, or SCI
  • Decoding of Compressed Au dio Formats, Including -D o l b y® Digital/AC3 -D o l b y® Pro Logic IIx -A A C ™ L C -D T S ® Digital Surround -D T S ® ES -D T S N e o : 6®
  • Audio Enhancement Feature Support -D 2 A u d i o® SoundSuite™ Audio Processing Enhancement - Mark Levinson MightyCat™ Audio Processing Enhancement

Canvas™ software and system design data. of advanced processing features.

  • Flexible system configuration with 8 audio input and audio processing channels, with up to 12 audio output PWM channels, supporting differential or single-end PWM outputs with up to 18 PWM output pins.
  • Audio processing for up to 4 simultaneous stereo asynchronous digital audio inputs from a variety of sources (HDA, I 2S, HDMI, DSD, S/PDIF Digital)
  • Multiple D2-7xx83 devices may be cascaded to support higher channel count designs. Functional Description The D2-7xx83 Family of ICs, integrated into D2Audio’s offerings of reference design platforms support present and future design features with little or no additional hardware or logic to enable new features. Audio Input Multiple versions of the D2-7xx83 family IC-based reference designs support a wide range of market applications and each of these market applications has a variety of potential audio sources such as:
  • Mono and Stereo Analog Inputs
  • S e r i a l A u d i o , I 2S and Time Division Multiplexed (TDM) Single Line “Network” Mode
  • HD-Audio Interface (UAA-Class Driver Capable)
  • Stereo and Multichannel DSD
  • S/PDIF Digital (IEC60958-Compliant and IEC61937- Compliant) SERIAL AUDIO INPUT Since most systems incorporate some mix of digital and analog inputs, the DAE-6 offers a very flexible digital audio peripheral interface. The DAE-6 features four independent Serial Audio Interface (SAI) ports. All SAI ports support both master or slave clocking and can support sample rates from 32kHz to 192kHz. Each SAI port supports the digital audio industry I 2S standard, which supports carrying up to 24-bit Linear PCM audio words per subframe IEC60958, or compressed digital audio (Dolby® Digital, AAC, DTS®, MPEG, etc.) packing per the IEC61937 specification. The SAI port also supports Left-Justified formatted Linear PCM or compressed digital audio. Each SAI port supports time division multiplexing (TDM) capability (a.k.a. “Network mode”) with up to 32 words per frame. SAI ports 2 and 3 (the 3rd and 4th ports) have multiplexed inputs to provide a standard input signal flow for the ADC, DSD, and HDA audio interfaces. All serial audio input data streams go through an SAI interface, which simplifies the data flow configuration. SAI data formats are shown in Figure 5. For I 2S format, the left channel data is read when LRCK is low. For the Left-Justified format, the left channel data is read when LRCK is high. Either format requires data to be valid on the rising edge of SCLK and sent MSB-first on SDIN with 32 bits of data per channel. Each set of digital inputs runs asynchronously to the others and may accept different sample rates and formats. LRCLKx SCLKx Serial Data MSB -1 -2 -3 +3 +2 +1 LSB MSB -1 -2 -3 +3 +2 +1 LSB MSB Left Channel Right Channel I2S Format LRCLKx Left Channel Right Channel SCLKx Serial Data MSB -1 -2 -3 +3 +2 +1 LSB MSB -1 -2 -3 +3 +2 +1 LSB MSB-4 Left-Justified -4 -1

FIGURE 5. SAI PORT SUPPORTED DATA FORMATS FOR DE LIVERY OF LINEAR PCM OR COMPRESSED AUDIO DATA

and a decoder to separate audio, channel status, and user data. tolerance specified in IEC60958-4. but instead meets the IEC60958 specification.

24 BITS

FIGURE 6. ADC DECIMATOR FREQUENCY RE SPONSE (256 TAPS DECIMATE BY 32) FIGURE 7. ADC PERFORMANCE AT FULL SCALE INPUT

optimized for passband flatness. input clock and attenuate any jitter in the DSD input stream. second SAI 2 port and the SAI 3 port for other uses. consumer electronic/content protection licensing restrictions. response at 2 different frequency zoom levels. FIGURE 8. DSD DECIMATOR FREQUENCY RESPONSE (128 TAPS DECIMATE BY 16)

22 FN7838.2 September 29, 2011 Audio Output PWM AUDIO AMPLIFIER OUTPUT The D2-7xx83 family supports multiple PWM output topologies, which enables system designs to use an output stage, which meets the cost and performance requirements of the particular application. Twelve PWM channels are mapped to 18 PWM output pins by the programmed firmware. The PWM output pins are 3.3V CMOS levels with either 8mA or 16mA drive capability. Output topologies supported include:

  • Half-bridge, N+N or N+P
  • Full-bridge, N+N or N+P using 2-level modulation, 2 or 4-quadrant control LINE LEVEL OUTPUT In addition to amplified outputs, the D2-7xx83 family IC also supports line-level outputs that generate a nominal 1V RMS output using a simple passive filter. Headphone outputs or line-level outputs that require a 2VRMS (or higher output level) are also supported, using an active filter to accomplish the signal level needs. S/PDIF TRANSMITTER The D2-7xx83 contains one IEC60958 compatible S/PDIF Digital transmitter. The transmitter complies with the consumer applications defined in IEC60958-3. The transmitter supports 24-bit audio data, 24-bit user data, and 30-bit channel status data. A bit-exact pass-through mode from the selected SPDIFRX[1:0] input is also supported. This simplifies system designs that require that the IEC61937-compliant original compressed audio bitstream be made available at the back panel of the product, as well as giving the user the capability to select a decoded (and downmixed, if necessary) IEC60958-compliant stereo or mono Linear PCM output for digital audio recording/playback capabilities. The D2-7xx83 family optional firmware offers digital audio format conversion support for I 2S Digital format input to S/PDIF Digital format output, as well as S/PDIF Digital format input to I2S Digital format output, for all digital audio Linear PCM (non-compressed) audio sources. This functionality is not available for compressed audio inputs, unless the compressed audio data is first decoded by the internal DSP, and if necessary, downmixed to 2 channels. This format conversion path offers the ability to reduce the clock jitter on the output due to the fact that both inputs (when in this mode) pass through the professional-grade Sample-Rate Converters (SRC). This approach also enables consumer products to output a downsampled digital audio output for audio that may not otherwise be made available to the consumer in the original higher-bandwidth format due to certain consumer electronic/content protection licensing restrictions. SERIAL AUDIO OUTPUT D2-7xx83 family IC-based systems support outputting a bit-exact pass-through of a compressed audio bitstream, or a decoded, down-mixed (Lt/Rt or Lo/Ro) and downsampled 2 channel Linear PCM audio bitstream via a specified SAI port, or S/PDIF Digital transmitter. In addition, depending on the firmware functionality, it is possible for unused SAI (Serial Audio Interfaces) to also support I 2S output as well, in either slave or master mode. The output audio sample rate is determined by the firmware and can vary from 32kHz up to 192kHz. HD Audio HDA INTERFACE The HD Audio interface also provides a control interface. This control interface uses the HD Audio GPI, GPO, and GPIO 8-bit ports to provide a message passing facility between the D2-7xx83 and the PC. The D2-7xx83 fully supports Windows® Hardware Quality Labs (WHQL™)-certification as, it is a UAA-Compliant Secondary HD Audio CODEC. The devices may be used either as the primary HDA CODEC, or as the second HDA CODEC in the system. Features supported are:
  • Message passing to other devices located on the motherboard (e.g. HP jack detection and reporting.)
  • Amplifier firmware download.
  • Amplifier code load during system boot.
  • Amplifier control protocol (D2Audio Canvas II support). HD AUDIO PLAY The D2-7xx83 provides for direct connection of a PC’s HD Audio (HDA) Controller to the device. In this configuration, the D2-7xx83 functions as an HDA CODEC with powered (amplified) outputs. Supported Features Include:
  • 2, 4, 6, or 8 Amplified or PWM DAC Channels
  • Audio Sample Rates 48kHz, 96kHz, 192kHz
  • Data Widths of 16-bit, 20-bit, and 24-bit
  • Independent Channel Gain Control The HDA interface uses 5 of the 6 pins of the SAI 3 port. The HDA interface captures the audio streams and converts them into one to four I 2S data streams, depending on the number of channels used. These I2S stereo streams are routed through SAI 3 and SAI 4 and then on to the Sample Rate Converter. The SRC will rate lock to the HDA stream and remove any jitter while converting the data to the output sample rate.

23 FN7838.2 September 29, 2011 HD AUDIO FUNCTIONS AND FUNCTION TYPES HD AUDIO VERBS SUPPORTED TABLE 2. FUNCTION FUNCTION TYPE NODE ID CONNECTIONS Audio Function Group Function Group 01 Parent of all other nodes, also holds GPIO functions Front L/R DAC Stereo DAC 02 To Front L/R Mixer Center/LFE DAC Stereo DAC 03 To Center/LFE Mixer Surround L/R DAC Stereo DAC 04 To Surround L/R Mixer Side Surround L/R DAC Stereo DAC 05 To Side Surround Mixer Front L/R Mixer Sum/Mixer Node 06 To Front L/R Pin Center/LFE Mixer Sum/Mixer Node 07 To Center/LFE Pin Surround L/R Mixer Sum/Mixer Node 08 To Surround L/R Pin Side Surround L/R Mixer Sum/Mixer Node 09 To Side Surround L/R Pin Front L/R Output Pin Pin Complex 0A To sy stem per configuration default register Center/LFE Output Pin Pin Complex 0B To sy stem per configuration default register Surround L/R Output Pin Pin Complex 0C To sy stem per configuration default register Side Surround L/R Output Pin Pin Complex 0D T o system per configuration default register TABLE 3. VERB FUNCTION GET CODE SET CODE WIDGET NID 01 02 - 05 06 - 09 0A - 0D Converter Format A 2 Y Gain/Mute B 3 Y Processing Coefficient C 4 Coefficient Index D 5 G e t P a r a m e t e r F 0 0 YYY Y Connection Select F01 701 Get Connection List F02 Y Y Processing F03 SDI Select F04 704 Power State F05 705 Y Channel/Stream ID F06 706 Y Pin Widget F07 707 Y Unsolicited Response F08 708 Pin Sense F09 709 Y Beep F0A 70A EAPD/BTL F0C 70C Digital Converter F0D 70D - 70E Volume Knob F0F 70F GPI F10 - F1A 710 - 71A Y Config Default F1C 71C - 71F Y Subsystem ID F20 720 - 723 Y

TABLE 3. (Continued) WIDGET CAP. PCM SIZE RATE FO RMAT PIN CAP. INPUT AMP CAP.

01 Function Y Y

02 DAC Y Y Y

03 DAC Y Y Y

04 DAC Y Y Y

05 DAC Y Y Y

06 Mixer Y Y

07 Mixer Y Y

08 Mixer Y Y

09 Mixer Y Y

LENGTH POWER STATES PROCESS CAP.

01 Function Y

02 DAC

03 DAC

04 DAC

05 DAC

compatible with the DSP processing rate and PWM switch rate. and a THD+N that exceeds -125dB. own DMA, interrupt control, memory, and control interfaces. processing capability through interface to the DSP. serial audio interfaces can function as either a master or a slave.

  • Low noise crystal oscillator
  • Low jitter PLL clock multiplier
  • P o w e r o n r e s e t g e n e r a t o r
  • Brown out detectors on the CVDD and RVDD supplies
  • System reset generation logic
  • Clock generators for the DSP, S/PDIF transmitter, ADC, and MCLK output pin The PLL block is completely managed by the system firmware. The system clock is provided by the crystal oscillator block, using either a fundamental mode crystal or a clock input to the XTALI pin. If the clock input is used, it must be a 1.8V signal level. The input signal on the XTALI pin is analog buffered and driven onto the OSCOUT pin for use in driving the XTALI input of other D2-7xx83 controllers. The PLL uses the signal on the XTALI pin as the reference clock. The reference clock frequency is multiplied by an integer multiple of 4 to 15 to get the PLL output clock. The PLL output is used to time the PWM outputs and to generate the DSP clock. During system start-up, before the PLL has been configured and locked, the PLL is bypassed and the system operates at XTALI speed. HDA Link Interface Front L/R DAC Front L/R Mixer (Gain Control) Front L/R Pin Complex (Mute Control) NID 02 NID 06 NID 0A Surround L/R DAC Surround L/R Mixer (Gain Control) Surround L/R Pin Complex (Mute Control) NID 04 NID 08 NID 0C Center / LFE DAC Center / LFE Mixer (Gain Control) Center / LFE Pin Complex (Mute Control) NID 03 NID 07 NID 0B Side Surr L/R DAC Side Surr L/R Mixer (Gain Control) Side Surr L/R Pin Complex (Mute Control) NID 05 NID 09 NID 0D

FIGURE 9. HD AUDIO SYSTEM TOPOLOGY

26 FN7838.2 September 29, 2011 The power on reset circuit senses the rise of the PLLVDD supply. When the supply reaches the sense threshold, the power on reset pulse is generated. If the PLLVDD supply droops below the sense threshold, the reset pulse will occur when the supply rises above the threshold. The power on reset signal will drive the nRSTOUT output pin low. The two power supply brown out detectors monitor the CVDD and PWMVDD power rails. If the power rail droops below the threshold, the brown out detector will activate and drive the nRSTOUT output pin low. The system reset generation logic is activated by a low level on the nRESET input pin or by the power on reset sensor pulse. Upon de-assertion of nRESET a sequential counter ensures sufficient time and clock cycle count for the internal synchronous logic to reset. Multiple D2-7xx83 ICs are capable of running on a common timebase. Multiple D2-7xx83 ICs synchronize themselves onto a single crystal oscillator so that all ICs run at identical frequencies. DSP CLOCK SPEED AND MEMORY CAPACITY SUPPORT The D2-7xx83 devices are offered in part number-specific devices that support multiple DSP clock speeds and memory capacity. Depending on the device part number, the D2-7xx83 operates up to clock rates of 147.456MHz or 159.744MHz, and offers memory capacity of 24k/24k/32k or 40k/40k, 56k of X/Y/P memory space. The higher speed and larger memory devices support designs requiring higher processing capacity, while the lower speed devices provide cost optimization to systems not requiring the additional audio processing and decode capability. Refer to “DAE-6 Device Feature Set Offering” on page 3 for the device part numbers and definitions of clock speed and memory capacity. Hardware I/O Functions The D2-7xx83 provides programmable I/O pins used for various hardware functions of the system design. Pin functions are defined by the product firmware, and may be different from one design to another. GENERAL-PURPOSE (GPIO) I/O PINS, Eight dedicated General Purpose I/O (GPIO) pins are available for system use. These are controlled only by the D2-7xx83 device family firmware. TIMERS A timer block consisting of 3 separate general purpose timers provides programmed control of event or count down timing functions. The timer functions are controlled through the firmware, where these timers can operate as timed pulse generators, as pulse-width modulators, or as event counters to capture an event or to measure the width or period of a connected signal. These timers are connected to the 3 timer pins (TIO[0:2]), which are also assignable as I/O by firmware. POWER SUPPLY SYNCHRONIZATION The PSSYNC pin provides a power supply synchronization signal for switching power supplies. Firmware configures PSSYNC to the frequency and duty cycle needed by the system switching regulator. The proper configuration eliminates audio output tones generated if the switching power supply is not locked to the amplifier switching. POWER SUPPLY ANTI-PUMP D2-7xx83 supports designs to correct for power supply pumping that occurs in half-bridge output stage topologies. The PUMPHI and PUMPLO pins provide a differential PWM signal pair that drive an anti-pump correction stage. The dead time and duty cycle are adjustable to eliminate the power supply DC offset. Amplifier Protection The D2-7xx83 supports individual PWM channel protection through individual protection input pins. These PROTECT pins are primarily intended for protecting the PWM powered output stages. The protection inputs are activated by either a pulse or level driven into the pin. Firmware configures the input processing logic to properly interpret the input signal as rising edge triggered, falling edge triggered, high level, or low level. The protection input signal is generated by specialized sensing circuits. There are several kinds of sensing circuits for detecting current, temperature, or voltage. A powered PWM output stage or a power supply pump driver typically uses an overcurrent sensor. This sensor will detect power FET current, load current, or both. These circuits are unique to the specific power stage design, and may be embedded inside an integrated power stage. Temperature and voltage sensing are accomplished in a variety of ways and usually create a DC level representing a fault condition. D2-7xx83 designs incorporate a variety of protection strategies to prevent damage from the high voltages, currents, and temperatures present in class-D amplifier designs. This protection is also effective against user-induced faults, such as clipping, output overload, or output shorts, including both shorted outputs or short-to-ground faults. The D2-92xx IC works in conjunction with specific surrounding parts to provide continuous system monitoring for destructive events. These events include:

  • O u t p u t O v e r c u r r e n t
  • Output Short Circuit
  • Over-Temperature (Thermal Event)
  • Power Supply Brown Out
  • Shoot Through Overcurrent Protection features and their details are firmware application dependent. Firmware functions running on the D2-7xx83 can be assigned to observe the temperature at critical points in the hardware and automatically respond to excessive temperature. Depending on the specific implementation, this response can be as simple as turning on an optional fan to reduce temperature, or managing the audio signal to reduce power consumption.

27 FN7838.2 September 29, 2011 GRACEFUL OVERCURRENT AND SHORT CIRCUIT Overcurrent sensing requires a current sensor in the power device to be protected, usually a powered PWM output. The typical sensor creates a pulse that is active when the current exceeds a specified threshold. The D2-7xx83 IC observes the overcurrent protection inputs and provides graceful protection for the output stage. The hardware is configured to provide immediate current reduction, cycle-by-cycle output clipping, output signal control, and output stage deactivation depending on the severity and duration of high current events. The combination of hardware features and firmware monitoring allows the system to differentiate between an overcurrent situation or a more serious short circuit condition. THERMAL PROTECTION The D2-7xx83 IC can connect to an optional low-cost thermal sensing circuit and monitor temperatures in the system. Firmware monitoring can record the system temperature and provide system responses including enabling a fan and managing the audio output signal. Device Operation RESET AND INITIALIZATION The D2-7xx83 must be reset after power up to begin proper operation, and in normal system hardware configurations, the reset occurs automatically via the reset hardware circuitry. The chip contains power rail sensors, brown out detectors, on the 3.3V and 1.8V power supplies. These brown out sensors will assert and hold an internal Power-on Reset, which will disable the device until the power supplies are at a safe level for the DSP to start. These same brownout sensors will detect a power supply voltage droop while the system is active and provide a safe amplifier shutdown. POWER SEQUENCING The CVDD and RVDD (including PWMVDD) supplies should be brought up together to avoid high current transients that could fold back a power supply regulator. The ADCVDD and PLLVDD may be brought up separately. Best practice would be for all supplies to feed from regulators with a common power source. Typically this can be achieved by using a single 5V power source and regulating the 3.3V and 1.8V supplies from that 5V source. RESET D2-7xx83 has one reset input: the nRESET pin. The nRESET input pin (active low, non-reset high) is effectively a power-on system reset. All internal state logic, except internal test hardware, is initialized by nRESET. While reset is active the system is held in the reset condition. The reset condition is defined as all internal reset signals being active, the crystal oscillator is running, and the PLL disabled. At the de-assertion of nRESET, the chip will capture the boot mode selection and begin the boot process. Booting and Boot Modes CODE INITIALIZATION AND BOOT MODES D2-7xx83 includes a fully-programmable DSP with internal boot ROM. The boot ROM’s primary function is to download a second-stage boot image from one of several possible peripheral sources:

  • I 2C Interface EEPROM
  • I 2C Interface Slave
  • S P I R O M
  • S P I I n t e r f a c e S l a v e
  • H D A B u s The specific boot mode is selected based on the state of the IRQD, IRQC, IRQB, and IRQA pins at the time of reset de-assertion. The boot ROM code has been designed to handle both encrypted and non-encrypted boot images from any of the above storage locations. Boot modes are shown in Table 4. The system requires external firmware to boot the internal DSP. Internal ROM within the DAE-6 initiates the boot process to read the boot records and firmware, to load into the internal DAE-6 memory. There are multiple boot modes provided on the DAE-6 devices, as shown in Table 4. The mode is selected by a hardware pull-up or pull-down connection to each of the four boot mode (IRQ[D:A]) pins. (Modes not listed are reserved.) Boot sources include: 2C EEPROM
  • SPI EEPROM or SPI Flash 2C Slave (to external Microcontroller)
  • SPI Slave (to external Microcontroller)
  • Asynchronous UART (RS-232 fo r PC Communication Mode as well as D2-7xx83 Device to Device Communication Mode)
  • H D A u d i o B u s
  • Combo Mode with I 2C EEPROM or SPI

code loads a program that manages the system boot. interfaces are multi-master capable. being used in the application. establishes communication with the external controller device. provides access to the internal registers. TABLE 4. BOOT MODES

  1. For the “per Master” and “N/A” entries above, there is a maximum transfer rate that is a fraction of XTALI speed. This maximum transfer rate is

30 FN7838.2 September 29, 2011 Audio Processing Functions Each system design has its own firmware-dependent signal flow. This signal flow may be generic, or specifically designed for a particular amplifier application and consists of input elements connected to various signal processing blocks, routing the audio data to an output element. The input elements consist of chip peripherals used for audio input (I2S input, S/PDIF Digital receiver, and ADC). The output elements include the chip I2S output, S/PDIF Digital transmitter, and PWM outputs. Typical audio processing blocks include gain stages, mixers, tone controls, compressors, limiters, equalizers, routers, loudness contour, crossover filters, delays, as well as audio enhancement features provided within the specific application firmware. The input and output elements are configured by the firmware application and the scope of I/O selection is generally specific to the hardware of the particular application. The signal processing blocks contain one or more parameters that define the signal transfer characteristic of the block and a mechanism for choosing the source and destination data locations. The signal flow is created by connecting together the signal processing blocks in the proper order to achieve the overall system audio processing function. FIRMWARE FUNCTIONS D2-7xx83 IC contains a DSP supporting powerful audio processing algorithms. Some of the standard audio algorithms that are typically supported in all firmware loads. Other algorithms are specific system design and firmware load dependent. Additional features support multiple system capabilities such as:

  • Automatic power-on amplifier calibration
  • Parameter control and status reporting
  • Integrated power supply control and clock synchronization
  • Automatic power supply high-voltage rail anti-pump control
  • Automatic negative rail generation and bring-up control (for select half-bridge designs where a ± rail is not already supplied)
  • Automatic cycle-by-cycle temperature sensing and system response
  • Automatic cycle-by-cycle current sensing and system response
  • Input audio signal sensing and pop-free power-on/off via D2Audio’s patented “Green Mode” algorithm with adjustable threshold
  • Dynamic adjustment of efficiency vs. distortion vs. output power level via D2Audio’s patented “DynaTiming” algorithm
  • AM radio interference avoidance mode allows for dynamic switching of PWM engines when system microcontroller is in AM Radio model INPUT SOURCE SELECTION A source selection register specifies the action of a signal multiplexer, which will implement a simple switching function. The selected input will be routed to the block output unaltered. All non-selected inputs will be ignored. Selections typically include I 2S inputs, S/PDIF Digital inputs, HD Audio inputs, and ADC inputs. MASTER VOLUME A master volume function alters the level on all channels simultaneously by applying the same gain/attenuation function to each. A single parameter controls all channels. CHANNEL ATTENUATION A channel attenuation function alters the level of a single channel. A single parameter is provided for each channel. EQUALIZATION An equalization processing block consists of a single input and output, and is characterized by how many frequency bands are supported. Typical equalizers have 3-bands or 5-bands, although multiple combinations are directly supported. Each frequency band has 3 parameters - the center frequency, the filter Q, and the filter gain. TONE CONTROL Tone control provide simple bass and treble processing to the audio signal. Each tone processing block includes two first-order (6dB/octave) shelving filters, one each for bass and treble. Filters include programmable corner frequency and gain settings. EXCURSION CONTROL Excursion processing provides dynamic control of the subwoofer response. Three audio processing control adjustments are provided for frequency settings, and three adjustments are provided for Q parameter settings. MIXER Mixer configuration blocks have multiple input channels and as many output channels as required by the system implementation. The mixer has an input gain parameter for each input to every mixing node. (e.g. An 8-input mixer with 12 outputs incorporates a total of 96 independent gain adjustment parameters.) The minimum gain parameter value is infinite attenuation, or mute. MIXERS An input mixer provides a two-input, two-output mixing and routing path. All inputs can be mixed at adjustable gain into any combination of outputs. Programmable settings are continuously adjustable from unity (0 dB) gain, through full cut-off. COMPRESSOR/LIMITER The compressor/limiter processor is used to gracefully limit the dynamic range of the audio signal. This is useful to prevent the amplifier from clipping or to limit the amplifier output power. Each compressor/limiter has configurable Compression Ratio, Threshold, Attack and Release Time, as well as Makeup Gain. UPWARD COMPRESSOR Upward Compressors provide audio compression and limiting functions but also provide an increase of signal level to inputs below the threshold setting. Upward Compressors have configurable Expansion Ratio, Threshold, Attack and Release Time, as well as Makeup Gain. Controls are supported for Global settings, Gate adjustment, and for Low Level Expansion.

31 FN7838.2 September 29, 2011 Upward compressors support two inputs. One input receives the audio that is processed by the compressor and passed to its output. A separate side chain input is used as the reference input for the processing algorithms. DELAY A delay block simply adds delay to the audio signal. A single delay parameter is used. CROSSOVER Low-pass and high-pass filter blocks add frequency filtering to the audio paths, providing appropriate signal processing for speaker crossover functionality, including bi-amplified solutions, and subwoofer low-pass filtering. HIGH/LOW-PASS FILTERS High-Pass and Low-Pass filter blocks are provided for each of the 5 output channels downstream of the Router and Stereo Mixer. These provide a flexible Crossover function for all the output channels, including provision for defining the subwoofer channel’s frequency response. Filters are implemented as cascaded elements, with elements allocated for high-pass as well as for low-pass functionality, with complete flexibility of assignment. Pre-defined filter types including Butterworth, Bessel, and Linkwitz-Riley implementations are also provided. ROUTERS Routers provide individual audio path selection to any one of available input channels. The router performs path assignment only. It does not have a provision for gain or signal level adjustment. LOUDNESS CONTOUR Loudness contour provides adjustment to allow for dynamically and automatically enhancing the frequency response of the audio program material relative to the master volume Level setting. The Loudness Contour models the frequency response correction as defined by the Fletcher/Munson audio response curve. It provides for amplitude or volume changes to those signals to which the ear does not respond equally at very low listening levels. AUDIO PROCESSING ENHANCEMENTS AND DECODING Depending on the device part number and design-specific firmware definitions, the DAE-6 device supports a variety of processing, decoding, virtualization, and pre/post processing feature sets, as well as options for DSP clock speed and memory capacity. Features and processing support are shown in “DAE-6 Device Feature Set Offering” on page 3. SOUNDSUITE™ PROCESSING The D2Audio SoundSuite™ audio processing provides a full set of enhancements to audio that greatly add to the quality and listening experience of sound in wide scopes of consumer devices. The D2Audio SoundSuite™ algorithms use psycho-acoustic processing that create a rich-sounding environment from small speakers, and synthesizes the sound and quality equivalent to more complex systems. It is especially suited to consumer products that include televisions, docking stations, and mini hi-fi stereo products. The DAE-6 includes enhanced SoundSuite Processing that includes:

  • D 2 A u d i o ® WideSound™
  • D 2 A u d i o® DeepBass™
  • D 2 A u d i o® AudioAlign™
  • D 2 A u d i o® ClearVoice™ The D2Audio®SoundSuite™ algorithms are completely included within the D2-71083 and D2-74083 DAE-6 devices. MARK LEVINSON MIGHTYCAT™ PROCESSING The Mark Levinson MightyCat™ Se ries of Processors provide an exclusive set of Mastering Tools and Tuning Capabilities, and have been developed and refined by Mark Levinson over the course of his many years of recording experience. The Tools and Capabilities allow for an extended Studio Quality Tuning that is only available in the MightyCat™ Series of DAE-6 Processors. The MightyCat™ algorithms are included within the D2MC-72083 and D2MC-76083 devices. Refer also to the “DAE-6 Device Feature Set Offering” on page 3.

Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN7838.2 September 29, 2011 For additional products, see www.intersil.com/product_tree Products Intersil Corporation is a leader in the design and manufacture of high-performance analog semiconductors. The Company's products address some of the industry's fastest growing markets, such as, flat panel displays, cell phones, handheld products, and notebooks. Intersil's product families address power management and analog signal processing functions. Go to www.intersil.com/products for a complete list of Intersil product families. To report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff

Revision History

The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to web to make sure you have the latest Rev. DATE REVISION CHANGE June 23, 2011 FN7838.1 Initial release. September 20, 2011 FN7838.2 Revise/add available de vice part numbers and related descriptions.

33 FN7838.2 September 29, 2011 Low Plastic Quad Flatpack Packages (LQFP) D E e 128X b L (L1) A2A S 0 3 c1c b 33 64 97128 SEATING PLANE Y 0.080 Y DETAIL F DETAIL F 124X

0.25 GAUGE

0.05

0.07 Y T-U

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0.2 H T-U Z4X

0.2 Y T-U Z4X

H PLANE PIN 1 M Q128.14x14 128 LEAD LOW PLASTIC QUAD FLATPACK PACKAGE .4 MM PITCH SYMBOL MILLIMETERS NOTESMIN NOM MAX A - 1.60 - A1 0.05 0.15 - A2 1.35 1.40 1.45 - b 0.13 0.16 0.23 4 b1 0.13 - 0.19 - c 0.09 - 0.20 - c1 0.09 - 0.16 - D1 6 B S C - D1 14 BSC 3 E1 6 B S C - E1 14 BSC 3 L 0.45 0.60 0.75 - L1 1.00 REF - R1 0.08 - - - R2 0.08 - 0.20 - S 0 . 2 0 --- 00 ° 3 . 5 ° 7 ° - 0 1 0 ° --- 02 11° 12° 13° - 03 11° 12° 13° - N 128 - e0 . 4 0 B S C - Rev. 1 7/11 NOTES: 1. Dimensions are in millimeters. Dimensions in ( ) for Refer- ence Only. 2. Dimensions and tolerances per AMSEY14.5M-1994. 3. Dimensions D1 and E1 are excluding mold protrusion. Al- lowable protrusion is 0.25 per side. Dimensions D1 and E1 are exclusive of mold mismatch and determined by datum plane H. 4. Dimension b does not include dambar protrusion. Allowable dambar protrusion shall not cause the lead width to exceed the maximum b dimension by more than 0.08mm. Dambar cannot be located at the lower radius or the foot. Minimum space between protrusion and an adjacent lead is 0.07 mm.