D1990 | DigiCamel IC Datasheet

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UPD1990AC NEC | Alldatasheet

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NE C ELECTRONICS INC 72 ve 6427525 GOONOLY Oo qo FSG | a SERIAL I/O CALENDAR & CLOCK : CMOS LSI | Se! OO aw P The PD 1990AC is a CMOS integrated circuit having a clock function, which has been designed with the intent of connecting to microcomputer. . This IC counts independently the month, date, day of the week, hour, minute and second, and is able to have the output and input of these time data freely upon command from the microcomputer. By employing this IC, the microcomputer is freed from performing clock functions, and will be able to be use exclusively to other com- 7 plicated operations, | The uPD1990AC employs the oscillation of a32.768 kHzcrystal as a reference, And all functions are enclosed in a 14 pin dual in-line package. - FEATURES ] @ Timekeeping (hours, minutes and seconds) and calendar (months, date and day of the week). . ®@ Serial input and output of date. | (Input & output code: All digits Binary Coded Decimal, except “Month” which is Hexa-Decimal Code) @ Reference frequency is 32.768 kHz, which is generated by a crystal oscillator circuit. @ Provided with timing pulse outputs. (Selection of 64 Hz, 256 Hz or 2 048 Hz is possible.) | @ By using CS (chip selection) terminal, multi-chip applications are possible. . PACKAGE DIMENSIONS . CONNECTION DIAGRAM (Top View) | in millimeters (inches)

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(0.76 MAX.) . PAAR AA AA c; [2] 13] xtra R4 lL “ ee 36 o8 aa | “ls ETI T ET ste [4] OUT ENBL c P 39 s [5] [ro] | EE aE (+) pata in [6] [9] Data out : Pap BIg T geleS { ] GND [8] ck | 2 2/2 | 4 (Vgg) . a2 2.54 ? " " s a | (0,010) «J [2 [ee | aracur_| | 3 | co to | re [a [ste [a4 our enc _| | ps {cs [2 | Xrac_ | . [6 [oataw [13 | Xran | [7 Penotvesi [4] Voom _| ] Ga .

: NE C ELECTRONICS INC 72 DEB eye7sas goo%015 1 I : uPD1990AC “6427525 N EC ELECTRONICS INC : " 72€ 09015 0 7-5I-(9 | SERIAL 1/0 CALENDAR BLOCK DIAGRAM ! OUT ENBL O cLK oO | [_) 40 Bit Shift Register Multiplexer N-ch re FLITE TT TY | fiom Hl ° S DA’ : " se os i [) " our | Tl] i th fai Time Counter XTAL © 15 Stage Binary Divider | | ky ILIA is XTAL © ij mal , | i 32 Hz Multiplexer N-ch ii [Lge Open Drain . IK-—O TP cot te got It 7 . C9 0 | J ——— GND cso |) COMMAND SD _ : Serial Data { Latch/Decoder PS: Preset DM_ : Day ot the Week d | | CS: Chip Select STB GNDIVsg) Vpp(+) TP: Timing Pulse fosc * 32.768 kHz Vop = 2.0 t6 5.5 V I 68

WE C ELECTRONICS INC 7@ DEffeue7ses ooosou 3 Oo ‘ uPD1990AC L » 6427525 'N.E C ELECTRONICS INC ~ 72C 09016 «=D T-S/-19 ABSOLUTE MAXIMUM RATINGS | Supply Voltage Vpp-Vss. 6.0 Vv Input Voltage VIN Vgs-0.3 to Vpp +0.3 v ) Operating Temperature Range Topt —40 to +85 °c J Storage Temperature Range Tstg —56 to +125 °c Output Terminal Voltage VouT Vgs-—0.3 to 6.0 v - } ELECTRICAL CHARACTERISTICS (f=32.768 kHz,CG=CD=20 pF,Xtal Rg=20 k2,Ta=25 °C) | [_cuanaerenierc | svwooc [win | 7ve | wax] unr [ Test conorrions | : Fcowatnevatoe —[Voo-ves [200 few) v |_| Pemewen| = fe] [fee | Voi=0.4 V [ ck inmurrreaveney | fox | oc | | 100 | He | Voo-vss=20 v.buty 80 9 | Frost core | am ||| + [4a [voo-verseov | Fi utinrvotes | vw oavool [veo v | | 1 Fon tnwtinorvoiwe | vi | ves | pavool v | Fottonsrvevonne| vera | 20[ | |v [rotor | | * TP and DATA OUT are N-channel open drain output. ° A.C. ELECTRICAL CHARACTERISTICS (FOR REFERENCE --- NOT SPECIFIED) ‘ (f=32,768 kHz, Vpp—Vss=2.0 V, Ta=25 ‘C) | [—aranaereniene [son [ne |r [wai | uni [esr eonomons | : freruewon [te fa | | [= |_| sre aovovertiw [wr | | | | m [eomrtine neo | : euc-barAout oy ie| woo | || 2 | [acoamcinsor | paranewerme [ww [a | | [=| | arawnectie [ows [2 | 1 [= {| _| | * Note: When group 0 is Time Read mode, STB LATCH delay time is 40 us MAX. (tg2). Lt |

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H FUNCTION SPECIFICATIONS - @ Reference frequency (X tal osc.). © 32.768 kHz : @ Data. © Hours, Minutes, Seconds, Months, Date and Days of the Week (“Hours 24 hour form) (Automatic { adjustment of long and short months). The data is output in order to “Second”, “Minute”, “Hour’’, “Day”, “Day of Week”, “Month”. Refer to Fig. 1. @ Data format 5 © Binary Coded Decimal (except ‘‘Month” which is Hexa-Decimal Code) @ Data input-output and Clock. © Serial input, serial output. ) © Data input and output in synchronization with the clock input from the CLK. @ Timing pulse output. | © One of 64 Hz, 256 Hz or 2 048 Hz can be selected by command. @ Mode selection. © Selected according to input to Co, C1, C2. Group “O" Cg=0 Register control (control of data input-output). Group “1° Cg=1 Tp selection (Selection of timing pulses) and TEST MODE setting. © Commands of group “0” and those of group ‘1” are independently latched by the STB input. { @ Chip select. { © CLK and STB inputs prohibited by connecting CS input to GND(Vgg) level. . @ Prohibition of output of data. | © Making OUT ENBL input GND level DATA OUT terminal become high impedance. @ Leap year © The correction for length of the month is automatically performed and leap year is not automatically performed. Rut it is possible to set calendar FEB. 29, and the day after, it will be Mar. 1. (Hor Pay of Week| Ten's of | Unitof | Ten'sof | Unitof | Ten'sof | Unitof | Tensor | WOtct -Decimsl)} days days hours hours | minutes | minutes | seconds | (8cD) { (0,020, 0,)) (o~ 6) (BCD) (BCD) (BCD) (BCD) (BCD) (BCD) (BCD) |D,|p,|D,|D6| Le

40 Bit Shift Register

DATA of 40 Bit Shift Register appears on DATA OUT terminal from LSB of Second. Fig. 1 -o6ys

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TERMINALS : | @ Input terminals. © DATAIN Data input of 40 bit shift register. o CLK "Shift clock input of 40 bit shift register. | © Co~C2 Command input (3 bit). © STB Strobe input. . ° CS Chip select input (Prohibits CLK & STB). . ! © OUTENBL Output control input (Makes the DATA OUT high impedance by inputting low level). ) @ Output terminals, (N-channel Open Drain) ) © DATAOUT Data output of 40 bit shift register. | o TP Time pulse output. © Oscillation terminals. . ° XTAL Oscillation inverter input (OSC IN). ° XTAL Oscillation inverter output (OSC OUT). © Power supply terminals, : | o Vpp Plus power supply. - © GND (Vgs) Common line. COMMAND SPECIFICATIONS . | Oo 0 0 Register Hold DATA OUT = 1 Hz ; 0 (TEST MODE is released) i‘) 0 1 Register Shift DATA OUT = [LSB] y 0 1 0 Time Set & Counter Hold DATA OUT = [LSB] 7} 0 1 1 Time Read DATA OUT = 0.5 Hz ! 1 t') 0 TP = 64 Hz Set ~ (TEST MODE is released) 1 0 1 ‘TP = 256 Hz Set | (TEST MODE is released) j 1 1 0 TP = 2048 Hz Set = (TEST MODE is released) 1 1 1 TEST MODE Set * Groups “0” and “1” hold their functions independently, in other word, the command of the group “0” (""1"") ~ can change the group “0” (’1") function mode only. Then you must release the x4PD1990AC from TEST MODE by setting commands of TP selection (group “1"’) or Register Hold Mode. | @ Command input. © 3 bit, binary code input. Co,C7,C2 © Number of commands. ~ © Register contro! 4 © TP control 3) 8 | © TEST MODE set 1 ~ lM J

NE C ELECTRONICS INC 72 DE || 6427525 0005019 9 it | uPD1990AC 6427525 NE C ELECTRONICS INC ~ T2C 09019. 0 T=5)~(F © Commands. t © Register control [Group “0")} * Register Hold MODE [0 0 0] Holds the 40 Bit Shift Register, . ) The data is held, and shifting of the data becomes impossible. 1 Hz is output from the DATA OUT terminal. The TEST MODE is released by this command. * Shift MODE [00 1) | Shifting of data of the 40 Bit Shift Register becomes possible. Data is shifted in synchronization with the clock input on CLK terminal. DATA OUT terminal outputs data from [LSB] of the 40 Bit Shift Register. %* Time set MODE [0 1 0] | Presets the data of the 40 Bit Shift Register in the Time Counter, Resets the Flip-Flop (F/F) of 11 to 15 bits of the 15 Stage Binary Divider and hold the Time Counter. By setting other command of group “0”, the Time Counter is released from the reset and the hold. } [LSB] is output from the DATA OUT terminal. Shifting of data becomes impossible. . * Time read MODE [0 1 1} Reads into the 40 Bit Shift Register the data of the Time Counter. | DATA OUT terminal outputs the data of [LSB] ([LSB]=0.5 Hz). Shifting of data becomes impossible, \\ * TP = 64 Hz set MODE [100] : 64 Hz (duty 50 %) is output from the TP terminal. * TP = 256 Hz set MODE [10 1] 256 Hz (duty 50 %) is output from the TP terminal. } * TP = 2048 Hz set MODE [1 10] 2.048 Hz (duty 50 %) is output from the TP terminal. %* TEST MODE set MODE [1 1 1] | Sets up the TEST MODE (Not used for ordinary operation). When TEST MODE is released by Register Hold MODE [000], TP terminal is 64 Hz output. @ TEST MODE (Set by command of TEST mode (111)) | In this mode DATA OUT terminal is enabled in spite of OUT ENBL input. There are 2 type TEST MODE selected by OUT ENBL terminal. | TEST MODE 1 ; OUT ENBL = 0 In this mode every Counter (“Month", “Day of Week”, “Date”, “Hour”, “Minute”, “‘Second”) is advanced at a 1024 Hz in parallel. In this case overflow carry of each counter is not affect to the next counter. ey hE} EE tl 1024 Hz . TEST MODE 2 ; OUT ENBL =1 In this mode TIME COUNTER is advanced at 1024 Hz in stead of 1 Hz from “Second” counter input. [so a ee de ed | 1024 Hz A

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Following table shows the signals appeared on DATA OUT and TP terminals during the XPD1990AC is in the TEST MODE. ee _ | REGISTER HOLD ooo THz By this command, TEST MODE is released. ) ; "0" or "4" TEST T/C is advanced ) REGISTER SHIFT LSB of 40 Bit S/R “0” or “1” | 32 Hz MODE at 1024 Hz in is remained. | parallel or serial. - TIME SET pote] LSB of 40 Bit S/R “0” or “1” rr] - | TIME READ TIC is advanced | at 1024 Hzin parallel or serial. S/R = Shift Register - | T/C = Time Counter *Note: While uPD1990AC is TEST Mode, by setting the Register Hold mode (Group “0” mode), Test Mode | changes TP=64 Hz mode in group "4" and as a result Register Hold mode is set. 1 Hz appears on DATA - OUT terminal and 64 Hz appears on TP terminal. DATA INPUT/OUTPUT TIMING DIAGRAM Command (C2. C1, Cg) is set to [001] (Shift Mode). | cS="H" cLK | 4" Sec, INPUT NOL July 16 (Sun.) 36 Seconds. ouT $ ENBL L\\ OUTPUT DATA November 25 (Sat.) | OUT | | 2 Hours 23 Minutes . ‘49 Seconds. 0123456789101 a | Written-in data LSB ("H") appears at output. (Note) Reading-in timing of CPU (Trailing edge of CLK). ors |

. NE € ELECTRONICS INC 72 DE Pp buer7sas goos0el 7 i | uPD1990AC 6427525_N E C ELECTRONICS INC” | . 72C 09021 [) T-SI-19 | TIMING DIAGRAM FOR SETTING COMMANDS" - CAN CHANGE STABLE CAN CHANGE j Vi I, c2,c1,c0 r= yo" vw A—vit j Vin Vin : - i cs } tsu tHLD ‘STB. Vin {7 | VIL \\ : ts.ct ts.cr ins PO cLK \\ ‘ } ot ----- IN CASE OF BEING IN ORDINALY MODE . tat OLD MODE NEW MODE. INTERNAL | MODE OF IN CASE OF BEING IN THE TIME READ MODE | OLD MODE NEW MODE tsu = 2 us MIN. . tHLD = 2 usMIN, tstB = 2 usMIN. 1 td1 = 4 ys MAX. (In case of being in ordinaly mode.) . td2 = 40 us MAX, (In case of being in the Time Read mode.) ts-c = 2 usMIN. ¥ Note: * Setting Register Shift command (001), input level of the CLK must be fow level. ** The delay time until new mode becomes valid is 4 us. MAX. (tq7). But in the case of uPD1990AC being in the Time Read mode, it takes 40 us MAX. (tga). Love =

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| APPLICATION CIRCUIT . } cpu r---4 uPD1990AC 32.768 te : Ce 1 t Ce XTAL, S 30 pF } bl INPUT ia) oS op Co ae co XTAL 5 ~30 pF sTB sTB } DATA IN { FACE DATA IN cLK | cLK ‘ OUT ENBL OUT ENBL cs! ) [ er | ‘ ro774 DATA OUT ouTeuT DATA OUT | H INTER- | ‘ Vec_eno 1 FACE t Te vpp GND | Coan 7 45V SUPPLY } || { circuit 1 [anne com

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POWER SUPPLY CIRCUIT | 28A733 :

48 V (Vcc) - Tr to Vpp of #PD1990AC

NE C ELECTRONICS INC 22 DE I 6427525 g009025 4 if | uPD1990AC oP TIBOAG 6427525 ‘N E © ELECTRONICS “INC 72C 09025~ D 7-5/-(4 | INPUT INTERFACE For STB input 1 to Vop of uPD1990AC _ 7 i} . ‘ 2SA733 STB (CPU) 22k2 28945 16 to STB of uPD1990AC \\ Tr . 22k2 10kKA GND i For other input (C2, C1, CO, DATA IN, CLK, OUT ENBL) to Vec (+5 V) i | 3.3 kn from CPU to input terminal of 4PD1990AC OUTPUT INTERFACE (DATA OUT, TP) \\ to Voc (+5 V) 33kn to CPU from DATA OUT or TP. ' terminal of uPD1990AC OS3 :

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APPLICATION | 2SA733 Vecl+5 V) © Power Supply Voltage teen 5102 28C945 =n 47k2 ] | 77 Vee = 32.768 kQ se 3.3k2 1 po 13 Cg=30 pF | C2 Co XTAL abe Cy . cy rac? Vec Cp=5~30 pF 3.3k2 3 Co Co 4 . Vec 3.3k2 8 \\ CLK CLK é g , g DATA IN sake $1 DATA IN 3 Voc | 2 3.3k2 2 & our ENBL ‘Mourens. = csf® | 33 kn 9 DATA OUT DATA OUT e 33 kN 10 1P - Voo 2SA 733 22kQ 4 ste sTB | GND 10kQ Vss ~ ; | esd |

Product Information

D1990 specifications and overview.

Summary

SERIAL I/O CALENDAR & CLOCK CMOS LSI

Description

SERIAL I/O CALENDAR & CLOCK CMOS LSI

Source title D1990 Datasheet(PDF) - NEC

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