STD150NH02L-1 STMICROELECTRONICS | Alldatasheet

Document overview

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Technical content

Datasheet sections

  • 1 Electrical ratings
  • 2 Electrical characteristics
  • 2.1 Electrical characteristics (curves)
  • 3 Test circuit
  • 4 Package mechanical data
  • 5 Packaging mechanical data
  • 6 Revision history

N-channel 24V - 0.003Ω - 150A - ClipPAK™ - IPAK STripFET™ IlI Power MOSFET General features ■ RDS(on) * Qg industry’s benchmark ■ Conduction losses reduced ■ Switching losses reduced ■ Low threshold device

Description

The STD150NH02L utilizes the latest advanced design rules of ST’s proprietary STripFET™ technology. This novel 0.6µ process utilizes also unique metallization techniques that couple to a "bondless" assembly technique result in outstanding performance with standard DPAK outline. It is therefore ideal in high performance DC-DC converter applications where efficiency it to be achieved at very high out currents.

Applications

■ Switching application Internal schematic diagram Type VDSSS RDS(on) ID STD150NH02L STD150NH02L-1 24V 24V <0.0035Ω <0.0035Ω 150A 150A ClipPAKTM IPAK Order codes Part number Marking Package Packaging STD150NH02LT4 D150NH02L ClipPAK™ Tape & reel STD150NH02L-1 D150NH02L IPAK Tube

1 Electrical ratings

Table 1. Absolute maximum ratings

  1. Garanted when external Rg = 4.7 Ω and tf < tfmax.
  2. Pulse width limited by safe operating area

Table 2. Thermal data

2 Electrical characteristics

Table 3. On (1) /off states

  1. Pulsed: Pulse duration = 300 µs, duty cycle 1.5%

Table 4. Dynamic

  1. Pulsed: pulse duration=300µs, duty cycle 1.5%
  2. Q oss = Coss*∆ Vin , Coss = Cgd + Cds . See Appendix A
  3. Gate charge for synchronous operation

2.1 Electrical characterist ics (curves)

Figure 1. Safe operating area Figure 2. Thermal impedance Figure 3. Output characterisics Figure 4. Transfer characteristics Figure 5. Transconductance Figure 6. Static drain-source on resistance

3 Test circuit

Figure 13. Switching times test circuit for Figure 14. Gate charge test circuit Figure 15. Test circuit for inductive load Figure 16. Unclamped Inductive load test Figure 17. Unclamped inductive waveform

4 Package mechanical data

In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com

DIM. mm inch A 2.2 2.4 0.086 0.094 A1 0.9 1.1 0.035 0.043 A3 0.7 1.3 0.027 0.051 B 0.64 0.9 0.025 0.031 B2 5.2 5.4 0.204 0.212 B3 0.85 0.033 B5 0.3 0.012 B6 0.95 0.037 C 0.45 0.6 0.017 0.023 C2 0.48 0.6 0.019 0.023 D 6 6.2 0.236 0.244 E 6.4 6.6 0.252 0.260 G 4.4 4.6 0.173 0.181 H 15.9 16.3 0.626 0.641 L 9 9.4 0.354 0.370 L1 0.8 1.2 0.031 0.047 L2 0.8 1 0.031 0.039 A C H D LL2 1 3 = = B E G = = = = TO-251 (IPAK) MECHANICAL DATA 0068771-E

Packaging mechanical data STD150NH02L

5 Packaging mechanical data

DIM. mm inch MIN. MAX. MIN. MAX. A 330 12.992 B 1.5 0.059 C 12.8 13.2 0.504 0.520 D 20.2 0.795 G 16.4 18.4 0.645 0.724 N 50 1.968 T 22.4 0.881 BASE QTY BULK QTY 2500 2500 REEL MECHANICAL DATA DIM. mm inch MIN. MAX. MIN. MAX. A0 6.8 7 0.267 0.275 B0 10.4 10.6 0.409 0.417 B1 12.1 0.476 D 1.5 1.6 0.059 0.063 D1 1.5 0.059 E 1.65 1.85 0.065 0.073 F 7.4 7.6 0.291 0.299 K0 2.55 2.75 0.100 0.108 P0 3.9 4.1 0.153 0.161 P1 7.9 8.1 0.311 0.319 P2 1.9 2.1 0.075 0.082 R 40 1.574 W 15.7 16.3 0.618 0.641 TAPE MECHANICAL DATA All dimensions are in millimeters

  • The low side (SW2) device requires:
  • Very low RDS(on) to reduce conduction losses
  • Small Qgls to reduce the gate charge losses
  • Small Coss to reduce losses due to output capacitance
  • Small Qrr to reduce losses on SW1 during its turn-on
  • The Cgd/Cgs ratio lower than Vth/Vgg ratio especially with low drain to source
  • voltage to avoid the cross conduction phenomenon;
  • The high side (SW1) device requires:
  • Small Rg and Ls to allow higher gate current peak and to limit the voltage feedback on the gate
  • Small Qg to have a faster commutation and to reduce gate charge losses
  • Low RDS(on) to reduce the conduction losses.

Figure 18. Buck converter: power losses estimation

Table 7. Power losses calculation

  1. Dissipated by SW1 during turn-on

Table 8. Paramiters meaning

6 Revision history

Table 9. Revision history 20-Dec-2006 9 Typo mistake on Table 3.