PACDN006S CALMIRCO | Alldatasheet
Document overview
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Technical content
Features
Six channels of ESD protection 15KV ESD protection (HBM) 8KV contact, 15KV air ESD protection per IEC 1000-4-2 Low loading capacitance, 3 pF typ. Miniature 8-pin MSOP or SOIC package Product Description The PAC DN006 is a diode array designed to provide 6 channels of ESD protection for electronic components or sub- systems. Each channel consists of a pair of diodes which steers the ESD current pulse either to the positive (V P) or negative (VN) supply. The PAC DN006 will protect against ESD pulses up to 15 KV Human Body Model (100 pF capacitor discharging through a 1.5KΩ resistor) and 8KV contact discharge per International Standard IEC1000-4-2. This device is particularly well-suited for portable electronics (e.g. cellular phones, PDAs, notebook computers) because of its small package footprint, high ESD protection level, and low loading capacitance. It is also suitable for protecting video output lines and I/O ports in computers and peripheral equipment.
Applications
I/O port protection for cellular phones, notebook computers, PDAs, etc. ESD protection for VGA (Video) port in PCs or Notebook computers ESD protection for sensitive electronic equipment. ABSOLUTE MAXIMUM RATINGS SCHEMATIC CONFIGURATION Note 2: From I/O pins to V P or VN only. VP bypassed to V N with 0.2 µF ceramic capacitor. Note 3: Human Body Model per MIL-STD-883, Method 3015, C Discharge=100pF , RDischarge=1.5KΩ, VP=5.0V, VN=GND. Note 4: This parameter is guaranteed by design and characterization. Note 5: Standard IEC1000-4-2 with C Discharge=150pF , and RDischarge=330Ω, VP=5V, VN=GND. CALIFORNIA MICRO DEVICES 3/99 Rev. 1 ' 1999 California Micro Devices Corp. All rights reserved. PAC DN006 is a trademark of California Micro Devices Corp. 1215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com SNOITACIFICEPSDRADNATS retemaraP. niM. pyT. xaM egatloVylppuSgnitarepOV ( P V- N)V 5.5 I,egatloVdrawroFedoiD F C°52=T,Am02=V 56.0V 59.0 C°52=T,egatlovnwodkaerbesreveredoiDV 0.71 noitcetorPDSE metsys-ni,tupnIlennahCynataegatloVegrahcsiDkaeP )2etoN( 000 5103dohteM,ledoMydoBnamuH )4,3etoN( – VK51 000 2-4-0001CEIrepegrahcsiDtcatnoC )5etoN( – VK8 000 2-4-0001CEIrepegrahcsiDriA )5etoN( – VK51 C°52=T,MBHDSEVK51@egatloVpmalClennahC )4,3setoN( 000 stneisnartevitisoP 000 stneisnartevitageN VP+V 0.31 VN-V 0.31 C°52=T,tnerruCegakaeLlennahC Aµ1.0A µ0.1 )zHM1@derusaeM(ecnaticapaCtupnIlennahC VP V,V5= N ,V0=V TUPNI V5.2= Fp3F p6 gnitaRrewoPegakcaP 000 egakcaPCIOS 000 egakcaPPOSM Wm053 Wm002
'1999 California Micro Devices Corp. All rights reserved. Rev 1 3/99215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com
Application Information
See also California Micro Devices Application Note AP 209, Design Considerations for ESD Protection. In order to realize the maximum protection against ESD pulses with the PAC DN006, care must be taken in the PCB layout to minimize the parasitic series inductance to the Supply and Ground rails. Refer to Figure 1, which illustrates the case of a positive ESD pulse applied between an input channel and Chassis Ground. The parasitic series inductance back to the power supply is represented by L 1. The voltage VZ on the line being protected is: VZ = Forward voltage drop of D1 + L1 x d(Iesd)/dt + VSupply where Iesd is the ESD current pulse, and VSupply is the positive supply voltage. An ESD current pulse can rise from zero to its peak value in a very short time. As an example, consider the case of an ESD pulse that rises from zero to 10 Amps in 1nS. Here d(Iesd)/dt can be approximated by ∆Iesd/∆t, or 10/(1x10-9). So each nano Henry of series inductance (L1) will lead to a 10V increment in VZ. Figure 1 PAC DN006 Input Capacitance vs. Input Voltage 012345 Input Voltage Input Capacitance (pF) Typical variation of CIN with VIN. (VP=5V, VN=0V) NOITAMROFNIGNIREDROTRAPDRADNATS egakcaPr ebmuNtraPgniredrO sniPe lytSs ebuTl eeR&epaTg nikraMtraP 8C IOST /S600NDCAPR /S600NDCAPS 600NDP 8P OSMT /M600NDCAPR /M600NDCAP6 00D
' 1999 Calirornia Micro Devices Corp. All rights reserved. 3/99 Rev 1 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com Implementation Examples ESD events are very high speed pulses with rise times in the range of 1 nS or less. To effectively use the PAC DN006, the following design guidelines must be observed (as discussed in the application section): 1. The inductance from the V N and VP connections of the PAC DN006 to ground must be very low. This includes the path through the VP decoupling capacitor to ground and the path to the power supply (as discussed above). 2. The inductance between the connector pin to be protected and the PAC DN006 channel input pin must be kept to a minimum. (If there is a large inductance here, the ESD event will find a lower impedance path which will more likely be through the device to be protected.) Figure 2 shows the implementation schematic and Figure 3 shows a possible layout for the PAC DN006. In Figure 3, notice the large V CC and ground areas with multiple via connections to the underlying reference planes and the positioning of the bypass capacitor. Note how the signal lines to be protected flow from the connector to the PAC DN006 and then out to the device to be protected (Figures 3, 4, and 5). This daisy chaining provides a low impedance path from the connector to the PAC DN006 and a higher impedance path from the PAC DN006 to the protected device. Figure 2 ONE CHANNEL OF PAC DN006 CHANNEL INPUT GROUND RAIL POSITIVE SUPPL Y RAIL SYSTEM OR CIRCUITRY BEING PROTECTED LINE BEING DECOUPLING CAPACITOR 0.1uF PROTECTED OPTIONAL ZENER DIODE FOR EXTRA PROTECTION POWER SUPPL Y PAC DN006 Similarly for negative ESD pulses, parasitic series inductance from the VN pin to the ground rail will lead to increased negative voltage on the line being protected. Another consideration is the output impedance of the power supply for fast transient currents. Most power supplies exhibit a much higher output impedance to fast transient current spikes. In the VZ equation above, the VSupply term, in reality, is given by (VDC + Iesd x Rout), where VDC and Rout are the nominal supply DC output voltage and effective output impedance of the power supply respectively. As an example, a Rout of 1 ohm would result in a 10V increment in VZ for a peak Iesd of 10A. To mitigate this effect, a high frequency bypass capacitor should be connected between the VP pin of the PAC DN006 and the ground plane. The value of this bypass capacitor should be chosen such that it will absorb the charge transferred by the ESD pulse with minimal change in Vp. Typically a value in the 0.1 µF to 0.2 µF range is adequate for IEC-1000-4-2, level 4 contact discharge protection (8KV). Ceramic chip capacitors mounted with short printed circuit board traces are a good choice for this application. Electrolytic capacitors should be avoided as they have poor high frequency characteristics. For extra protection, connect a zener diode in parallel with the bypass capacitor to mitigate the effects of the parasitic series inductance inherent in the capacitor. The breakdown voltage of the zener diode should be slightly higher than the maximum supply voltage. As a general rule, the PAC DN006 should be located as close as possible to the point of entry of expected electrostatic discharges. The power supply bypass capacitor mentioned above should be as close to the PAC DN006 as possible, with minimum PCB trace lengths to the power supply and ground planes to minimize stray series inductance.
'1999 California Micro Devices Corp. All rights reserved. Rev 1 3/99215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com PAC DN006 Power Derating Curve Mechanical Specifications Lead Plating Tin-Lead Lead Material Copper Alloy Lead Coplanarity 0.004" (0.102mm) Substrate Material Silicon Body Material Molded Epoxy Flammability UL94V-0 MSOP - TOP VIEW CMD noitamrofnI&noitapissiDrewoP,snoisnemiDegakcaP egakcaPP OSM #sniP8 CEDEJ7 81OM mms ehcni nimx amn imx am A 49.09 0.17 30.03 40.0 A 1 50.05 1.02 00.06 00.0 B 02.00 4.08 00.06 10.0 C 80.03 2.03 00.09 00.0 D 09.20 1.34 11.02 21.0 E 09.20 1.34 11.02 21.0 e CSB46.0C SB520.0 H 87.48 9.48 81.06 91.0 L 04.09 6.06 10.07 20.0 PD C07@W m002 ebut/#s cp05 leer&epat/#s cp005,2
'1999 California Micro Devices Corp. All rights reserved. Rev 1 3/99215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com Power Derating Curve Mechanical Specifications Lead Plating Tin-Lead Lead Material Copper Alloy Lead Coplanarity 0.004" (0.102mm) Substrate Material Silicon Body Material Molded Epoxy Flammability UL94V-0 SOIC - TOP VIEW PAC DN006 C L noitamrofnI&noitapissiDrewoP,snoisnemiDegakcaP egakcaPC IOS #sniP8 CEDEJ2 10SM mms ehcni nimx amn imx am A 53.15 7.13 50.09 60.0 A 1 01.05 2.04 00.00 10.0 B 33.01 5.03 10.00 20.0 C 91.05 2.07 00.00 10.0 D 08.40 0.59 81.07 91.0 E 08.39 1.40 51.05 61.0 e CSB72.1C SB005.0 H 08.50 2.68 22.04 42.0 h 52.00 5.09 90.06 910.0 L 04.07 2.16 10.00 50.0 PD C07@W m005 ebut/#s cp001 leer&epat/#s cp005,2 Printed on recycled Paper C0240298D