HI2570 INTERSIL | Alldatasheet
Document overview
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- PDF pages: 8
Technical content
Features
- Two-Channel AD/DA Converters and Their Each Deci- mation and Oversampling Digital Filter in a Single Chip
- Simplified External Parts with a Built-In Analog Circuit Around AD Converter
- D i s t o r t i o n
- S/N Ratio (Typical Values when F S = 16kHz)
- Attenuation in the Digital Filter Rejection Band. . . 45dB>
Applications
- Telephones, TV Conference Systems, Language Lab- oratory Equipment, TV Game Equipment and Elec- tronic Musical Instrument
Description
The HI2570, CXD2570 is a 1-bit stereo AD/DA converter which uses a 2nd-order ∆ ∑ system noise shaper. This LSI is especially suited for sampling frequency between 8kHz and 32kHz. Function
- Data Can Be Input/Output at Rate of 1xF S with a Built- In Digital Filter
- Multi-Channel Systems can be Connected Using Several HI2570, CXD2570Qs
- The 32-Slot Serial Data Interface Enables Independent Selection of Data Frontward Truncation/Rearward Truncation and MSB First/LSB First
- 512F S/1024FS (when FS = 8 to 16kHz) or 256FS/512FS/ 768FS/1024FS (When F S = 16 to 32kHz) Can be Used as the Master Clock
- The Sampling Frequency of Not Only 8kHz or 16kHz, but 32kHz or 44.1kHz Can Be Used for Audio Equipment
- Various Frequency Divided Clocks are Output for LSIs Connected Pinout HI2570, CXD2570 (48 LEAD MQFP) TOP VIEW
Ordering Information
TEMP. RANGE (oC) PACKAGE PKG. NO. HI2570JCQ -20 to 55 48 Ld MPQF Q48.12x12-S CXD2570Q -20 to 55 48 Ld MPQF Q48.12x12-S 2423222120191817 1213 14 15 16 373839404142434445464748 XSL2 XSL1 XSL0 MLSL MASL DV SS SOUT SIN BCK LRCK MS DV DD AVDD3 AOUT1- AVSS3 UCLK XCLK XTLO XVSS AVSS4 AOUT2- AVDD4 XVDD XTLI AOUT1+ AVSS3 AVSS1 AIN1 AVDD1 NC NC DVDD WO DASL1 DASL0 SUB AOUT2+ AVSS4 AVSS2 AIN2 AVDD2 NC SUB NC DVSS XMCK2 TEST CLR CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved File Number 4122.1 NOT RECOMMENDED FOR NEW DESIGNS
PIN NO. SYMBOL I/O DESCRIPTION 1A V DD3 — Analog power supply for channel-1 DA converter
2 AOUT1 (-) O Analog reversed phase output of channel-1 DA converter
3A V SS3 — Analog GND for channel-1 DA converter 4 UCLK O Outputs a 1/2 frequency divider of clock input from oscillation pin XTLI (Pin 7). User clock output for the externally connected ICs. 5 XCLK O 256Fs/512Fs clock output. This provides the master clock for ICs operating in the slave mode when multiple CXD2570Qs are connected. 6X V DD — Digital power supply for the master clock 7 XTLI I Crystal oscillation circuit input. Connects the crystal oscillator selected by the crystal selector pins XSL0 to 2 (Pins 34, 35 and 36). To input an external mas- ter clock, this pin is used. 8 XTLO O Crystal oscillation circuit output. Connects the crystal oscillator selected by the crystal selector pins XSL0 to 2 (Pins 34, 35 and 36). 9X V SS — Digital GND for the master clock
10 AV SS4 — Analog GND for channel-2 DA converter
11 AOUT2 (-) O Analog reversed phase output of channel-2 DA converter
12 AV DD4 — Analog power supply for channel-2 DA converter
13 AOUT2 (+) O Analog forward phase output of channel-2 DA converter
SS4 — Analog GND for channel-2 DA converter
15 AV SS2 — Analog GND for channel-2 AD converter
16 AIN1 I Analog input of channel-2 converter
DD2 — Analog power supply for channel-2 AD converter
18 NC —
19 SUB — Connected to the substrate in the IC (having the same potential as power sup-
ply). Connect this pin to GND via a capacitor on the external printed wiring board.
20 NC —
SS —D i g i t a l G N D 22 XMCK2 O IC measurement. Normally, Low is output. 23 TEST I Test. Normally, fixed at Low. Equipped with a pull-down resistor. 24 CLR I System clear input. Normally, fixed at High; cleared at Low. Equipped with a pull-up resistor. 25 DV DD — Digital power supply. 26 MS I Master/slave mode switching input. High = Master mode. Low = Slave mode. Equipped with a pull-up resistor. 27 LRCK I/O Sampling frequency clock pin of serial I/O. Outputs in master mode (when Pin 26 is High). Inputs in slave mode (when Pin 26 is Low). Transfers channel-1 data at High; transfers channel-2 data at Low. HI2570, CXD2570
28 BCK I/O Serial bit transfer clock for serial input data SIN or serial output data SOUT
(64FS). Outputs in master mode (when Pin 26 is High). Inputs in slave mode (when Pin 26 is Low). Retrieves serial input data at ; send serial out- put data at . 29 SIN I Serial data input of 2-channel sampling. The data format is 2’s complement, and consists of 32-bit slot. 30 SOUT O Serial data output of 2-channel per sampling. The data format is 2’s comple- ment, and consists of 32-bit slot.
31 DV SS —D i g i t a l G N D
32 MASL I Selects whether 16-bit serial data is applied in the first 16-bits or the last 16-
bit of 32-bit slot in serial I/O. High = Frontward truncation; Low = Rearward truncation
33 MLSL I Selects whether 16-bit serial data is input/output at LSB first or MSB first in
serial I/O. High = MSB first; Low = LSB first 34 XSL0 I Crystal oscillator selection. Three bits, XSL0 to 2. Selects the clock frequency to be input from XTLI (Pin 7). 35 XSL1 I Crystal oscillator selection. Three bits, XSL0 to 2. Selects the clock frequency to be input from XTLI (Pin 7). 36 XSL2 I Crystal oscillator selection. Three bits, XSL0 to 2. Selects the clock frequency to be input from XTLI (Pin 7). 37 DASL0 I IC measurement. Normally, fixed at High. 38 DASL1 I IC measurement. Normally fixed at Low.
39 WO I Window masked when High; window open when Low (forced synchroniza-
tion). Equipped with a pull-up resistor. 40 DV DD — Digital power supply
41 NC —
42 NC —
43 SUB — Connected to the substrate in the IC (having the same potential as power sup-
ply). Connect this pin to GND via capacitor on the external printed wiring board. 44 AV DD1 — Analog power supply for channel-1 AD converter
45 AIN1 I Analog input of channel-1 AD converter
SS1 — Analog GND for channel-1 AD converter
47 AV SS3 — Analog GND for channel-1 DA converter
48 AOUT1 (+) O Analog forward phase output of channel-1 DA converter
Pin Descriptions (Continued) PIN NO. SYMBOL I/O DESCRIPTION HI2570, CXD2570
Absolute Maximum Ratings TA =2 5oC I/O Capacitance Recommended Operating Conditions Supply Voltage (Note 1) (V DD) 4.5V 5.0V 5.5V Input Pin (CIN) . — — 9 p F Measurement conditions: VDD = V1 = 0V, f = 1MHz CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not i mplied. NOTES: 1. The analog power supplies for AD converters (Pins 17 and 44) must be turned on simultaneously with or before other poser supp lies. turning on these power supplies after any other power supply may cause the device to fall into latch-up condition. this precaut ion, how- ever, does not apply when turning off the power supplies. 2. Although the device can operate with F S frequencies such as FS = 44.1kHz or 48kHz, its analog characteristics deteriorate to extent. When used at only these FS frequencies, the CXD255Q is recommended that is pin-compatible with the CXD2570Q. Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS PART NUMBER OR GRADE UNITS APPLICABLE PINSMIN TYP MAX DC Characteristics AVDD1 = AVDD2 = AVDD3 = AVDD4 = XVDD = DVDD = 5.0V ± 10%, AVSS1 = AVSS2 = AVSS3 = AVSS4 = XVSS = DVSS = 0V, TA = -20oC to 75oC Input Voltage V IHC 0.7VDD —— V * 1 VILC ÒÒ 0 . 3 V DD VIN Analog Input V SS —V DD V* 2 Output Voltage V OH1 IOH = -2mA V DD -0.5 — V DD V* 3 VOL1 IOL = 4mA 0 — 0.4 VOH2 IOH = -4mA V DD -0.5 — V DD V* 4 VOL2 IOL = 4mA 0 — 0.4 VOH3 IOH = -12mA V DD/2 — V DD V* 5 VOL3 IOL = 16mA 0 — V DD/2 VOH4 IOH = -2mA V DD -0.8 — V DD V* 6 VOL4 IOL = 4mA 0 — 0.4 Input Leak Current 1 I LI1 -10 — 10 µA* 7 Input Leak Current 2 I LI2 -40 — 40 µA* 8 Input Leak Current 3 I LI3 -20 -50 -12- µA* 9 Input Leak Current 4 I LI4 20 50 120 µA* 1 0 Output Leak Current I LZ -40 — 40 µA* 1 1 Feedback Resistance R FB VIN = VSS or VDD 250K 1M ‘2.5M Ω *12 Supply Current I DD (Note 3) — 43 60 mA AC Characteristics AVDD1 = AVDD2 = AVDD3 = AVDD4 = XVDD = DVDD = 5.0V ± 10%, AVSS1 = AVSS2 = AVSS3 = AVSS4 = XVSS = DVSS = 0V, TA = -20oC to 75oC SIN Setup Time tsus 10 — — ns SIN Hold Time ths 15 — — ns LRCK Setup Time tsul Slave mode 10 — — ns LRCK Hold Time thl Slave mode 15 — — ns LRCK Delay Time tdl Master mode CL = 130pF -40 — 30 ns HI2570, CXD2570
SOUT Delay Time tds CL = 60pF 9 — 65 ns SOUT Data Recovery Time tzd 7 — 42 ns SOUT Data Erase Time tdz 6 — 40 ns XTLI Pulse Width for Low Period twl FS = 16kHz, 256Fs (XSL0 = XSL1 = XSL2 = Low 40 — 200 ns NOTES: 3. This includes current consumption at load resistance (RL = 3.9 Ω). Fs = 16kHz *1 All input pins except AIN1 and AIN2, and when bidirectional pins (BCK and LRCK) are input mode. *2 AIN1, AIN2 *3 XCLK, XMCK2, SOUT *4 AOUT1 (+), AOUT1 (-), AOUT2 (+), AOUT2 (-), UCLK *5 XTLO *6 When bidirectional pins (BCK and LRCK) are output mode *7 All input pins except AIN1 and AIN2 *8 When directional pins (BCK and LRCK) are input mode *9 MS, WO, CLR *10 TEST *11 SOUT, AOUT1 (+), AOUT1 (-), AOUT2 (+), AOUT2 (-), UCLK *12 Resistance between XTLO and XTLI Electrical Specifications (Continued) PARAMETER SYMBOL TEST CONDITIONS PART NUMBER OR GRADE UNITS APPLICABLE PINSMIN TYP MAX Analog Characteristics AVDD1 = AVDD2 = AVDD3 = AVDD4 = XVDD = DVDD = 5.0V ± 10%, AVSS1 = AVSS2 = AVSS3 = AVSS4 = XVSS = DVSS = 0V, TA = 25oC ITEM CONDITIONS MIN. TYP. MAX. UNIT ADC + DAC Connection Overall Characteristics. Measured under the following conditions unless otherwise specified. Input waveform = 1kHz sine wave, 1.4Vrms (= 0dB), R IN = 16kΩ XTAI = 16.384MHz (= 1024Fs, Fs = 16kHz) CLR = MS = WO = open (= 5V) SOUT and SIN directly coupled. S/N Ratio 8kHz LPF 74 80 — dB THD + N 8kHz LPF — 0.015 0.03 % Dynamic Range 1kHz, -60dB 8kHz LPF 74 80 — dB Channel Separation 1kHz, 0dB — 97 — dB Gain Difference Between Channels — 0.1 — dB Gain RL = 3.9kW -3 0 +3 dB Input Level R IN = 0Ω —0 . 1— V r m s RIN = 16Ω —1 . 4— V r m s DC Offset (ADC Output) — 030F — Hex ADC Input Impedance — 1.2 k Ω DAC characteristics in a single unit. Measured under the following conditions unless otherwise specified. Input data = 1kHz sine wave, full scale (= 0dB) XTAI = 16.384MHz (= 1024Fs, Fs = 16kHz CLR = WO = open (= 5V), MS = GND S/N Ratio 8kHz LPF 84 90 — dB THD + N 8kHz LPF, -3dB — 0.009 0.03 % Dynamic Range 1kHz, -60dB 8kHz LPF 82 88 — dB HI2570, CXD2570
- Serial data interface [Related pins] LRCK, BCK, SOUT, SIN, MASL, MLSL The serial data format is common for both SIN (DA converter input) and SOUT (AD converter output), consisting of two channels per sampling serial data represented by 2’s com- plement. Each channel is divided into 32-bit slots, of which 16 bits are handled as data. MASL is used to select whether the 16 bits of valid data is placed in the first or the last half of the 32-bit slots. Similarly, MLSL is used to select whether the serial data is arranged at MSB first of LSB first. 2. Master mode/slave mode [Related pins] MS, LRCK, BCK When using the CXD2570Q in multiple units or in a pair with DA converter such as the CXD2558M, one of these CXD2570Qs should be in the master mode to serve as the source of clocks LRCK and BCK. The other ICs including CXD2570Qs are used in the slave mode, with their clocks LRCK and BCK supplied by the mas- ter CXD2570Q. 3. Crystal oscillator frequency selection (FS = 16kHz to 48kHz) [Related pins] XTLI, XTLO, XSL0, XSL1, XSL2, UCLK, XCLK By setting a combination of XSL0 and XSL1, with XSL2 fixed low, the frequency of the external crystal oscillator con- nected to XTLI and XTLO can be selected. In this case, XCLK outputs a clock whose frequency is always 256 times Fs, and UCLK outputs a clock that is half the crystal oscilla- tor frequency. When supplying the master clock from some other external source, not a crystal oscillator, use XTLI for this clock input and leave XTLO open. *The CXD2555Q, which has the same pin configuration with this IC is recommended when using only Fs = 32kHz to 48kHz. 4. Crystal oscillator frequency selection (FS = 8kHz to 16kHz) [Related pins] XTLI, XTLO, XSL0, XSL1, XSL2, UCLK, XCLK With XSL2 fixed High, the device can be operated with low- Fs frequencies. In this case, the frequency of the crystal oscillator can be selected by setting a combination of XSL0 and XSL1 accordingly. 5. A/D converter input level Any desired input level V IN (m . 0.1Vrms) can be selected by adjusting RIN to generate the full-scale output of the AD con- verter. VIN generation of full-scale output varies with the products, and calculate the V IN maximum level (approximately -3dB below the full-scale) using the following equation to input the signal. (1) Fs = 16kHz to 48kHz (XSL2 = Low) R IN = 1230 ⋅ VIN [Vrms] -1200 (Ω) (2) Fs = 8 to 16kHz (XSL2 = High) RIN = 26600 ⋅ VIN [Vrms] -1200 (Ω) 6. D/A converter output level To change the D/A converter output level, adjust R15, R17, R30 and R32 in Application Circuit on page. Channel Separation 1kHz, 0dB — 100 — dB Gain Difference Between Channels — 0.05 — dB Output Level R L = 3.9kW 1.80 1.93 2.10 Vrms Analog Characteristics AVDD1 = AVDD2 = AVDD3 = AVDD4 = XVDD = DVDD = 5.0V ± 10%, AVSS1 = AVSS2 = AVSS3 = AVSS4 = XVSS = DVSS = 0V, TA = 25oC (Continued) ITEM CONDITIONS MIN. TYP. MAX. UNIT MASL MLSL High Frontward truncation High MSB first Low Rearward truncation Low LSB first MS MODE LRCK AND BCK I/O High Master mode Output Low Slave mode Input XSL2 XSL1 XSL0 CRYSTAL OSCILLATOR FREQUENCY XCLK UCLK L L L 256Fs 256Fs 128Fs L L H 512Fs 256Fs 256Fs L H L 768Fs 256Fs 384Fs L H H 1024Fs 256Fs 512Fs XSL2 XSL1 XSL0 CRYSTAL OSCILLATOR FREQUENCY* XCLK UCLK H L L 512Fs 512Fs 256Fs HLH — — — H H L 1024Fs 512Fs 512Fs HHH — — — HI2570, CXD2570
HI2570, CXD2570 D EE 1 PIN 1 A 0.15 0.006 0o-10o L PLANE B SEATING e M0.24 0.10/0.25 0.004/0.010 -C- -H- Metric Plastic Quad Flatpack Packages (MQFP) Q48.12x12-S
48 LEAD METRIC PLASTIC QUAD FLATPACK PACKAGE
A 0.081 0.100 2.05 2.55 - A1 0.000 0.011 0.00 0.30 - B 0.008 0.017 0.20 0.45 5 D 0.587 0.618 14.90 15.70 2 D1 0.469 0.488 11.90 12.40 3, 4 E 0.587 0.618 14.90 15.70 2 E1 0.469 0.488 11.90 12.40 3, 4 L 0.028 0.043 0.70 1.10 - N4 8 4 8 6 e 0.032 BSC 0.80 BSC - Rev. 0 2/96 NOTES: 1. Controlling dimension: MILLIMETER. Converted inch dimen- sions are not necessarily exact. 2. Dimensions D and E to be determined at seating plane . 3. Dimensions D1 and E1 to be determined at datum plane . 4. Dimensions D1 and E1 do not include mold protrusion. 5. Dimension B does not include dambar protrusion. 6. “N” is the number of terminal positions. -C- -H-