CXD2559Q

HI2559 INTERSIL | Alldatasheet

Document overview

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• PDF pages: 11

Technical content

Features

• Two-Channel D/A Converter and Oversampling Digital Filter Into a Single Chip S or 256FS

Applications

• CD Player and CD-ROM Player, etc. Functions
• Data Can Be Input at Rate of 1 x FS with a Built-In Digital Filter
• The 24-/32-Slot Serial Data Interface Enables Independent Selection of Data Frontward Trunca- tion/Rearward Truncation and MSB First/LSB First
• Two Channels Can Be Attenuated Independently in 255 Steps
• The Output From Two Channels (L/R/L + R/Mute) Can Be Selected Independently
• Digital Emphasis

Description

The HI2559, CXD2559 is a 1-bit stereo D/A converter featur- ing a 2nd-order ∆∑ system noise shaper. This good cost per- formance LSI has functions such as digital attenuator and digital de-emphasis and others. Pinout HI2559, CXD2559 (MQFP) TOP VIEW

Ordering Information

TEMP. RANGE (oC) PACKAGE PKG. NO. HI2559JCQ -20 to 75 32 Ld MPQF Q32.7x7-S CXD2559Q -20 to 75 32 Ld MPQF Q32.7x7-S WO LATCH SHIFT ATT MLSL SIN BCK LRCK AOUT1+ AVSS2 XVDD XTLO XTLI XV SS AVSS3 AOUT2+ AVDD0 AOUT2- AVSS0 DVDD0 TEST CLR MASL DVSS0 AVDD1 AOUT1- AV SS1 DVSS1 XCLK DASL0 DASL1 DV DD1 8 161514131211109 3231 30 29 28 27 26 25 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved File Number 4120.1 NOT RECOMMENDED FOR NEW DESIGNS

(OVER SAMPLING) CLOCK GENERATOR TIMING CIRCUIT LRCK BCK SIN MASL MLSL ATT SHIFT LATCH SP HOST COMPUTER I/F XTLI XTLO XCLK DAC1 DAC2 AOUT1 (+) AOUT1 (-) AOUT2 (+) AOUT2 (-) ROM ATT1 ATT2 RAM Pin Descriptions PIN NO. SYMBOL I/O DESCRIPTION 1A V DD0 - Analog power supply for Channel 2 output. 2 AOUT2(–) O Analog reversed phase output for Channel 2. 3A D V SS0 - Analog GND for Channel 2 output. 4D V DD0 - Digital power supply. 5 TEST I IC measurement. Fixed to Low. 6 CLR I System clear input. Cleared when low. Equipped with a pull-up resistor. 7 MASL I Selects whether 16-bit serial data is placed in the first 16-bit or the second 16-bit slot of the serial IN 32-bit slots. Frontward truncation when High; rearward truncation when low. Equipped with a pulldown resistor. 8D V SS0 - Digital GND. 9 LRCK I Serial IN sampling frequency clock. Transfers Channel-1 data when High; Channel-2 data when low. 10 BCK I Serial bit transfer clock 48 F S or 64 FS in serial IN. The serial input data is retrieved at the rising edge. 11 SIN I Two channels per sampling serial data input. Data format is represented by 2’s comple- ments, and consists of 24-bit or 32-bit slots. 12 MLSL I Selects whether 16-bit serial data SIN (Pin 15) of serial IN at LSB first or MSB first. MSB- first when High; LSB-first when Low. Equipped with a pull-up resistor. HI2559, CXD2559

13 ATT I Data input of the microcomputer interface. Attenuation data, output selection setting value, and de-emphasis on/off data re-input in serial mode. 14 SHIFT I Shift clock input of the microcomputer interface. 15 LATCH I Latch input of the microcomputer interface. Latched at the rising edge. 16 WO I Synchronization window control. Window open when Low (forced synchronization). 17 DV DD1 - Digital power supply. 18 DASL1 I IC measurement. Fixed to Low. 19 DASL0 I IC measurement. Fixed High. 20 XCLK O Inversion output of the clock input from XTLI (Pin 1). 21 DV SS1 - Digital GND. 22 AV SS1 - Analog GND for Channel 1 output. 23 AOUT1 (-) O Analog reversed phase output for Channel 1. 24 AV DD1 I Analog power supply for Channel 1 output. 25 AOUT1 (+) O Analog positive phase output for Channel 1. 26 AV SS2 - Analog GND for Channel 1 output. 27 XV DD - Digital power supply for the master clock. 28 XTLO O Crystal oscillator output. Connects the master clock 256 F S or 384 FS crystal oscillator, which is identified automatically. 29 XTLI I Crystal oscillator input. Connects the master clock 256 F S or 384 FS crystal oscillator, which is identified automatically. External clock pulse is input at this pin.

30 XV SS - Digital GND for master clock

31 AV SS3 - Analog GND for Channel 2 output. 32 AOUT2 (+) O Analog positive phase output for Channel 2. Pin Descriptions (Continued) PIN NO. SYMBOL I/O DESCRIPTION HI2559, CXD2559

Absolute Maximum Ratings TA =2 5oC, VSS = 0V Operating Conditions Input/Output Capacitance Measurement conditions: VDD = VI = 0V, f = 1MHz Electrical Specifications PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS APPLICABLE PIN Input Voltage V IH 0.7 VDD - - V Note 1 VIL -- 0 . 3 V DD VIH 2.2 - - V Note 2 VIL Output Voltage V OH IOH = -2mA V DD -0.8 - 0.4 V Note 3 VOL IOL = 4mA - - 0.4 VOH IOH = -1mA V DD /2 - - V Note 4 VOL IOL = 1mA - - V DD /2 VOH IOH = -4mA V DD -0.8 - - V Note 5 VOL IOL = 4mA 0 - - Input Leakage Current 1 I IL1 VIN = VSS or VDD -10 - 10 µA Note 6 Input Leakage Current 2 I IL2 VIN = VSS or VDD -40 - 40 µA Note 7 Input Leakage Current 3 I IL VIL = VSS -40 -100 -240 µA Note 8 Input Leakage Current 4 I IH VIH = VDD 40 100 240 µA Note 9 Feedback Resistance R FB VIN = VSS or VDD 250k 1M 2.5M Ω Note 12 NOTES: 1. Input pins except for *2t 2. ATT, SHIFT, LATCH 3. XCLK 4. XLO 5. AOUT1 (+), AOUT1 (-), AOUT2 (+), AOUT2 (-) 6. ATT, SHIFT, LATCH, LRCK, BCK, SINt 7. WO 8. CLR, MLSLt 9. MASL 10. XTLI PARAMETER SYMBOL Oscillation Frequency 256 F S fx 2 - 13 MHz

384 FS 2- 2 0

External Clock Pulse Input High Level Width

258 FS tCWH 38 - 250 ns

384 FS 25 - 250 ns

HI2559, CXD2559

External Clock Pulse Input Low Level Width

256 FS tCWL 38 - 250 ns

External Clock Pulse Input Pulse Cycle (Note 2)

256 FS tCYC 76 - 500 ns

384 FS 50 - 500 ns

Input BCK Frequency f BCK -- 3 . 1 M H z Input BCK Pulse Width t WIB 100 - - ns Input Data Setup Time t IDS 10 - - ns Input Data Hold Time t IDH 15 - - ns Input LRCK Setup Time t ILRS 10 - - ns Input LRCK Hold Time t ILRH 15 - - ns Program Input Basic Time t PR 100 - - ns Latch Input Pulse Width t WLT 200 - - ns ATT Setup Time t SET 5-- n s ATT Hold Time t HOLD 100 - - ns ATT Interval t INT 300 - - ns NOTE: 11. Always input an external clock after turning the power on. ANALOG CHARACTERISTICS MEASUREMENT CONDITIONS TA = 25oC, VDD = 5.0V, FS = 44kHz, signal frequency = 1kHz, measurement band = 4Hz to 20kHz, Master Clock 384FS. S/N (EIAJ) *1 96 100 - dB THD + N (EIAJ) - 0.010 0.012 % Dynamic Range (EIAJ) *1, *2 91 93 - dB Channel Separation (EIAJ) - 90 - dB Output Level -2 . 5 8-V ( m s ) Gain Difference Between Channels - - 0.1 dB NOTES: 12. A-weighting filter used. 13. -60dB, 1kHz input. DD = 5.0 ±10%, TOPR = -20oC to 75oC PARAMETER SYMBOL HI2559, CXD2559

FIGURE 4. SERIAL DATA INTERFACE

relationship between the commands and the outputs. the relationship between the commands and the outputs. NOTE: When the data is more than three bytes are transferred to the ATT pin, only the three bytes transferred finally are effect ive. FIGURE 7. METHOD OF OBTAINING AN ATTENUATION VALUE

G. I/O Sync Circuit [Related pins] LRCK and WO (1) Operation (When the WO Pin is “H”) The synchronization circuit has the window of eight clocks of the master clock and it monitors whether the rising edge of LRCK is in the window. If the rising edge of LRCK is out of the window, resyn- chronization is automatically performed. (2) Forced Synchronization by WO Pin Even if the rising edge of LRCK is within the window, it may not synchronize owing to the mixing of the exter- nal noises, etc. when the rising edge of LRCK is posi- tioned near at both edges of the window. When the power is turned on, it is necessary to set the rising edge of LRCK in the center of the window by performing the forced synchronization. After the system is cleared, the forced synchronization is performed by setting WO pin to Low at 2/F S or more. The forced synchronization is performed at the second rising edge of LRCK after the WO pin is turned to “Low.” NOTE: WO pin must be “H” except the forced synchronization. H. System Clear When the Power is Turned ON. [Related Pins] CLR When the power is turned ON and the master clock more than 4 clocks is input to the XTLI pin, set the CLR pin from “L” to “H.” P0 P1 P2 P3 L CHANNEL OUTPUT R CHANNEL OUTPUT REMARKS 0 0 0 0 Mute Mute Mute

0001 M u t e R

0010 M u t e L

0011 M u t e L + R

0100 R M u t e

0101 R R

0110 R L R e v e r s e

0111 R L + R

1000 L M u t e

1001 L R S t e r e o

1010 L L

1100 L + R M u t e

1101 L + R R

1110 L + R L

1111 L + R L + R M o n o

NOTE: For L + R, the output data is (L + R)/2 to avoid overflow. HI2559, CXD2559

0.01 17 18 19 20 21 22 23 24 0.01 MASL B 3.9K 130K 6 3.9K 47P 3.9K 3.9K 2 8 1 47P 130K 4.7K 4.7K 4.7K 4.7K 0.01 820P 820P 0.01 1800P 82P 0.015 28 1 4.7K 4.7K 4.7K 0.01 0.01 22µ 100 12K CH1 OUT 20p 20p 384FS OR 256FS A 8 76543 2 1 D 0.01 0.01 3.9K 3.9K 47P 130K 4.7K +- +- 47P 820P 4.7K 820P C 3.9K 3.9K 130K 2 8 1 47K 0.01 47K 0.01 MLSL 4.7K 4.7K 4.7K 1800P 82P 28 1 0.01 22µ 12K 100 CH2 OUT +12V 0.01 -12V AOUT2 (+) VSS VSS XTLI XTLO VDD VSS AOUT 1 (+) VDD DASL1 DASL0 XCLK VSS VSS AOUT 1 (-) VDD LRCK BCK SIN MLSL ATT SHIFT LATCH WO MASL VSS CLR TEST VDD VSS AOUT 2 (-) VDD CXD2559Q +5V POWER SUPPLY FOR THE XTAL OSCILLATOR CIRCUITA B +5V POWER SUPPLY FOR AOUT1 C +5V POWER SUPPLY FOR AOUT2 D +5V DIGITAL POWER SUPPLY ANALOG GND DIGITAL GND

4558 IS USED FOR OPERATIONAL AMPLIFIER

NOTE: Application circuits shown are typical examples illustrating the oper- ation of the devices. Sony cannot as- sume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.