HI2555 INTERSIL | Alldatasheet

Document overview

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Technical content

Features

  • Two-Channel AD/DA Converters and Their Respective Digital Filters for Decimation and Oversampling Into a Single Chip
  • Peripheral Analog Circuits for AD Converter Greatly Reduces External Elements
  • Distortion (Typ)
  • S / N R a t i o ( T y p )

Description

The HI2555, CXD2555 is a 1-bit stereo AD/DA converter featuring a 2nd-order DA system noise shaper. This LSI has also built-in digital filters and provides good cost performance. Functions

  • Data Can Be Input/Output at Rate of 1 x f S with a Built- In Digital Filter
  • Simple Connection of Multiple HI2555, CXD2555s Enable Multi-Channel System
  • The 32-Slot Serial Data Interface Enables Independent Selection of Data Frontward Packing/Rearward Packing and MSB First/LSB First
  • The Master Clock is Applicable to Four Sources
  • 256f S, 512fS, 768fS, and 1024fS
  • The Sampling Frequency May be Adjusted to Low f S Frequencies Such as 16kHz or 8kHz, in Addition to Normal Ones of 48kHz, 44.1kHz, and 32Hz
  • Various Frequency Divider Clocks Can Be Output for LSIs Chips Connected Pinout HI2555, CXD2555 (48 LEAD MQFP) TOP VIEW

Ordering Information

TEMP. RANGE (oC) PACKAGE PKG. NO. HI2555JCQ -20 to 75 48 Ld MPQF Q48.12x12-S CXD2555Q -20 to 75 48 Ld MPQF Q48.12x12-S 2423222120191817 1213 14 15 16 373839404142434445464748 XSL2 XSL1 XSL0 MLSL MASL DV SS SOUT SIN BCK LRCK MS DV DD AVDD3 AOUT1- AVSS3 UCLK XCLK XTLO XVSS AVSS4 AOUT2- AVDD4 XVDD XTLI AOUT1+ AVSS3 AVSS1 AIN1 AVDD1 NC NC DVDD WO DASL1 DASL0 SUB AOUT2+ AVSS4 AVSS2 AIN2 AVDD2 NC SUB NC DVSS XMCK2 TEST CLR CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved File Number 4121.1 NOT RECOMMENDED FOR NEW DESIGNS

AOUT1(-) AOUT1(+) AOUT2(-) AOUT2(+) ADC2 MAF1 MAF2 DAC1 DAC2 ROM RAM MLSL MASL DIGITAL FILTER (OVER SAMPLING DECIMATION) SOUT LRCK BCK SIN CLOCK GENERATOR/TIMING CIRCUIT XSL2 XSL1 XSL0 XTL0 XTL1 XCLK UCLK ADC1 S → P S ← P Pin Descriptions PIN NO. SYMBOL I/O DESCRIPTION 1A V DD 3 - Analog power supply for Channel-1 DA converter.

2 AOUT1(–) O Analog opposite-phase output of Channel-1 DA converter

3A V SS 3 - Analog GND for Channel-1 DA converter. 4 UCLK O Outputs a 1/2 frequency divider of the clock input form the oscillator pin XTLI (Pin 7). User clock output for externally connected ICs. 5 XCLK O 256 f S clock output. this provides the master clock for ICs operating in the slave mode when multiple CXD255Qs are connected. (When XSL2 = Low) 6X V DD - Digital power supply for the master clock. 7 XTLI I Crystal oscillator circuit input. Connects the crystal oscillator selected by the crystal selection pins XSLO to 2 (Pins 34, 35, and 36). Used to input the master clock from external. 8 XTLO O Crystal oscillator circuit output. Connects the crystal oscillator selected by the crystal selection pins XSLO to 2 (Pins 34, 35, and 36). 9X V SS - Digital GND for the master clock. 10 AV SS 4 - Analog GND for Channel-2 DA converter. 11 AOUT2(-) O Analog opposite-phase output for Channel-2 DA converter. 12 AV DD 4 - Analog power supply for Channel-2 DA converter. 12 AOUT2 (+) O Analog in-phase output for Channel-2 DA converter. 14 AV SS 4 - Analog GND for Channel-2 DA converter. 15 AV SS 2 - Analog GND for Channel-2 AD converter. 16 AIN2 I Analog input for Channel-2 AD converter. HI2555, CXD2555

17 AV DD 2 - Analog power supply for Channel-2 AD converter.

18 NC -

19 SUB - Connected to the IC internal circuit board (same electric potential as power supply). Connect to GND on the printed circuit board via a capacitor.

20 NC -

21 DV SS - Digital GND. 22 XMCK2 O IC measurement. Low is output normally. 23 TEST I Test pin. Normally fixed to Low. Equipped with a pull-down resistor. 24 CLR I System clear input. Normally High; cleared when Low. Equipped with a pull-up resistor. 25 DV DD - Digital power supply. 26 MS I Master/slave mode switching input. Master mode when High; slave mode when Low. Equipped with a pull-up resistor. 27 LRCK I/O Serial I/O sampling frequency clock. Output i master mode (Pin 26 = High); input in slave mode (Pin 26 = Low). Transfers Channel-1 data when high, and Channel-2 data when Low. 28 BCK I/O Serial bit transfer clock (64 f S) for serial input data SIN and serial output data SOUT. Output in master mode (Pin 26 = High); input in slave mode (Pin 26 = Low). Serial input data is re- trieved at the rising edge; serial output data is transferred at the falling edge. 29 SIN I Two channels per sampling serial data input. Data format is represented by 2’s complements, and consists of 32-bit slots. 30 SOUT O Two channels per sampling serial data input. Data format is represented by 2’s complements, and consists of 32-bit slots. 31 DV SS - Digital GND. 32 MASL I Selects whether 16-bit serial data is place din the first 16-bit or the second 16-bit slots of the serial I/O 32-bit slots. Forward packing when High; rearward packing when Low. 33 MLSL I Selects whether 16-bit serial data is input/output at LSB-first or MSB-first. MSB-first when High; LSB-first when Low. 34 XSL0 I Crystal selection. Selects the clock frequency to be input from XTLI (Pin 7) using three bits, XSL 0 to 2. 35 XSL1 I Crystal selection. Selects the clock frequency to be input from XTLI (Pin 7) using three bits, XSL 0 to 2. 36 XSL2 I Crystal selection. Selects the clock frequency to be input from XTLI (Pin 7) using three bits, XSL 0 to 2. 37 DASL0 I IC measurement. Normally fixed to High. 38 DASL1 I IC measurement. Normally fixed to Low. 39 WO I Synchronization window open input. Window masked when High; window open when Low (forced synchronization). Equipped with a pull-up resistor. 40 DV DD - Digital power supply

41 NC -

42 NC -

43 SUB - Connected to the IC internal circuit board (same electric potential as power supply). Connect to GND on the printed circuit board via a capacitor. 44 AV DD 1 - Analog power supply for Channel-1 AD converter. 45 AIN1 I Analog input for Channel-1 AD converter. 46 AV SS 1 - Analog GND for Channel-1 AD converter. 47 AV SS 3 - Analog GND for Channel-1 DA converter. 48 AOUT1(+) O Analog in-phase output for Channel-1 DA converter. Pin Descriptions (Continued) PIN NO. SYMBOL I/O DESCRIPTION HI2555, CXD2555

Absolute Maximum Ratings TA = 25oC Thermal Information Recommended Operating Conditions ITEM MIN TYP MAX ITEM MIN TYP MAX NOTES: 1. The analog power supplies for AD converters (Pins 17 and 44) must be turned on simultaneously with or before other power supp lies. turning on these power supplies after any other power supply may cause the device to fall into latch-up condition. This precaut ion, how- ever, does not apply when turning off the power supplies. 2. Although the device can operate with low fS frequencies such as fS = 8kHz or 16kHz, its analog characteristics deteriorate to extent. When used at only these low frequencies, the CXD2570Q is recommended that is pin-compatible with the CXD2555Q. CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not i mplied. AVSS 1 = AVSS 2 = AVSS 3 = AVSS 4 = XVSS = DVSS = 0V, TA = -20oC to 75oC) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS APPLICABLE PIN Input Voltage V IHC 0.7 VDD - - V (Note 4) VILC -- 0 . 3 V DD VIN Analog Input V SS -V DD V (Note 5) Output Voltage V OH1 IOH = -2mA V DD -0.5 - 0.4 V (Note 6) VOL1 IOL = 4mA 0 - 0.4 VOH2 IOH = -4mA V DD -0.5 - V DD V (Note 7) VOL2 IOL = 4mA 0 - 0.4 VOH3 IOH = 12mA V DD/2 - V V (Note 8) VOL3 IOL = 16mA 0 - V DD/2 VOH4 IOH = -2mA V DD -0.8 - V DD V (Note 9) VOL4 IOL = 4mA 0 - 0.4 Input Leakage Current I L11 -10 - 10 µA( N o t e 1 0 ) IL12 -40 - 40 µA( N o t e 1 1 ) IL13 -20 -50 -120 µA( N o t e 1 2 ) IL14 20 50 120 µA( N o t e 1 3 ) Output Leakage Current I LZ -40 - 40 µA( N o t e 1 4 ) Feedback Resistance R FB VIN = VSS or VDD 250k 1M 2.5M Ω (Note 15) Supply Current I DD (Note 3) - 57 75 mA NOTES: 3. This includes current consumption at load resistance (R L = 3.9kΩ). 4. When all input pins except AIN1 and AIN2, and bi-directional pins (BCK, LRCK) are input. 5. AIN1 and AIN2. 6. XCLK, XMCK2, and SOUT. 7. AOUT1 (+), AOUT 1 (-), AOUT2 (+), AOUT2 (-), and UCLK. 8. XTLO. 9. When bi-directional pins (BCK, LRCK) are output. 10. All input pins except AIN1 and AIN2. 11. When bi-directional pins (BCK, LRCK) are input. 12. MS, WO, and CLR. 13. TEST. 14. SOUT, AOUT1 (+), AOUT1 (-), AOUT2 (+), AOUT2 (-), and UCLK. 15. Resistance between XTLO and XTLI. HI2555, CXD2555

AVSS 1 = AVSS 2 = AVSS 3 = AVSS 4 = XVSS = DVSS = 0V, TA = -20oC to 75oC PARAMETER SYMBOL TEST CONDITIONS MIN MAX UNITS SIN Setup Time tsus 10 - ns SIN Hold Time ths 15 - ns LRCK Setup Time tsul Slave Mode 10 - ns LRCK Hold Time thl Slave Mode 15 - ns LRCK Delay Time tdl Master Mode C L = 130pF -40 30 ns SOUT Delay Time tds C L = 60pF 9 65 ns SOUT Data Reset Time tzd 7 42 ns SOUT Data Erase Time tdz 6 40 ns XTLI Pulse Width twl f S = 48kHz, 256fS (XSL0 = XSL1 = XSL2 = L) 40 60 ns Analog Specifications AVDD1 = AVDD 2 = AVDD 3 = AVDD 4 = XVDD = 5.0V ± 10%, AVSS 1 = AVSS 2 = AVSS 3 = AVSS 4 = XVSS = DVSS = 0V, TA = -20oC to 75oC PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Overall Characteristics of ADC + DAC Connection: The following conditions apply unless otherwise specified: Input waveform = 1kHz sine wave, 1.4VRMS (= 0dB) XTAI = 33.8688MHz (= 768fS, fS = 44.1kHz) CLR = MS = WO = Open (= 5V) SOUT and SIN directly coupled S/N A-Weighting Filter 80 86 - dB THD + N 20kHz LPF - 0.010 0.018 % Dynamic Range 1kHz, - 60dB, 20kHz LPF 80 85 - dB Channel Separation 20kHz, 0dB - 96 - dB Gain Difference Between Channels - 0.1 - dB Gain R L = 3.9kΩ -3 0 +3 dB Input Level R IN = 0Ω -0 . 2 8 6-V RMS RIN = 4.7kΩ -1 . 4- V RMS DC Offset (ADC Output) - 069F - Hex ADC Input Impedance - 1.2 - k Ω Analog Specifications AVDD1 = AVDD 2 = AVDD 3 = AVDD 4 = XVDD = 5.0V ± 10%, AVSS 1 = AVSS 2 = AVSS 3 = AVSS 4 = XVSS = DVSS = 0V, TA = -20oC to 75oC PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DAC Specifications in Single Unit: The following conditions apply unless otherwise specified: Input data = 1kHz sine wave,full scale (= 0dB), XTAI = 33.8688MHz (= 768f S, fS = 44.1kHz), CLR = MS = WO = Open (= 5V), MS = GND S/N A-Weighting Filter 92 96 - dB THD + N 20kHz LPF - 0.008 0.012 % Dynamic Range 1kHz, - 60dB, 20kHz LPF 85 89 - dB Channel Separation 20kHz, 0dB - 100 - dB Gain Difference Between Channels - 0.05 - dB Output Level R L = 3.9kΩ 1.80 1.93 2.10 V RMS HI2555, CXD2555

(Related Pins) LRCK, BCK, SOUT, SIN, MASL, MLSL The serial data format is common for both SIN (DA converter input) and SOUT (AD converter output), consisting of two channels per sampling serial data represented by 2’s com- plement. Each channel is divided into 32-bit slots, of which 16 bits are handled as data. MASL is used to select whether the 16 bits of valid data is placed in the first or the second half of the 32-bit slots. Similarly, MLSL is used to select whether the serial data is arranged at LSB first or MSB first. Timing Diagram FIGURE 36. SOUT BCK SIN LRCK (SLAVE MODE) BCK LRCK (MASTER MODE) XTLI tzd tds tdz thstsus thl tsul tdl twl TABLE 1. MASL HF o r w a r d P a c k i n g L Rearward Packing TABLE 2. MLSL H MSB first L LSB first TABLE 2. MLSL HI2555, CXD2555

FIGURE 39. 10µF 10µF 100K AIN CXD2555Q RIN VIN + TABLE 5. XSL2 XSL1 XSL0 CRYSTAL OSCILLATOR FREQUENCY (NOTE 16) XCLK UCLK FREQUENCY DIVISION RATIO RELATIVE TO NORMAL fS FREQUENCY EXAMPLE OF 32kHz NORMAL FREQUENCY HLL 5 1 2 f S 512fS 256fS 1/2 f S = 16kHz H L H 1024f S 1024fS 512fS 1/4 f S = 8kHz H H L 1024f S 512fS 512fS 1/2 f S = 16kHz H H H 2048f S 1024fS 1024fS 1/4 f S = 8kHz NOTE: 16. When the normal frequency is assumed to be 32kHz, its derived frequency is 16kHz when divided by 2, or 8kHz when divided by 4. When divided in the same way, the low-f S frequencies for 44.1kHz are 22.05kHz and 11.025kHz, and for 48kHz, they are 24kHz and 12kHz.

HI2555, CXD2555 Serial Data Interface Timing

HI2555, CXD2555 Application Circuit Master Mode (MS = High)