CXA2064

CXA2064M SONY | Alldatasheet

Document overview

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• PDF pages: 21

Technical content

Features

• Adjustment free of VCO and filter.
• Audio multiplexing decoder and dbx noise reduction decoder are all included in a single chip. Almost any sort of signal processing is possible through this IC.
• Various built-in filter circuits greatly reduce external parts.
• This IC is near pin to pin compatible with the CXA2020M.

Applications

TV, VCR and other decoding systems for US audio multiplexing TV broadcasting Structure Bipolar silicon monolithic IC Absolute Maximum Ratings(Ta = 25°C)

• Supply voltage V CC 11 V
• Operating temperature Topr –20 to +75 °C
• Storage temperature Tstg –65 to +150 °C
• Allowable power dissipation PD 1000 mW
• STID, SAPID drive current IO 2 (max.) mA Range of Operating Supply Voltage 9 ± 0.5 V * This device is available only to the licensees of the dbx-TV noise reduction system. – 1 – E98513-PS Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. CXA2064M 30 pin SOP (Plastic) Standard I/O Level
• Input level COMPIN (Pin 7) 100mVrms (MONO 100Hz 100% mod.)
• Output level TVOUT-L/R (Pins 23 and 22) 490mVrms (MONO 100Hz 100% mod.) Pin Configuration (Top View) STIN 2 3 4 5 6 7 8 9 10 11 12 13 14 151 161718192021222324252627282930 SUBOUT NOISETC V CC IREF GND COMPIN SAPTC VGR PLINT STID SAPID PCINT2 PCINT1 MAINOUT VE VEWGT SAPOUT SAPIN VETC VEOUT VCAIN TVOUT-LTVOUT-RVCATC VCAWGT MUTE M1 FOMO MAININ

– 2 – CXA2064M Block Diagram 9 5 IR EF 1112 D ETEC TIO N M O D E_D ISPLAY N O ISE D ET SAPVC O STIN D SAPIN D BPF LPF LPF D eEm LPF LPF 1/21/4VC OLFLT FLT LPF LPF R M SD ET VC AVED eEm AM P (+4dB) SW H PF M ATR IX R M SD ET 101314 15 16 17 18 19 20 21 2425262728 29301 C O M PIN VC C G N D N O ISETC SAPTC VGR IREF SAPID STID FOMO MUTE SAPOUT SAPIN STIN VE VEWGT VETC VEOUT VCAIN VCAWGT VCATC TVO U T-L TVO U T-R MAININ MAINOUT SUBOUT PLINT PCINT2 PCINT1 +6dB

– 3 – CXA2064M Pin Description (Ta = 25°C, VCC = 9V) Pin No. Symbol Pin voltage Equivalent circuit Description VCC SUBOUT STIN NOISETC 4.0V 4.0V 3.0V Supply voltage pin. (L–R) signal output pin. Input the (L-R) signal from SUBOUT (Pin 2). Set the time constant for the noise detection circuit. (Connect a 4.7µF capacitor between this pin and GND.) SAPIN 4.0V Input the (SAP) signal from SAPOUT (Pin 28).27 3 4 12k 4k 147 580 580 Vcc 23k 147 18k 20k 11.7k 23k 147 18k VC C 271 3k3k 3.3k Vcc × 2 10k 1k 2k Vcc 200k

– 4 – CXA2064M Pin No. Symbol Pin voltage Eqivalent circuit Description COMPIN IREF GND 4.0V 1.3V Audio multiplexing signal input pin. Set the filter and VCO reference current. (Connect a 68kΩ (±1%) resistor between this pin and GND.) Analog block GND. Set the time constant for the SAP carrier detection circuit. (Connect a 4.7µF capacitor between this pin and GND.) SAPTC 4.5V8 VC C 24k 50k 147 24k 24k 10k VC C ↓ 50µ VC C 40k 40k 30k 30p 1.8k 16k 6.3k 147 34k 15k 30k VC C × 2 VC C

– 5 – Pin No. Symbol Pin voltage Eqivalent circuit Description PLINT 5.1V Pilot cancel circuit loop filter integrating pin. (Connect a 1µF capacitor between this pin and GND.) VC C 147 20k 26µ 20k 10k20k ↓ 50µ 20k20k 1010 STID — Stereo detection pin. Open collector output. Drive current is 2mA (Max.). SAPID — SAP detection pin. Open collector output. Drive current is 2mA (Max.). 68k 10.5k 15k VGR 1.3V Band gap reference output pin. (Connect a 10µF capacitor between this pin and GND.) × 4 11k 9.7k 19.4k 2.06k 3k 147 VC C 11k 11k

– 6 – CXA2064M VC C 147 10k 47k VC C Pin No. Symbol Pin voltage Eqivalent circuit Description MAININ 4.0V Input the (L + R) signal from MAINOUT (Pin 15).16 MAINOUT 4.0V (L + R) signal output pin. VC C 147 15k 200µ VC C × 4 1515 FOMO — Mode control switch pin. This pin has 3 ranges for input voltage. Sets forced monoral mode and also control ST.ID. MUTE — Mode control switch pin. When this pin is set to H level, TVOUT output is muted. 50k 70k 10.5k PCINT1 PCINT2 4.0V 4.0V Stereo block PLL loop filter integrating pin. 22k VC C 30k 147 VC C × 2 10k 10k 147

– 7 – CXA2064M Pin No. Symbol Pin voltage Eqivalent circuit Description VCATC 1.7V Determine the restoration time constant of the VCA control effective value detection circuit. (the specified restoration time constant can be obtained by connecting a 10µF capacitor between this pin and GND.) 50µ VC C 4k 20k × 4 × 4 7.5µ TVOUT-R 4.0V TVOUT right channel output pin.22 TVOUT-L 4.0V TVOUT left channel output pin.23 580 580 VC C VCAWGT 4.0V Weight the VCA control effective value detection circuit. (Connect a 1µF capacitor and a 3.9kΩ resistor in series between this pin and GND.) VC C 30k 8k 36k 2.9V 580 580147 40k 40k 50µ M1 — Mode control switch pin. This pin has 3 ranges for input voltage. Stereo, BOTH, SAP selection are available. 10.5k 40k 24k VC C 25k

– 8 – CXA2064M Pin No. Symbol Pin voltage Eqivalent circuit Description VEOUT 4.0V Variable de-emphasis output pin. (Connect a 4.7µF non-polar capacitor between Pins 25 and 24.) Vcc 10k 580 580 VETC 1.7V Determine the restoration time constant of the variable de-rmphasis control effective value detection circuit. (the specified restoration time constant can be obtained by connecting a 3.3µF capacitor between this pin and GND.) 20k ↓ 7.5µ4k ↓ 50µ Vcc × 4 × 4 SAPOUT 4.0V SAP FM detector output pin.28 24k ↓ 10µ 580 Vcc 580 ↓ 50µ 10k 147 VCAIN 4.0V VCA input pin. Input the variable de-emphasis output signal from Pin 25 via a coupling capacitor. VC C 20k VC C 47k 47k

– 9 – CXA2064M Pin No. Symbol Pin voltage Eqivalent circuit Description VE 4.0V Variable de-emphasis integrating pin. (Connect a 2700pF capacitor and a 3.3kΩ resistor in series between this pin and GND.) 7.5k 147 VC C VEWGT 4.0V Weight the variable de-emphasis control effective value detection circuit. (Connect a 0.047µF capacitor and a 3kΩ resistor in series between this pin and GND.) Vcc 36k 2.9V580 147 580 8k 30k ↓ 8µ ↓ 50µ

– 10 – CXA2064M

Electrical Characteristics

(100% modulation level) (Ta = 25°C, V CC = 9V) Current consumption Main output level Main de-emphasis frequency characteristic Main LPF frequency characteristic Main distortion Main overload distortion Main S/N Sub output level Sub LPF frequency characteristic Sub distortion Sub overload distortion Sub S/N ST fi SAP Crosstalk Sub pilot leak Icc Vmain FCdeem FCmain THDm THDmmax SNmain Vsub FCsub THDsub THDsmax SNsub CTst PCsub MONO MONO MONO MONO MONO MONO ST ST ST ST ST SAP ST 440 –1.2 –3.0 225 –3.0 490 –1.0 0.1 0.15 275 –0.5 0.1 0.2 –27 540 1.0 1.0 0.5 0.5 325 1.0 1.0 2.0 –16 mA mVrms dB dB dB mVrms dB dB dB dB No signal Mono 1kHz 100% mod. Pre-em. ON Mono 5kHz 30% mod. Pre-em. ON Mono 12kHz 30% mod. Pre-em. ON Mono 1kHz 100% mod. Pre-em. ON Mono 1kHz 200% mod. Pre-em. ON Mono 1kHz, Pre-em. ON SUB (L-R) 1kHz, 100% mod., NR OFF SUB (L-R) 12kHz, 30% mod., NR OFF SUB (L-R) 1kHz, 100% mod., NR OFF SUB (L-R) 1kHz, 200% mod., NR OFF SUB (L-R) 1kHz, NR OFF SUB (L-R) 1kHz, 100% mod., NR ON, SAP Carrier (5f H ) PILOT (fH ) 0dB 20 log ('5k'/'1k') 20 log ('12k'/'1k') 20 log ('100%'/'0%') 20 log ('12k'/'1k') 20 log ('100%'/'0%') 20 log ('M1 = L'/ 'M1 = H') 0dB = 20mVrms 15kLPF 15kLPF 15kLPF 15kLPF 15kLPF 15kLPF 1kBPF f H BPF Main (L + R) (Pre-Emphasis: OFF) = 100mVrms SUB (L – R) (dbx-TV: OFF) = 200mVrms Pilot= 20mVrms SAP Carrier= 60mVrms f H = 15.734kHz No. Item Signal Mode Input pin Input signal Measurement conditions Filter Output pin Min. Typ. Max. Unit

– 11 – CXA2064M Stereo ON level Stereo ON/OFF hysteresis SAP output level SAP LPF frequency characteristic SAP distortion SAP S/N SAP fi ST Cross talk SAP ON level SAP ON/OFF hysteresis ST separation 1 L fi R ST separation 1 R fi L ST separation 2 L fi R ST separation 2 R fi L THst HYst Vsap FCsap THDsap SNsap CTsap THsap HYsap STLsep1 STRsep1 STLsep2 STRsep2 SAP SAP SAP SAP ST ST ST ST ST –9.0 2.0 130 –3.0 –12.0 2.0 –6.0 6.0 170 2.5 –9.0 4.0 –3.0 10.0 210 2.5 6.0 –6.5 6.0 dB dB mVrms dB dB dB dB dB dB dB dB dB SAP 1kHz 100% mod. NR OFF SAP 10kHz 30% mod . NR OFF SAP 1kHz 100% mod . NR OFF SAP 1kHz, NR OFF SAP 1kHz 100% mod. NR ON, Pilot (fH ) ST-L 300Hz 30% mod. NR ON ST-R 300Hz 30% mod. NR ON ST-L 3kHz 30% mod. NR ON ST-R 3kHz 30% mod. NR ON 0dB = 20mVrms 20 log (‘on level'/'off level') 20 log ('10k'/'1k') 20 log ('100%'/'0%') 20 log ('M1 = H'/ 'M1 = L') 0dB = 60mVrms 20 log (‘on level’/’off level’) 20 log ('Lch'/'Rch') 20 log ('Rch'/'Lch') 20 log ('Lch'/'Rch') 20 log ('Rch'/'Lch') 15kLPF 15kLPF 1kBPF 15kLPF 15kLPF 15kLPF 15kLPF No. Item Signal Mode Input pin Input signal Measurement conditions Filter Output pin Min. Typ. Max. Unit ST 7 Change PILOT (fH ) Level Change SAP Carrier (5fH ) Level 7SAP

– 12 – CXA2064M Electrical Characteristics Measurement Circuit R 7 3.9k 2.5V R 2 68k G N D C 5 10µ R 3 10k R 4 10k C 11 10µ TAN TA- LU M M ETAL ±1% C 7 5600p R 5 1M EG R 6 100k C 8 0.012µ C 14 4.7µC 17 0.047µ R 8 C 18 2700P R 9 3.3k C 15 3.3µ TAN TA- LU M 2 3 4 5 6 7 8 9 10 11 12 13 14 151

161718192021222324252627282930 STIN

4.7µ C 2 4.7µ C 3 4.7µR 1 10k C 1 4.7µ C 9 4.7µ C 16 4.7µ C 19 4.7µ ATTSG G N D S8 BU FF FILTER S 15kH z LPF fH BPF 1kH z BPF M EASU R ES C 12 4.7µ S1S2S3 C 13 4.7µ VC C C 10

– 13 – CXA2064M Adjustment Method 1.Input level adjustment 1) Connect components as shown in Fig. 1. 2) Set the US MPX encoder output to MONO 100Hz 100% modulation. 3) Adjust the "ATT" so that COMPIN (Pin 7) level goes to 100mVrms (±0.5dB). 2.Separation adjustment 1) Mode control pin are set to FOMO (Pin 17): L, M1 (Pin 18): L, MUTE (Pin 19): L. 2) Set the USMPX encoder ouput to Stereo Lch-only 300Hz 30% modulation, NR-ON. Then, adjust the variable resistor of SUBOUT (Pin 2) to reduce the TVOUT-R output to the minimum. 3) Next, set the frequency only of the input signal to 3kHz and adjust the variable resistor of VEWGT (Pin 29) to reduce the TVOUT-R output to the minimum. 4) The adjustments in 2 and 3 above are performed to optimize the separation. U S M PX encoder ATT C XA2064M 4.7µ C O M PIN (Pin 7) Fig. 1. Adjustment setup * Adjust this IC through Tuner and IF when this IC is mounted on the set.

– 14 – CXA2064M Description of Operation The US audio multiplexing system possesses the base band spectrum shown in Fig. 2. PEAK D EV kH z 25 25 L + R 50 – 15kH z L-R dbx-TV N R AM -D SB-SC SAP dbx-TV N R FM 10kH z 50 – 10kH z TELEM ETR Y FM 3kH z fH = 15.734kH z fH 2fH 3fH 4fH 5fH 6fH 6.5fH f PILOT (C O M PIN ) STER EO LPF PLL (VC O 8fH ) 2fH L0° fH L90° fH L0° ST.IDPILO T D ET PILO T C AN C EL M AIN LPF D E.EM (M AIN O U T) L + R 4.7µ (M AIN IN ) L-R (D SB) D ET IN J. LO C K SU B LPF (SU BO U T) 4.7µ N R SW dbx-TV BLO C K M ATR IX M O D E C O N TR O L (SAP IN ) 4.7µ SAP(FM ) D ET SAP LPFSAP BPF (SAP O U T) A B N O ISE D ET M O D E C O N TR O L SAP D ET SAP.ID (TVO U T-L) (TVO U T-R ) 2728 15 16 10k M O D E C O N TR O L (STIN ) N R SW FIXED D EEM PH ASIS VAR IABLE D EEM PH ASIS (VE O U T) (VC A IN ) to M ATR IX 4.7µ H PF LPF LPF R M S D ET R M S D ET VC A A B (ST IN ) (SAP IN ) 2425 Fig. 2. Base band spectrum Fig. 3. Overall block diagram (See Fig. 4 for the dbx-TV block) Fig 4. dbx-TV block

– 15 – CXA2064M (1) L + R (MAIN) When the audio multiplexing signal is inputted to COMPIN (Pin 7), the SAP signal and telemetry signal are suppressed by STEREO LPF. Next, the pilot signals are canceled. Finally, the L – R signal and SAP signal are removed by MAIN LPF, and frequency characteristics are flattened (de-emphasized) and input to the matrix. (2)L – R (SUB) The L – R signal follows the same course as L + R before the pilot signal is canceled. L – R has no carrier signal, as it is a suppressed-carrier double-sideband amplitude modulated signal (DSB-AM modulated). For this reason, the pilot signal is used to regenerate the carrier signal (quasi-sine wave) to be used for the demodulation of the L – R signal. In the last stage, the residual high frequency components are removed by SUB LPF and the L – R signal is input to the dbx-TV block via the NRSW circuit. (3)SAP SAP is an FM signal using 5f H as a carrier as shown in the Fig. 2. First, the SAP signal only is extracted using SAP BPF. Then, this is subjected to FM detection. Finally, residual high frequency components are removed and frequency characteristics flattened using SAP LPF, and the SAP signal is input to the dbx-TV block via the NRSW circuit. (4)Mode discrimination Stereo discrimination is performed by detecting the pilot signal amplitude. SAP discrimination is performed by detecting the 5f H carrier amplitude. NOISE discrimination is performed by detecting the noise near 25kHz after FM detection of SAP signal. (5)dbx-TV block Either the L – R signal or SAP signal input respectively from STIN (Pin 1) or SAPIN (Pin 27) is selected by the mode control and input to the dbx-TV block. The input signal then passes through the fixed de-emphasis circuit and is applied to the variable de- emphasis circuit. The signal output from the variable de-emphasis circuit passes through an external capacitor and is applied to VCA (voltage control amplifier). Finally, the VCA output is converted from a current to a voltage using an operational amplifier and then input to the matrix. The variable de-emphasis circuit transmittance and VCA gain are respectively controlled by Each of effective value detection circuits. Each of the effective value detection circuits passes the input signal through a predetermined filter for weighting before the effective value of the weighted signal is detected to provide the control signal. (6)Matrix The signals (L + R, L – R, SAP) input to “MATRIX” become the outputs for the ST-L, ST-R, MONO and SAP signals according to the mode control and whether there is ST / SAP discrimination. (7) Others “Bias” supplies the reference voltage and reference current to the other blocks. The current flowing to the resistor connecting IREF (Pin 5) with GND become the reference current.

– 16 – CXA2064M Decoder Output and Mode Control Table Input signal mode MONO STEREO MONO & SAP STEREO & SAP ID Pin dbx input Output ST SAP M1 FOMO H H L * MUTE MUTE MUTE L – R MUTE MUTE MUTE MUTE MUTE L – R MUTE MUTE MUTE SAP SAP SAP SAP L – R MUTE MUTE SAP SAP SAP SAP SAP SAP Lch Rch H H M * L + R L + R H H H * L + R L + R L H L L L + R L + R L H L M L R H H L H L + R L + R L H M L L + R L + R L H M M L + R L + R H H M H L + R L + R L H H L L + R L + R L H H M L R H H H H L + R L + R H L L * L + R L + R H L M * L + R L + R H L H L L + R SAP H L H M SAP SAP H L H H L + R SAP L L L L L + R SAP L L L M L R H L L H L + R L + R L L M L L + R L + R L L M M L + R SAP H L M H L + R SAP L L H L L + R SAP L L H M H L H H SAP SAP L + R SAP L + R SAP *: Don’t care Regarding ST, SAP, ID L shows that drive current runs through load register and pin voltage is low. H shows that drive current doesn't run through load resistor and pin voltage is high.

– 17 – CXA2064M H SAP 4.5V to VCC 2 to 3V (or OPEN) 0 to 0.5V 8.5V to V CC 3 to 7V 0 to 0.5V (or OPEN) 3V to V CC 0 to 0.5V (or OPEN) BOTH STEREO STID-H STID-L STID-L ON OFF M L H M L H L Limits of Control Voltage FOMO MUTE

– 18 – CXA2064M Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same. R 7 3.9k R 2 68k G N D C 5 10µ C 11 10µ TAN TA- LU M M ETAL ±1% C 7 5600p R 5 1M EG R 6 100k C 8 0.012µ C 14 4.7µC 17 0.047µ R 8 C 18 2700P R 9 3.3k C 15 3.3µ TAN TA- LU M 2 3 4 5 6 7 8 9 10 11 12 13 14 151 4.7µ C 2 4.7µ V1 C 3 4.7µ R 1 10k C 1 4.7µ C 9 4.7µ C 16 4.7µ C 12 4.7µ C 13 4.7µ VC C C 10 R 10 10k C O M P IN STID R 3 10k R 4 10k 3 to VC C SAPID M O D E C O N TR O L SWTVO U T-L TVO U T-R Application Circuit

– 19 – CXA2064M Input level vs. D istortion characteristics 1 (M O N O ) Distortion [% 1.0 0.1 –10 0 10 Input level vs. D istortion characteristics 2 (Stereo) Distortion [% 1.0 –10 0 10 Input level [dB] Input level vs. D istortion characteristics 3 (SA P) Distortion [% 1.0 –10 0 10 Input level [dB] Input level [dB] Input signal: M O N O (Pre-em phasis on), 1kH z 0dB = 100% m odulation level VC C = 9V, 30kH z using LPF M easurem ent point: TVO U T-L/R Standard level (100% ) Input signal: Stereo L = –R (dbx-TVN R O N ), 1kH z 0dB = 100% m odulation level VC C = 9V, 30kH z using LPF, ST m ode M easurem ent point: TVO U T-L/R Standard level (100% ) Standard level (100% ) Input signal: SAP (dbx-TVN R O N ) 1kH z, 0dB = 100% m odulation level VC C = 9V, 30kH z using LPF, SAP m ode M easurem ent point: TVO U T-L/R

– 20 – CXA2064M Frequency [kH z] Gain [dB] Stereo LPF frequency characteristics –10 0 20 40 60 80 100 –20 –50 1 2 5 10 20 507 70 100 –40 –30 –10 Gain (FC m ain and FC sub) [dB] Frequency [kH z] M ain LPF and Sub LPF frequency characteristics –20 20 40 60 80 100 120 –10 SA P frequency characteristics and group delay Group delay [µs] 100 5fH G ain G roup delay 3.8fH 6.2fH Frequency [kH z] Gain [dB]

– 21 – CXA2064M Package Outline Unit: mm 0.45 ± 0.1 1.27 7.6 – 0.1 + 0.3 10.3 ± 0.4 1630 18.8 – 0.1 + 0.4 0.2 M 0.1 0.2 – 0.05 + 0.1 0.5 ± 0.2 0.1 – 0.05 A(9.3) 2.3 – 0.15 + 0.4 30PIN SO P(PLASTIC ) SO N Y C O D E EIAJ C O D E JED EC C O D E SO P-30P-L03 SO P030-P-0375 PAC KAG E M ATER IAL LEAD TR EATM EN T LEAD M ATER IAL PAC KAG E M ASS EPO XY R ESIN SO LD ER PLATIN G C O PPER ALLO Y PAC KAG E STR U C TU R E 0.7g 0° to 10° + 0.2 D ETAIL A N O TE : PALLAD IU M PLATIN G This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Fram e).