CX74063-26

CX74063-26 SKYWORKS | Alldatasheet

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Skyworks Solutions, Inc., Proprietary and Confidential 1 103052A [781] 376-3000 I FAX [781] 376-3100 I SALES@SKYWO RKSINC.COM I WWW.SKYWORKSINC.COM MAY 16, 2003 DATA SHEET CX74063-26: RF Transceiver for Multi-Band GSM, GPRS, and EDGE Applications with Power Ramping Controller and Integrated Crystal Oscillator with 26 MHz Output

APPLICATIONS

• GSM850, EGSM900, DCS1800, and PCS1900 handsets
• GPRS handsets and modules
• EDGE downlink support

FEATURES

• Direct down-conversion receiver eliminates the external image reject/IF filters
• Three separate LNAs with single-ended inputs
• RF gain range: GSM = 20 dB, DCS = 22 dB, PCS = 20 dB. Baseband gain range = 100 dB
• Gain selectable in 2 dB steps
• Integrated receive baseband filters with tunable bandwidth
• Integrated DC offset correction sequencer
• Reduced filtering requirements with translational loop transmit architecture
• Integrated transmit VCOs
• Wide RF range for quad band operation
• Integrated PAC loop
• Single integrated, fully programmable fractional-N synthesizer suitable for multi-slot GPRS operation
• Fully integrated wideband Ultra High Frequency (UHF) VCO
• Integrated crystal oscillator
• Separate enable lines for power management transmit, receive, and synthesizer modes
• Supply voltage down to 2.6 V
• Band select and front-end enable states may be exercised on output pins to control external circuitry
• Low external component count
• Optional bypass of baseband filtering for use with high dynamic range Analog to Digital Converters (ADCs) for current savings
• Interfaces to low dynamic range ADC
• Meets AM suppression requirements without baseband interaction
• 56-pin RFLGA 8x8 mm package
• Low power standby mode

DESCRIPTION

The CX74063-26 transceiver is a highly integrated device for multi-band Global System for Mobile Communications™ (GSM™) or General Packet Radio Service (GPRS) applications. The device requires a minimal number of external components to complete a GSM radio subsystem. The CX74063-26 supports GSM850, EGSM900, DCS1800, and PCS1900 applications. The receiver also supports downlink Enhanced Data-Rate GSM Evolution (EDGE). The receive path implements a direct down-conversion architecture that eliminates the need for Intermediate Frequency (IF) components. The CX74063-26 receiver consists of three integrated Low Noise Amplifiers (LNAs), a quadrature demodulator, tunable receiver baseband filters, and a DC-offset correction sequencer. In the transmit path, the device consists of an In-phase and Quadrature (I/Q) modulator within a frequency translation loop designed to perform frequency up-conversion with high output spectral purity. This loop also contains a phase-frequency detector, charge pump, mixer, programmable dividers, and high power transmit Voltage Controlled Oscillators (VCOs) with no external tank required. With the integrated gain controller (and an integrator ), the device realizes the Power Amplifier Control (PAC) functionality when combined with a coupler, a Radio Frequency (RF) detector and a Power Amplifier (PA). The CX74063-26 also features an integrated, fully programmable, sigma-delta fractional-N synthesizer suitable for GPRS multi-slot operation. Except for the loop filter, the frequency synthesizer function, including a wideband VCO, is completely on-chip. The reference frequency for the synthesizer is supplied by the integrated crystal oscillator circuitry. The 56-pin 8x8 RF Land Grid Array (RFLGA™) device package and pin configuration are shown in Figure 1. A functional block diagram is shown in Figure 2. Signal pin assignments, functional pin descriptions, and equivalent circuitry are provided in Table 1.

Figure 1. CX74063-26 Pinout – 56-Pin RFLGA (8 x 8 mm) (Top View)

Figure 2. CX74063-26 Transceiver Block Diagram

Table 1. CX74063-26 Signal Descriptions (1 of 5)

1 RXENA Receiver enable input

2 TXENA Transmitter enable input

3 PCO Bi-directional band select

4 VCXO_EN VCXO enable pin

5 PDETVCC Bias for the RF Detector

6 VCC1 LNA and TX charge pump supply VCC1

7 TXCPO Translational loop charge pump output

8 TXINP Translational loop feedback input

9 LNA900IN Low band LNA input for GSM850,

10 GNDLNA900 Low band LNA emitter ground

Table 1. CX74063-26 Signal Descriptions (2 of 5)

11 LNA1800IN DCS LNA input

12 PDET Feedback Input to power control loop

13 LNA1900IN PCS LNA input

14 NC No connect No connect

15 NC No connect No connect

16 PAVAPC PA control output Vout

17 BBVAPC PA control Baseband input

18 TXIP TX I baseband input positive

19 TXIN TX I baseband input negative

20 TXQP TX Q baseband input positive

21 TXQN TX Q baseband input negative

22 TXFP TX IF filter output positive

23 TXFN TX IF filter output negative

Table 1. CX74063-26 Signal Descriptions (3 of 5)

24 VCC2 RX mixer and TX loop supply VCC2

25 CAPIP Capacitor filter I positive

26 CAPIN Capacitor filter I negative

27 CAPQP Capacitor f ilter Q positive

28 CAPQN Capacitor f ilter Q negative

29 LPFADJ LPF frequency setting resistor

30 XTALBUF Crystal oscillator buffer output

31 GNDD Synthesizer digital ground

32 VCCD Synthesizer digital supply VCCD

33 VCCF Synthesizer analog supply and crystal

34 XTAL Crystal input

35 GNDFN Synthesi zer analog ground

Table 1. CX74063-26 Signal Descriptions (4 of 5)

36 UHFCPO Synthesizer charge pump output

37 VCCFN_CP Synthesizer charge pump supply VCCFN_CP

38 SXENA Synthesizer enable input

39 XTALTUNE Crystal oscillator varactor control

40 DATA Serial bus data input

41 CLK Serial bus clock input

42 LE Serial bus latch enable input

43 VDDBB Digital CMOS supply VDDBB

44 UHFBYP Bypass capa citor for UHF VCO

45 UHFTUNE UHF VCO control input

46 VCCUHF UHF VCO supply VCCUHF

47 VCC3 LO chain supply VCC3

Table 1. CX74063-26 Signal Descriptions (5 of 5)

48 RXQN Receiver output Q negative

49 RXQP Receiver output Q positive

50 RXIN Receiver output I negative

51 RXIP Receiver output I positive

52 VCC4 Baseband supply VCC4

53 VCCTXVCO Transmit VCO supply VCCTXVCO

54 TX900 Low band transmit VCO

55 TX1800/TX1900 DCS and PCS transmit VCO output

56 TXVCOTUNE Transmit VCO control input

• Receive section . Includes three integrated LNAs, a quadrature demodulator section that performs direct down conversion, baseband amplifier circuitry with I/Q outputs, and three stages of DC offset correction. The receiver can be calibrated to optimize IP2 performance.
• Synthesizer section . Includes an integrated on-chip VCO locked by a fractional-N synthesizer loop, and a crystal oscillator to supply the reference frequency.
• Transmit section . The TX path is a translational loop architecture consisting of an I/Q modulator, integrated high power VCOs, offset mixer, programmable divider, PFD, and charge pump. The device also provides integrated gain controller for the PAC loop, plus the bias generator for an external diode detector. A 3-wire serial interface controls the transceiver and synthesizer. The receiver gain control, as well as the division ratios and charge pump currents in the synthesizer and transmitter, can be programmed using 24-bit words. These 24-bit words are programmed using the 3-wire input signals CLK, DATA, and LE. Pin 43 (VDDBB) is provided for the digital sections to allow power supply operation compatible with modern digital baseband devices. VDDBB is also used to supply registers 0 through 5 to maintain programmed values. The TXENA, RXENA, and SXENA signals separately enable the CX74063-26 transmitter, receiver, and synthesizer sections. TXENA and RXENA should be held low during programming. SXENA should be held high during the programming of register 3 (IP2 calibration). (These timing signals are detailed in Figures 9, 10, and 11.)

30 dB, selectable in 6 dB steps. output, the auxiliary gain stage, selectable at 0 dB or + 6 dB. The gain control ranges are shown in Figure 3. places the DC compensation circuitry in the track mode. end, and generates an interfering baseband signal. Table 2. Receive Pole Locations

Note 1. t T_H1, tT_H2, tT_H3, and tFEENA are programmed in Register 2. Figure 5. DC Offset Correction Timing (LNA On During Part of the DC Offset Correction Sequence) test requirements in all bands with good margin. signal applied for the purpose of the calibration are not critical. the LNA input, which applies to all three LNAs. with the appropriate IP2 coefficients for the band in use. must be re-programmed to the device again. adjustment for reference frequency errors.

• VCO
• High frequency prescaler
• N-divider with a sigma-delta modulator
• Reference buffer and divider
• Fast phase frequency detector and charge pump

• The reference divider value, from 1 to 15
• The N-divider value, in a manner similar to an integer-N synthesizer
• A fractional ratio The generated frequency is given by the following equation: R fFNN f ref VCO  ++ 222 5.3 where: f VCO = Generated VCO frequency N = N-divider ratio integer part FN = Fractional setting R = R-divider ratio f REF = Reference frequency UHF VCO Frequency Setting For the receiver, to tune the receive frequency, fRX, set the VCO frequency, fVCO, as follows:
• RXVCO f2 3f = for GSM850/900
• RXVCO f4 3f = for DCS1800 and PCS1900 For the transmitter VCO frequency, refer to the equations shown in Figure 6. Digital Frequency Centering The CX74063-26 uses a novel technique whereby the UHF VCO frequency range is re-centered each time the synthesizer is programmed. This technique is called Digital Frequency Centering (DFC). The DFC technique:
• Extends the VCO frequency coverage
• Speeds up settling time
• Ensures robust performance since the VCO is always operated at the center of its tuning range. Each time the synthesizer is programmed, the DFC circuit is activated, and the VCO is centered to the programmed frequency in less than 20 µs. After this, normal Phase Locked Loop (PLL) operation is resumed and the fine settling of the frequency is finalized. The DFC typically adjusts the VCO center frequency to within a few MHz and no more than 5 MHz offset, and presets the tuning voltage to the center of the range before the PLL takes over. This speeds up frequency settling and ensures that the PLL control voltage never operates close to the rails. 101514D 6_071101 900 X2Tx Q where: fTx = fLO (2 D1 - D2)/D1 GSM:fLO = (fVCO)/3 DCS/PCS: fLO = (2fVCO)/3 Tx I Phase Detect Tx VCO Ext Loop Filter fTx ÷3Fractional-N PLL UHF VCO fVCO L/C Filter Ext

Figure 6. Transmitter Frequency Generation

Skyworks Solutions, Inc., Proprietary and Confidential 13 103052A [781] 376-3000 I FAX [781] 376-3100 I SALES@SKYWO RKSINC.COM I WWW.SKYWORKSINC.COM MAY 16, 2003 The DFC is an adaptive circuit that corrects for any VCO center frequency errors caused by variations of the integrated VCO circuit, temperature, supply voltage, aging etc. The VCO can be centered at any frequency in the range from 1.2 GHz to 1.55 GHz. Once centered, the VCO has a minimum analog tuning range of 30 MHz. No calibration or data storage is needed for DFC operation. It is activated by one of two events:

• When the synthesizer is programmed, the rising edge of the LE signal starts the DFC cycle and,
• When changing the level of the SXENA signal from low to high, thereby turning on the synthesizer, the rising edge of the SXENA signal starts the DFC cycle. Crystal Oscillator A crystal oscillator is designed to provide the reference frequency for the synthesizer. As shown in Figure 7, the oscillator uses an external crystal to generate an accurate oscillation frequency. The reference frequency can be changed through coarse tuning with an integrated capacitor array or fine tuning with the integrated varactor diode. The coarse tuning is done by switching in and out (using a digital word programmed via the serial interface) the capacitor network (CAP_A and CAP_B) located at the input of the integrated buffer. The fine tuning is done by providing a tuning voltage to the integrated varactor diode. Table 20 describes the control bits. An output buffer is provided to drive the baseband circuitry (XTALBUF, pin 30). The VCXO and buffer circuitry are powered from pin 33 (VCCF). When VCCF is ramped to a voltage greater than 2.6 V, the output buffer powers on. The oscillator core powers up when pin 4 (VCXO_EN) is set to logic 1. If pin 4 is tied permanently to logic 1, the R6 VCXO Control Register is set to a defined state by a power-on reset. Pin 4 should be held low if an external reference oscillator is used. The buffer may be disabled by programming bit 3 in the SX1 Control Register (see Table 13) to logic 0. Transmit Section To minimize the post-PA filtering requirements and any additional post-PA losses, the transmit path consists of a vector modulator within a frequency translation loop. The translation loop consists of the following:
• Phase Frequency Detector (PFD) and charge pump
• Mixer with an operating range of 800 MHz to 2 GHz
• An in-loop modulator
• Two programmable dividers
• Two transmit VCOs Translational Loop The translational loop takes baseband analog I/Q signals and modulates them with the mixed product of transmitter output and LO signal, as shown in Figure 6. The unmodulated result is compared with a divided down LO at the PFD and the difference is used to control the transmit VCO. The on-chip Low Pass Filter (LPF) following the mixer attenuates the unwanted sidebands as well as harmonics. Transmit VCOs Two on-chip transmit VCOs are designed to meet GSM850, EGSM900, DCS1800, and PCS1900 requirements. The transmit VCOs use the same DFC technique as described in the Synthesizer section to lock the translational loop. The rising edge on TXENA initializes the transmit DFC. Power Amplifier Gain Controller The device contains an error amplifier/integrator to provide transmit burst control for an external power amplifier (PA). As shown in Figure 8, when the device is connected to a PA, an RF detector, and a coupler, a loop is formed that controls the transmit power in a multi-band wireless application. The error amplifier amplifies and integrates the voltage difference between the RF detector output (PDET) and the power control input (BBVAPC). The output of the integrator is fed to an internal gain shaper that drives the gain control input (PAVAPC) of the external RF PA. The device. provides a bandgap voltage (PDETVCC) which can be used as the supply voltage for the external peak detector and can source up to 200 µA. The PA pre-bias is activated after a programmable delay and time-referenced from the rising edge of TXENA. The time delay is set using the serial interface. See Table 19 for details. Digital Interface The transceiver and synthesizer are controlled by a single three-wire serial interface. The transmitter, receiver, and synthesizer are each enabled through external inputs according to typical timing requirements as shown in Figures 10 and 11. Band selection for the CX74063-26 is through the three-wire serial interface. The PCO signal (pin 3) provides a band selection control output. DC offset calibration and front-end activation timing can also be controlled by an on-chip signal sequencer, precluding the need for separate control signals. All the logic and the three-wire interface inputs are referenced to the PCO signal (pin 3). The RX/TX Control Register is used to program the transceiver and to preset other test word states by setting bit 22 as a logic 1. If any test words are to be altered from their preset states, bit 22 must be sent to the RX/TX Control Register again as a logic 0. Typically, this is done only on power-up since the device has a zero-power standby mode that retains programmed test memory. There are seven additional registers used to program various functions of the CX74063-26. The SX1 Control Register is used to program the fractional-N synthesizer and the SX2 Fractional-N Modulo Register is used to program the modulus. Three auxiliary registers are used to program the transceiver besides the RX/TX Control Register, and two 24-bit registers are used to program the synthesizer:
• SX1 Control
• SX2 Fractional-N Modulo
• RX/TX Control
• R0 Auxiliary Control

Figure 8. PA Controller Block Diagram Table 3. CX74063-26 Absolute Maximum Ratings maximum rating conditions for extended periods may reduce device reliability. Table 4. CX74063-26 Recommende d Operating Conditions

Table 5. Power Consumption Specifications

Table 6. CX74063-26 Electrical Specification s – EGSM/GSM850 Receiver (1 of 3)

Table 6. CX74063-26 Electrical Specification s – EGSM/GSM850 Receiver (2 of 3)

Table 6. CX74063-26 Electrical Specification s – EGSM/GSM850 Receiver (3 of 3) Note 1 : Gain codes refer to LNA/Mixer /LPF1/VGA1/AUX/VGA2 gains in dB. Table 7. CX74063-26 Electrical Specificat ions – DCS1800 Receiver (1 of 3)

Table 7. CX74063-26 Electrical Specificat ions – DCS1800 Receiver (2 of 3)

Table 7. CX74063-26 Electrical Specificat ions – DCS1800 Receiver (3 of 3) Note 1: Gain codes refer to LNA/Mixer /LPF1/VGA1/AUX/VGA2 gains in dB.

Table 8. CX74063-26 Electrical Specificat ions – PCS1900 Receiver (1 of 3)

Table 8. CX74063-26 Electrical Specificat ions – PCS1900 Receiver (2 of 3)

Table 8. CX74063-26 Electrical Specificat ions – PCS1900 Receiver (3 of 3) Note 1: Gain codes refer to LNA/Mixer /LPF1/VGA1/AUX/VGA2 gains in dB. Table 9. CX74063-26 Electrical Specific ations – Transmitter (1 of 4)

Table 9. CX74063-26 Electrical Specific ations – Transmitter (2 of 4)

Table 9. CX74063-26 Electrical Specific ations – Transmitter (3 of 4)

1.9 V > VCTL)

820 MHz < fC < 850

870 MHz < fC < 915

1.9 V > VCTL

1710 MHz < fC <

1785 MHz

1850 MHz < fC <

1910 MHz

Table 9. CX74063-26 Electrical Specific ations – Transmitter (4 of 4)

Table 10. CX74063-26 Electrical Specifications – Synthesizer (1 of 3)

Table 10. CX74063-26 Electrical Specifications – Synthesizer (2 of 3)

1200 MHz < fC <

1300 MHz

1300 MHz < fC <

1400 MHz

1400 MHz < fC <

1475 MHz

1475 MHz < fC <

1550 MHz

26 MHz Crystal Oscillator

Table 10. CX74063-26 Electrical Specifications – Synthesizer (3 of 3)

26 MHz Crystal Oscillator (continued)

Note 1 : Using a crystal with equi valent 6 mH inductor and ESR ≤ 100 Ω. Table 11. CX74063-26 Electrical Specif ications – Digital Interface

Table 12. Control and Output States Table 13. SX1 Control Register (S ynthesizer Control Functions)

Table 14. SX2 Fractional-N Modulo Register Table 15. RX/TX Control Register (1 of 2)

Table 15. RX/TX Control Register (2 of 2) with PREENA = 0 and then program any or all of R0 to R5. VDDBB (pin 43) is supplied with power.

Table 16. R0 Auxiliary Control Register

Table 17. R2 DC Offset Timing Register Note 1 : See Figure 3 and Figure 4. Table 18. R3 IP2 Calibration Register

Table 19. R4 PAC Timing Control Register PAC_TIME PAC timing control [19:12] Bit [ 19:12] sets timing for the PAC pedestal. When all bits = 0, no pedestal. Table 20. R6 VCXO Control Register CAP_A Bit [11:7] capacitor A arra y control. Binary weighted. CAP_B Bit [15:12] capacitor B arra y control. Binary weighted. Note: Programmed values in this register are not maintained with VDDBB (pin 43).

Table 21. R7 VCXO Control Register Note: Programmed values in this register are not maintained with VDDBB (pin 43). Figure 9. Serial Data Input Ti ming Diagram For Transceiver

Table 22. Recommended EGSM900/GS M850 AGC Data (1 of 2)

Table 22. Recommended EGSM900/GS M850 AGC Data (2 of 2)

Table 23. Recommended DCS1800 AGC Data (1 of 2)

Table 23. Recommended DCS1800 AGC Data (2 of 2)

Table 24. Recommended PCS1900 AGC Data (1 of 2)

Table 24. Recommended PCS1900 AGC Data (2 of 2) Figure 12. Typical Baseba nd Frequency Response

Figure 13. Typical Differential Delay Response Table 25. EGSM900/GSM850 LN A S11 (Normalized to 50 Ω)

Table 26. DCS1800 LNA S11 (Normalized to 50 Ω) Table 27. PCS1900 LNA S11 (Normalized to 50 Ω)

Table 28. Typical EGSM and GSM850 Band Noise Figure vs. Gain Data Figure 14. Typical EGSM and GSM850 Band Noise Figure vs. V oltage Gain Curve

Table 29. Typical EGSM and GSM 850 Band Dynamic Range Data (I ncludes 4.0 dB Front End Loss) Figure 15. Typical EGSM and GSM850 Band Dy namic Range vs. An tenna Input Curve

Table 30. Typical DCS1800 Band Noise Figure vs. Gain Data Figure 16. Typical DCS1800 Band Noise Figure vs. Voltage Gain Curve

Table 31. Typical DCS1800 Band Dynamic Range Data (Includes 4.2 dB Front End Loss) Figure 17. Typical DCS1800 Band Dynamic Range vs. Antenna Input Curve

Table 32. Typical PCS1900 Band Noise Figure vs. Gain Data Figure 18. Typical PCS1900 Band Noise Figure vs. Voltage Gain Curve

Table 33. Typical PCS1900 Band Dynamic Range Data (Includes 4.2 dB Front End Loss) Figure 19. Typical PCS1900 Band Dynamic Range vs. Antenna Input Curve

2 IN OUT

Figure 27. Typical CX74063-26 Application Circuit

58 Skyworks Solutions, Inc., Proprietary and Confidential MAY 16, 2003 [781] 376-3000 I FAX [781] 376-3100 I SALES@ SKYWORKSINC.COM I WWW.SKYWORKSINC.COM 103052A

Ordering Information

Model Name Manufacturing Part Number Product Revision CX74063 CX74063-26 © 2001, 2002, 2003 Skyworks Solutions, Inc. All Rights Reserved. Information in this document is provided in connection with Skyworks Solutions, Inc. ("Skyworks") products. These materials are provided by Skyworks as a service to its customers and may be used for informational purposes only. Skyworks assumes no responsibility for errors or omissions in these materials. Skyworks may make changes to its products, specifications and product descriptions at any time, without notice. Skyworks makes no commitment to update the information and shall have no responsibility whatsoever for conflicts, incompatibilities, or other difficulties arising from future changes to its products and product descriptions. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as may be provided in Skyworks’ Terms and Conditions of Sale for such products, Skyworks assumes no liability whatsoever. THESE MATERIALS ARE PROVIDED "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESS OR IMPLIED, RELATING TO SALE AND/OR USE OF SKYWORKS™ PRODUCTS INCLUDING WARRANTIES RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, PERFORMANCE, QUALITY OR NON-INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. SKYWORKS FURTHER DOES NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. SKYWORKS SHALL NOT BE LIABLE FOR ANY SPECIAL, INDIRECT, INCIDENTAL, OR CONSEQUENTIAL DAMAGES, INCLUDING WITHOUT LIMITATION, LOST REVENUES OR LOST PROFITS THAT MAY RESULT FROM THE USE OF THESE MATERIALS. Skyworks™ products are not intended for use in medical, lifesaving or life-sustaining applications. Skyworks’ customers using or selling Skyworks™ products for use in such applications do so at their own risk and agree to fully indemnify Skyworks for any damages resulting from such improper use or sale. The following are trademarks of Skyworks Solutions, Inc.: Skyworks™, the Skyworks symbol, “Single Package Radio”™, SPR™, and “Breakthrough Simplicity”™. Product names or services listed in this publication are for identification purposes only, and may be trademarks of third parties. Third-party brands and names are the property of their respective owners. GSM™, “Global System for Mobile Communications™,” and the GSM logo are trademarks of the GSM Association. RFLGA™ is a trademark of Conexant Systems, Inc. Additional information, posted at www.skyworksinc.com, is incorporated by reference.

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