CX74036

CX74036 CONEXANT | Alldatasheet

Document overview

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Technical content

Features

• Front-end to baseband in one IC
• Inphase and Quadrature (I/Q) demodulator
• 3 V supply operation
• Low current consumption
• LNA gain switch with current reduction
• IF LO synthesizer with Voltage Controlled Oscillator (VCO) (requires external tank)
• 70 dB Variable Gain Amplifier (VGA) dynamic range
• Low Noise Figure (NF) and high 3rd order Input Intercept Point (IIP3) mixers

Applications

• Cellular and/or PCS band phones
• TDMA and/or AMPS mode phones
• Portable battery powered radio equipment 101105A-1_082500 IF_O- EXT_LOIN VCC_VCO VCO- VCO+ VCC_SYN LP_FIL REFIN DATA MX2I- VCC_IF IFBYPASS MX2OUT Vvga VCC_VGA VGAI- VGAI+ FB_CAP LATCH_EN CLK 17161514 18 19 20 21 22 23 24 LNA_G MXIH MIXIL BAND CHIP_EN LOIH LOIL VCC_MX STANDBY IQ/IF MXOUT+ MXOUT- MX2I+ 45464748 44 43 42 41 40 39 38 LNA_OH LNA_OL VCC2_LNAH VCC2_LNAL VCC1_LNA NC2 LNA_INL LNA_INH NC1 EXT_LO IF_O+

Figure 1. CX74036 48-Pin, 7x7 LGA Package Pin Configuration

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Figure 2. CX74036 Functional Block Diagram line interface. Only one LNA is powered at any given time. being fed to the RF mixer inputs. designed to provide high suppression of one-half IF response.

10 K Ω to IF SAW

Figure 3. RF Mixer Load Configuration system dynamic range is extended to more than 95 dB.

external LO source for the I/Q demodulator. diagram is shown in Figure 4. the recommended operating conditions are specified in Table 5. Electrical characteristics are shown in Table 6. Figure 6 provides the 48-Pin, 7x7 LGA package dimensions. Table 1. Control Logic Truth Table the IF Mixer with an external synthesizer. Table 2. 3-Wire Bus Programming Data

00 Select VCO or Reference Input to Programming Counter “0” = Reference Input

24 Charge Pump Polarity “0” = Ground Referenced Varactor

35 Synthesizer Power down (For External Synthesizer Mode) “0” = Internal Synthesizer

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Figure 4. 3-Wire Programming Data Pattern Table 3. Signal Pin Names and Definitions (1 of 2)

1 LNA_G LNAs gain control command

2 MXIH 1900 MHz band mixer Input

3 MIXIL 800 MHz band mixer Input

4 BAND 800 MHz/1900 MHz band select command

5 CHIP_EN Chip power down select command

6 LOIH 1900 MHz RF mixer LO input

7 LOIL 800 MHz RF mixer LO input

9 STANDBY Control signal to enable RF LO buffers and VHF synthesizer

10 IQ/IF I/Q or IF output select command

11 MXOUT+ RF mixer output. Open Collector. 12 MXOUT- RF mixer output. Open Collector.

13 MX2I+ IF mixer input

14 MX2I- IF mixer input

15 VCC_IF IF section VCC

16 IFBYPASS IF mixer bias decoupling

17 MX2OUT IF mixer output

18 Vvga Analog voltage input for VGA gain control

19 VCC_VGA VGA section VCC

20 VGAI- VGA input

21 VGAI+ VGA input

22 FB_CAP VGA DC feedback filter capacitor connection

23 LATCH_EN Enable input line for internal synthesizer programming

24 CLK Serial clock input line for internal synthesizer programming

25 DATA Serial data input line for internal synthesizer programming

26 REFIN 19.44 MHz reference oscillator input. Requires VCC/2 DC bias.

Table 3. Signal Pin Names and Definitions (2 of 2)

27 LP_FIL IF PLL external loop filter connection

28 VCC_SYN Synthesizer section VCC

29 VCO+ IF VCO external tank circuit connection

30 VCO- IF VCO external tank circuit connection

31 VCC_VCO VCO section VCC

32 EXT_LOIN External LO input for quadrature detector. Requires VCC/2 DC bias.

33 I+ I Channel data output

34 I– I Channel data output

35 Q+ Q Channel data output

36 Q– Q Channel data output

37 IF_O– Buffered IF output

38 IF_O+ Buffered IF output

39 EXT_LO Programmable counter ON/OFF control signal for choosing between

Internal and External demodulator LO.

40 NC1 No connect

41 LNA_INH 1900 MHz band LNA input

42 LNA_INL 800 MHz band LNA input

43 NC2 No connect

44 VCC1_LNA Bias VCC for LNAs

45 VCC2_LNAL VCC for cellular band LNA. 46 VCC2_LNAH VCC for PCS band LNA. 47 LNA_OL 800 MHz band LNA output. Requires external matching and AC coupling. 48 LNA_OH 1900 MHz band LNA output. Requires external matching and AC coupling. Table 4. Absolute Maximum Ratings

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Table 5. Recommended Operating Conditions Table 6. Electrical Characteristics (1 of 5)

Table 6. Electrical Characteristics (2 of 5) LO input port impedance Internal match.

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Table 6. Electrical Characteristics (3 of 5) LO input port impedance Internal match.

Table 6. Electrical Characteristics (4 of 5)

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Table 6. Electrical Characteristics (5 of 5) Figure 5. 3-Wire Bus Timing Diagram

Figure 6. 48-Pin, 7x7 LGA Package Dimensions

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Data Subject to Change October 17, 2000

Ordering Information

Table 7. Ordering Information © 2000, Conexant Systems, Inc. All Rights Reserved. conflicts or incompatibilities arising from future changes to its specifications and product descriptions. Conditions of Sale for such products, Conexant assumes no liability whatsoever. NOT WARRANT THE ACCURACY OR COMPLETENESS OF THE INFORMATION, TEXT, GRAPHICS OR OTHER ITEMS CONTAINED WITHIN THESE MATERIALS. REVENUES OR LOST PROFITS, WHICH MAY RESULT FROM THE USE OF THESE MATERIALS. applications do so at their own risk and agree to fully indemnify Conexant for any damages resulting from such improper use or sale. Additional information, posted at www.conexant.com, is incorporated by reference. Reader Response: Conexant strives to produce quality documentation and welcomes your feedback. Please send comments and suggestions to tech.pubs@conexant.com. For technical questions, contact your local Conexant sales office or field applications engineer.

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