CX24118A

NXP Semiconductors

Advanced Modulation Digital Satellite Tuner Rev. 02-8 September 2009

Manufacturer: NXP Semiconductors

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Advanced Modulation Digital Satellite Tuner Rev. 02 — 8 September 2009 Product data sheet Document information Info Content Keywords Abstract

CX24118A_N_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 8 September 2009 2 Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com NXP Semiconductors CX24118A Advanced Modulation Digital Satellite Tuner

Ordering information

Type number Description Package CX24118A-12Z* Advanced Modulation Digital Satellite Tuner 36-pin QFN *Lead-free (Pb Free) and RoHS compliant

Revision history

02 20090908 Added Figure 12 01 20081125 First NXP version based on the Conexant 102322A data sheet.

CX24118A_N_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 8 September 2009 3 NXP Semiconductors CX24118A Advanced Modulation Digital Satellite Tuner General description The CX24118A is a direct down-conversion satellite tuner intended for high-volume digital video, audio, and data receivers. The CX24118A offers excellent phase noise performance and very low implementation loss, required for advanced modulation systems such as 8PSK and DVB-S2. The CX24118A has a built-in auto-tuning system that eliminates the need for software calibration. The on-chip fractional synthesizer enables fine frequency step size without adversely affecting lock time. The CX24118A does not require a balun, thus reducing external BOM cost. Its highly integrated design saves valuable board space and simplifies RF layout.

Features

Single-chip RF-to-baseband satellite receiver Zero-IF architecture eliminates the need for image reject filtering Very low phase noise integrated Local Oscillators (LOs) for 8PSK and DVB-S2

applications

Variable baseband filters for optimal interference rejection Auto-tuning system eliminates need for software calibration Very low power consumption Small (6 mm x 6 mm) footprint Lead-free package 8PSK, DVB-S2, and advanced modulation set-top boxes Commercial digital video, audio, and PVR receivers Product Specifications RF input: 925–2175 MHz Symbol rate: 1–45 MSps Noise figure: 10 dB, typical Input IP3 at minimum gain: 10 dBm, typical Block diagram I_OUT Q_OUT VTUNE CP_OUT XSEL XTAL1 XTAL2 CKREF_OUT RF_IN AGC Crystal Oscillator and Clock Control PLL and VCO VCA VGA1 Filter 2 I/Q Mixer VGA2Filter 1 Final Amplifier0o 90o DC Offset Cancellation DC Offset Cancellation AGC Control Filter Control Logic Interface SADD SCL SDA : 2,

1.1 Pin Diagram

Figure 1 provides a pinout of the CX24118A. Figure 1. Pin Diagram

1.2 Pin Assignments

Table 1 lists the CX24118A pin names, numbers, types, and descriptions. Table 1. Pin Assignments N/C 1 N/C Not internally connected. VCC_VCO 2 Power 3.3V power supply for the VCO section. VCC_CP 4 Power 3.3V power supply for the charge pump section. CP_OUT 5 Output Charge pump output. The input of the external PLL loop filter is connected to this pin. XTAL_BIAS 6 Input Crystal oscillator bias. For normal operation, leave this pin unconnected. VCC_XTAL 7 Power 3.3V power supply for the crystal oscillator section. CKREF_OUT 10 Output Clock reference output. The maximum load allowed at this pin is 10 k Ω // 20 pF. VCC_DIG 11 Power 3.3 V power supply for digital section. GND_DIG 12 Ground Digital ground. SDA 13 I/O Serial programming interface data signal. Open drain. SCL 14 Input Serial programming interface clock signal. I_OUTN 15 Output The negative differential I channel output to demodulator. Zout = 1 k Ω // 10 pF. I_OUTP 16 Output The positive differential I channel output to demodulator. Zout = 1 k Ω // 10 pF. Q_OUTP 17 Output The positive differential Q channel output to demodulator. Zout = 1 k Ω // 10 pF. Q_OUTN 18 Output The negative differential Q channel output to demodulator. Zout = 1 k Ω // 10 pF. N/C 19 N/C Not internally connected. BB_REF 20 Input Current reference for baseband section. Place a 698 Ω ±1% resistor to ground. VCC2_BB 21 Power 3.3 V power supply for the baseband section. and both baseband variable gain amplifiers. Zin = 10 kΩ // 20 pF. VCC1_BB 23 Power 3.3 V power supply for the baseband section. VCC1_RF 24 Power 3.3 V power supply pin for the RF section. RF_INP 25 Input The positive differential RF signal input pin.

CX24118A_N_2 © NXP B.V. 2009. All rights reserved. N/C 27 N/C Not internally connected. N/C 28 N/C Not internally connected. N/C 29 N/C Not internally connected. N/C 30 N/C Not internally connected. VCC2_RF 31 Power 3.3 V power supply pin for the RF section. N/C 32 N/C Not internally connected. N/C 33 N/C Not internally connected. crystal. This pin has an internal 30 kΩ pull-up resistor. VCC_PS 36 Power 3.3 V power supply for the prescaler section.

2.1 General Description

fractional synthesizer, crystal oscillator with buffered output, and an automatic tuning system. A CX24118A detailed block diagram is shown in Figure 2. Figure 2. Detailed Block Diagram

2.2 Downconverter and Baseband Filtering

The L band input from the LNB is fed into the CX24118A either differentially or single-ended.

18 Bit

2.3 Gain Settings

The CX24118A is controlled by a single AGC signal, providing a dynamic range of 90 dB. stages are shown in figure 2-1. Table 2. Maximum Signal Level Settings demodulator, use the setting that corresponds to 25 dB.

2.4 Local Oscillator and PLL

set automatically at every channel change to give optimum integrated phase noise.

Set the dividers LODivSel (0x18[6]) and PLLRefDiv (0x02[1]) based on pre-defined or

calculated frequency ranges.

See Figure 3 for recommended divider settings when using a 40 MHz crystal. 2. Calculate the total PLL division ratio. Ndivider = ; if PLLRefDiv = 0 = ; if PLLRefDiv = 1 3. Calculate the integer divider PLLIntDiv[8:0]. PLLIntDiv[8:0] = Round[Ndivider] – 32
The Round function rounds the result to the nearest integer.
PLLIntDiv[8:0] can range from 6d to 511d. This is taken into consideration when selecting the divider ranges.

Table 3. Minimum Signal Level Settings demodulator, use the setting that corresponds to 25 dB.

Calculate the fractional divider PLLFracDiv[17:0].

To avoid fractional spurs, the fractional divider should not produce VCO frequencies within 250 kHz or 125 kHz of the frequencies generated by PLLFracDiv[17:0] = 0.0 or 0.5 respectively.
When the requested frequency is within 250 kHz of the frequency generated by PLLFracDiv[17:0] = 0.0, the PLL should be put into integer mode. Integer mode is enabled by setting register bit DSMByp (0x10[6]) to 1.
When the requested frequency is within 125 kHz of the frequency generated by PLLFracDiv[17:0] = 0.5, the closest fractional value outside of the keep-out range should be used.

Figure 3. Recommended Divider Settings vs. Frequency When Using 40 MHz Crystal

2.5 Crystal Oscillator and Reference Clock

PLLInDiv[8:0] within its usable range of 65-511d. (3) This reference divider break-point is set at 37.5*Fxtal. For a 40 MHz Xtal, this value is 1500 MHz.

40 MHz sinusoidal clock is produced, and when OUTRefDiv = 1, a 20 MHz square clock is

produced (when OUTRefDiv = 1 mode is used, the XTAL_BIAS pin needs to be grounded). components should be RF type components (high Q) with good characteristics at 40 MHz. Figure 4. Third-Overtone Crystal Oscillator External Circuit The selected crystal should be a high-quality crystal with minimum drive level dependencies. Table 4. Recommended Component Values for Third-Overtone Crystal Oscillator

2.6 Automatic Tuning System

2.6.1 Auto-tuning Procedure

Program the tuning system preload values with the values provided by Conexant and

enable the automatic tuning system. a. Set register field TUN1[5:0] (0x14[5:0]) to 0x0F. should be programmed to 00b at the same time. b. Set register TUN2[7:0] (0x15[7:0]) to 0xFF. c. Set register TUN3[7:0] (0x16[7:0]) to 0xFF.

Program automatic charge pump levels with the values provided by Conexant. These

values are selected based on the VCO tuning voltage. a. Set register field CPLevel1[1:0] (0x11[7:6]) to 11b. b. Set register field CPLevel2[1:0] (0x11[5:4]) to 11b. c. Set register field CPLevel3[1:0] (0x11[3:2]) to 10b. Table 5. Crystal Requirements this spec at 10 nW is required. This number is also required at operating power levels.

CX24118A_N_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 8 September 2009 21 NXP Semiconductors CX24118A Chapter 2: Functional Descriptions d. Set register field CPLevel4[1:0] (0x11[1:0]) to 00b. 3. There are other registers not directly related to tuning system initialization that must also be programmed. These values are not discussed here. During Channel Change 1. Choose the appropriate dividers using register bits LODivSel (0x18[6]) and PLLRefDiv (0x02[1])). For more detail, see Section 2.4 2. Select the gain settings. The minimum signal level settings can be used at this point. 3. Set the bandwidths of the baseband filters using register fields BBFil1BW[1:0] and BBFil2BW[1:0] based on the symbol rate, roll-off, and desired carrier acquisition range. 4. Program the PLL dividers PLLIntDiv[8:0] and PLLFracDiv[17:0] using the values generated from the procedure given in Section 2.4, and start the tuning process as follows: a. Program registers 0x19-0x1B. b. Program the remaining PLL dividers into register 0x1C while setting the start bit TUNReset (0x1C[4]) to 1. 5. Monitor PLL lock using register bit TUNLD. When lock has been achieved, measure the power to determine the appropriate gain settings. Set new gain settings if required. See Section 2.3 for more detail. a. After lock, the charge pump values are automatically selected, based on the VCO tuning voltage and the charge pump initialization values.

3.1 Serial Programming Interface

requiring an external pull-up resistor. The serial clock and data signals for a typical transaction is shown in Figure 5. Figure 5. Serial Clock and Data Signals address, it generates an acknowledge bit on the SDA line.

Send the Start condition.
Send the CX24118A slave address, a write bit, and receive an ACK.
Send the CX24118A desired register address = n, and receive an ACK.
Send the byte for a desired register = n, and receive an ACK.

The above-described single-byte write procedure is shown in Figure 6. (1) Acknowledge generated by CX24118A. (2) Subsequent bytes are assumed to be data for registers whose addresses follow in ascending order.

Send the Start condition.
Send the CX24118A slave address, a write bit, and receive an ACK.
Send the CX24118A desired register address = n, and receive an ACK.
Send the Start condition.
Send the part's slave address, a read bit, and receive an ACK.
Receive the byte from register n, and supply an ACK.
Receive the byte from register n+1, and supply an ACK.
Receive the byte from register n+2, and supply an ACK.
Receive the data from register n+m, and do not supply an ACK.
Send the Stop condition.

The above-described multiple-bytes read procedure is shown in Figure 9.

3.2 Registers

The register bit map is shown in Table 6. Table 6. Register Bit Map (Sheet 1 of 2)

00 CHPId[7:0]

01 CHPVer[7:0]

02 Reserved OUTRefDiv PLLRefDiv Reserved

10 DSMClkPol DSMByp CPMan[1:0] CPDVal[1:0] TUNLD CPSel

11 CPLevel1[1:0] CPLevel2[1:0] CPLevel3[1:0] CPLevel4[1:0]

12 BsDelayVal[3:0] Reserved CPCtrl CPVal[1:0]

13 Reserved

14 TUNAutoEn[1:0] TUN1[5:0]

15 TUN2[7:0]

16 TUN3[7:0]

17 TUN4[7:0]

18 VCOSel[5] LODivSel VCOSel[4:0] VCOBandSel

19 PLLIntDiv[8:1]

3.3 Register Index

The register index is shown in Table 7.

20 Reserved RFVCABCDis RFVCAOff[1:0] Reserved

21 Reserved CPEn PSEn BBEn DCCorrEn Reserved RFVCAEn

(1) The values in this column are hexadecimal. Table 7. Register Index BBFAmpGain[3:0] 1D[3:0] Final Baseband Amplifier Gain. BBFil1BW[1:0] 1E[7:6] Baseband Filter 1 Bandwidth. BBFil2BW[5:0] 1E[5:0] Baseband Filter 2 Bandwidth. BBVGA1Off[2:0] 1F[2:0] Baseban d VGA1 Offset Control. BBVGA2Off[2:0] 1F[5:3] Baseban d VGA2 Offset Control. BsDelayVal[3:0] 12[7:4] VCO Tuning System Delay. CHPId[7:0] 00[7:0] Chip Identification Number. CHPVer[7:0] 01[7:0] Chip Version Number. CPCtrl 12[2] Charge Pump Control. CPDVal[1:0] 10[3:2] Digital Charge Pump Valve. CPEn 21[5] Charge Pump Enable. CPLevel1[1:0] 11[7:6] Automatic Charge Pump Level 1 Select. CPLevel2[1:0] 11[5:4] Automatic Charge Pump Level 2 Select. CPLevel3[1:0] 11[3:2] Automatic Charge Pump Level 3 Select. CPLevel4[1:0] 11[1:0] Automatic Charge Pump Level 4 Select. Table 6. Register Bit Map (Sheet 2 of 2)

CX24118A_N_2 © NXP B.V. 2009. All rights reserved. CPMan[1:0] 10[5:4] Manual Analog Charge Pump Select. CPSel 10[0] Manual Override of Automatic Charge Pump Level Select. CPVal[1:0] 12[1:0] Analog Charge Pump Level. DCCorrEn 21[2] DC Offset Correction Enable. DSMByp 10[6] Delta Sigma Modulator Bypass. DSMClkPol 10[7] DSM Clock Polarity Select. LODivSel 18[6] Local Oscillator (LO) Divider Select. OUTRefDiv 02[2] Output Reference Divider. PLLRefDiv 02[1] PLL Reference Divider. PSEn 21[4] Prescaler Enable. RFVCABCDis 20[4] RF VCA Bias Control Circuit Disable. RFVCAEn 21[0] RF VCA Enable. RFVCAOff[1:0] 20[3:2] RF VCA Offset Select. TUN1[5:0] 14[5:0] Tuning System Configuration Register 1. TUN2[7:0] 15[7:0] Tuning System Configuration Register 2. TUN3[7:0] 16[7:0] Tuning System Configuration Register 3. TUN4[7:0] 17[7:0] Tuning System Configuration Register 4. TunAutoEn[1:0] 14[7:6] Auto-tuning System Enable. TUNLD 10[1] PLL Lock Detect. TUNReset 1C[4] Tuning System Reset. VCOBandSel 18[0] VCO Band Select. (1) The values in this column are hexadecimal.

3.4 Register Detail

This section provides the register detail. Register 00 Register 01 Register 02 Register 10 NOTE: POR refers to power-on reset value. NOTE: All bits in the registers are Read/Write unless indicated otherwise in the bit description. Register (Hex) POR D7 D6 D5 D4 D3 D2 D1 D0 00 43 CHPId[7:0] CHPId[7:0] Chip Identification Number. The current chip ID is 0x23. Read only. Register (Hex) POR D7 D6 D5 D4 D3 D2 D1 D0 01 03 CHPVer[7:0] CHPVer[7:0] Chip Version Number. The current chip version is 0x03. Read only. Register (Hex) POR D7 D6 D5 D4 D3 D2 D1 D0 02 00 Reserved OUTRefDiv PLLRefDiv Reserved OUTRefDiv Output Reference Divider. This bit selects the reference clock divider for the CKREF_OUT pin. See Section 2.5 for more detail. 0 = ÷1. 1 = ÷2. PLLRefDiv PLL Reference Divider. This bit selects the divider for the tuner synthesizer reference frequency. 0 = ÷1. 1 = ÷2. Register (Hex) POR D7 D6 D5 D4 D3 D2 D1 D0 10 00 DSMClkPol DSMByp CPMan[1:0] CPDVal[1:0] TUNLD CPSel

CX24118A_N_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 8 September 2009 30 NXP Semiconductors CX24118A Chapter 3: Serial Programming Interface and Registers Register 11 DSMClkPol DSM Clock Polarity Select. 0 = No clock inversion. 1 = Clock inversion. Use this setting for normal operation. DSMByp Delta Sigma Modulator Bypass. 1 = Disables the delta sigma modulator, resulting in integer division. 0 = Delta sigma modulator along with prescaler defines the divider. Normal operation. CPMan[1:0] Manual Analog Charge Pump Select. Selection of analog charge pump level in manual mode when register bit CPSel is set to 1. The levels are defined as follows: 00b = 0.5 mA. 01b = 1.0 mA. 10b = 1.5 mA. 11b = 2.0 mA. CPDVal[1:0] Digital Charge Pump Valve. The digital charge pump is enabled during tuning only. 00b = 0.5 x analog charge pump level. 01b = 1.0 x analog charge pump level. 10b = 2.0 x analog charge pump level. Use this setting for normal operation. 11b = 3.0 x analog charge pump level. TUNLD PLL Lock Detect. 0 = Synthesizer not frequency locked. 1 = Synthesizer is frequency locked. CPSel Manual Override of Automatic Charge Pump Level Select. 0 = Automatic charge pump current selection. 1 = Manual charge pump current selection. Register (Hex) POR D7 D6 D5 D4 D3 D2 D1 D0 11 00 CPLevel1[1:0] CPLevel2[1:0] CPLevel3[1:0] CPLevel4[1:0] Register (Hex) POR D7 D6 D5 D4 D3 D2 D1 D0

CX24118A_N_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 8 September 2009 31 NXP Semiconductors CX24118A Chapter 3: Serial Programming Interface and Registers Register 12 Register 14 CPLevel1[1:0] Automatic Charge Pump Level 1 Select. Charge pump level 1 is selected by the automatic tuning system when the VCO tuning voltage is greater than 2.0 V. For normal operation, set to 11b. CPLevel2[1:0] Automatic Charge Pump Level 2 Select. Charge pump level 2 is selected by the automatic tuning system when the VCO tuning voltage is between 1.5 V and 2.0 V. For normal operation, set to 11b. CPLevel3[1:0] Automatic Charge Pump Level 3 Select. Charge pump level 3 is selected by the automatic tuning system when the VCO tuning voltage is between 1.0 V and 1.5 V. For normal operation, set to 10b. CPLevel4[1:0] Automatic Charge Pump Level 4 Select. Charge pump level 4 is selected by the automatic tuning system when the VCO tuning voltage is lower than 1.0 V. For normal operation, set to 00b. For each of the above register fields, the analog charge pump levels are set as follows: 00b = 0.5 mA. 01b = 1.0 mA. 10b = 1.5 mA. 11b = 2.0 mA. Register (Hex) POR D7 D6 D5 D4 D3 D2 D1 D0 12 80 BsDelayVal[3:0] Reserved CPCtrl CPVal[1:0] BsDelayVal[3:0] VCO Tuning System Delay. VCO tuning system delay in reference clock cycles between the time tuning system is enabled and tuning starts. The default is 8 counts and can be set between 0 and 15 counts of reference cycle. The reference cycle period is: TREF = R/Reference oscillator frequency R is the reference divider value selected by register bit PLLRefDiv (0x02[1]). For normal operation, set to 0x8. CPCtrl Charge Pump Control. 0 = Analog charge pump turns OFF when the digital charge pump turns ON (when register bit TUNLD (0x10[1]) is low). 1 = Analog charge pump always ON. Use this setting for normal operation. CPVal[1:0] Analog Charge Pump Level. This is the value selected by the automatic tuning system, as specified in register 0x11. The values correspond to the following charge pump levels. Read only. 00b = 0.5 mA. 01b = 1.0 mA. 10b = 1.5 mA. 11b = 2.0 mA. Register (Hex) POR D7 D6 D5 D4 D3 D2 D1 D0 14 00 TUNAutoEn[1:0] TUN1[5:0] Register (Hex) POR D7 D6 D5 D4 D3 D2 D1 D0

CX24118A_N_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 8 September 2009 32 NXP Semiconductors CX24118A Chapter 3: Serial Programming Interface and Registers Register 15 Register 16 Register 17 Register 18 TUNAutoEn[1:0] Auto-tuning System Enable. 00b = Auto-tuning mode. The auto-tuning system selects the VCO. Normal operation. 01b = Manual tuning mode. The VCO is selected using register field VCOSel[5:0]. 10b - 11b = Reserved. TUN1[5:0] Tuning System Configuration Register 1. For normal operation, set to 0x0F. Register (Hex) POR D7 D6 D5 D4 D3 D2 D1 D0 15 00 TUN2[7:0] TUN2[7:0] Tuning System Configuration Register 2. For normal operation, set to 0xFF. Register (Hex) POR D7 D6 D5 D4 D3 D2 D1 D0 16 00 TUN3[7:0] TUN3[7:0] Tuning System Configuration Register 3. For normal operation, set to 0xFF. Register (Hex) POR D7 D6 D5 D4 D3 D2 D1 D0 17 00 TUN4[7:0] TUN4[7:0] Tuning System Configuration Register 4. For normal operation, set to 0xF0. Register (Hex) POR D7 D6 D5 D4 D3 D2 D1 D0 18 00 VCOSel[5] LODivSel VCOSel[4:0] VCOBandSel Register (Hex) POR D7 D6 D5 D4 D3 D2 D1 D0

CX24118A_N_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 8 September 2009 33 NXP Semiconductors CX24118A Chapter 3: Serial Programming Interface and Registers Register 19 – 1C Register 1D VCOSel[5] VCO 6 Select. This bit, when read, indicates if VCO6 is selected. 0 = VCO 6 deselected. 1 = VCO 6 selected when VCOSel[4:0] = 00000b. LODivSel Local Oscillator (LO) Divider Select. This bit, when read, indicates the LO divider selected by the auto-tuning system. When written to, this bit selects the divider. 0 = ÷2. 1 = ÷4. VCOSel[4:0] VCO Select. These bits, when read, indicate the VCO selected by the auto-tuning system. The VCO can be manually selected by writing to these bits. Only one VCO should be selected at a time. 00000b = None of these VCOs are selected. 00001b = VCO5 selected. 00010b = VCO4 selected. 00100b = VCO3 selected. 01000b = VCO2 selected. 10000b = VCO1 selected. VCOBandSel VCO Band Select. This bit is common to all VCOs. This bit, when read, indicates the VCO band selected by the auto-tuning system. When written to, this bit selects the VCO band. 0 = High band. 1 = Low band. Register (Hex) POR D7 D6 D5 D4 D3 D2 D1 D0 19 00 PLLIntDiv[8:1] 1A 00 PLLIntDiv[0] PLLFracDiv[17:11] 1B 00 PLLFracDiv[10:3] 1C 10 PLLFracDiv[2:0] TUNReset Reserved PLLIntDiv[8:0] PLL Integer Divider. PLLFracDiv[17:0] PLL Fractional Divider. TUNReset Tuning System Reset. Setting this bit to 1 resets the auto-tuning system and starts the auto-tuning process. Write only. Register (Hex) POR D7 D6 D5 D4 D3 D2 D1 D0 1D 00 Reserved BBFAmpGain[3:0] BBFAmpGain[3:0] Final Baseband Amplifier Gain. 0000b = 37 dB gain. 0001b = 34 dB gain. 0011b = 31 dB gain. Use this setting under all conditions. 0111b = 28 dB gain. 1111b = 25 dB gain. Register (Hex) POR D7 D6 D5 D4 D3 D2 D1 D0

CX24118A_N_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 8 September 2009 34 NXP Semiconductors CX24118A Chapter 3: Serial Programming Interface and Registers Register 1E Register 1F Register 20 Register (Hex) POR D7 D6 D5 D4 D3 D2 D1 D0 1E 00 BBFil1BW[1:0] BBFil2BW[5:0] BBFil1BW[1:0] Baseband Filter 1 Bandwidth. 00b = 100 MHz. 01b = 65 MHz. Use this setting for 30–45 MSps operation. 10b = 40 MHz. Use this setting for 20–30 MSps operation. 11b = 35 MHz. Use this setting for 1–20 MSps operation. BBFil2BW[5:0] Baseband Filter 2 Bandwidth. The filter bandwidth set is given by: BW = 2 + BBFil2BW[5:0] The bandwidth is adjustable in 63 steps with a step size of 1 MHz. The bandwidth range is 2 MHz to 65 MHz. Register (Hex) POR D7 D6 D5 D4 D3 D2 D1 D0 1F 00 Reserved BBVGA2Off[2:0] BBVGA1Off[2:0] BBVGA2Off[2:0] Baseband VGA2 Offset Control. 000b = –41 dB. 100b = –39 dB. 010b = –37 dB. 110b = –35 dB. 001b = –33 dB. 101b = –31 dB. Use this setting when fixed gain settings are desired. 011b = –29 dB. Use this setting for minimum signal levels. 111b = –27 dB. Use this setting for maximum signal levels. BBVGA1Off[2:0] Baseband VGA1 Offset Control. 000b = –36 dB. 100b = –34 dB. 010b = –32 dB. Use this setting for minimum signal levels. 110b = –30 dB. 001b = –28 dB. Use this setting when fixed gain settings are desired. 101b = –26 dB. 011b = –24 dB. 111b = –22 dB. Use this setting for maximum signal levels. Register (Hex) POR D7 D6 D5 D4 D3 D2 D1 D0 20 00 Reserved RFVCABCDis RFVCAOff[1:0] Reserved

CX24118A_N_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 8 September 2009 35 NXP Semiconductors CX24118A Chapter 3: Serial Programming Interface and Registers Register 21 RFVCABCDis RF VCA Bias Control Circuit Disable. The VCA is made up of multiple, parallel, gain stages. When stages are unused, they are either turned off, or completely disabled by shutting off their bias, according to the state of this bit. 0 = Bias in unused stages is turned off. 1 = Bias in unused stages is not turned off. RFVCAOff[1:0] RF VCA Offset Select. 00b = –70 dB. Use this setting for maximum signal levels, and when fixed gain settings are desired. 01b = –67 dB. 10b = –64 dB. Use this setting for minimum signal levels. 11b = –61 dB. Register (Hex) POR D7 D6 D5 D4 D3 D2 D1 D0 21 00 Reserved CPEn PSEn BBEn DCCorrEn Reserved RFVCAEn CPEn Charge Pump Enable. 1 = Enable. 0 = Disable. PSEn Prescaler Enable. 1 = Enable. 0 = Disable. BBEn Baseband Enable. 1 = Enable. 0 = Disable. DCCorrEn DC Offset Correction Enable. 1 = Enable. 0 = Disable. RFVCAEn RF VCA Enable. 1 = Enable. 0 = Disable. Register (Hex) POR D7 D6 D5 D4 D3 D2 D1 D0

4.1 Thermal Recommendations

lists the CX24118A thermal layout recommendations.

4.2 Sleep Mode Procedures

4.2.1 Changing from Normal Operation to Sleep Mode

Set register field TUNAutoEn[1:0] (0x14[7:6]) to 01b.
Set register field VCOSel[5:0] (0x18[7] and 0x18[5:0]) to 0.
Set the system enable bits (0x21[5:0]) to 0x00.

4.2.2 Changing from Sleep Mode to Normal Operation

Set register field TUNAutoEn[1:0] (0x14[7:6]) to 01b.
Set the system enable bits (0x21[5:0]) to 0x3F.
Restart the tuning system by setting TUNReset to 1.

Table 8. Thermal Recommendations Via diameter 0.33 mm drill-hole size with 1 oz copper plating. (1) As many of the layers should be grounded and connected to the thermal vias as possible. should be covered with solder mask.

5.1 S11 Plot

Figure 10. S11 Plot

The measurement was taken at the input of the device using a short 50 Ω coaxial cable stub.

5.2 Electrical and Thermal Specifications

5.2.1 Absolute Maximum Ratings

5.2.2 Recommended Operating Conditions

5.2.3 Receiver Electrical and Thermal Specifications

Table 9. Absolute Maximum Ratings Table 10. Recommended Operating Conditions Table 11. Receiver Electrical Spec ifications (Sheet 1 of 3)

CX24118A_N_2 © NXP B.V. 2009. All rights reserved. (1) This is the current drawn when all blocks are disabled except the crystal oscillator and digital sections. (2) –25 dBm is single tone power and –6 dBm is the aggregate average power of 40 QPSK modulated carriers. –69 dBm is the minimum power at 20 MSps, and –81 dB is the minimum power at 1 MSps. (3) This LO leakage is at RF_INP pin from 925 MHz–2175 MHz. (5) f3dB is calculated for alpha of 0.35, LNBoffset of 2.5 MHz. PLL step size, being very small (160 Hz), can be ignored. the ±(31,60) MHz tones correspond to ±(1.5*SR, 3*SR) MHz and the ±(91,180) MHz tones correspond to ±(4.5*SR, 9*SR) MHz. (8) From after serial communication has been received to stable lock. is a square wave when OutRefDiv is set to ÷2. Table 11. Receiver Electrical Spec ifications (Sheet 3 of 3)

5.3 Mechanical Specifications

The CX24118A uses two 36-pin Quad Flat No-Lead (QFN) plastic packages. The CX24118A package diagrams are shown in Figure 11 and Figure 12. Figure 11. Package Diagram

6.00 BSC

5.75 BSC

0.50 BSC

Plastic or metal protrusions of 0.075 mm maximum per side are not included.

Figure 12. Package Diagram

CX24118A_N_2 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 02 — 8 September 2009 45 NXP Semiconductors CX24118A Advanced Modulation Digital Satellite Tuner Legal information Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This docu ment contains the product specification.

NXP Semiconductors CX24118A Advanced Modulation Digital Satellite Tuner © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 8 September 2009 Document identifier: CX24118A_N_2 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 46

Product Information

CX24118A specifications and overview.

Summary

Advanced Modulation Digital Satellite Tuner Rev. 02-8 September 2009

Description

Advanced Modulation Digital Satellite Tuner Rev. 02-8 September 2009

Source title CX24118A Datasheet(PDF) - NXP Semiconductors

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