CX24109 NXP | Alldatasheet
Document overview
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Technical content
Datasheet sections
- 1 Functional Description
- 1.1 Pinout Information
- 1.2 Pin Description
- 1.3 Application Overview
- 1.4 Signal Path
- 1.5 AGC and Control
- 1.6 Local Oscillator
- 1.7 Programming Interface
- 1.7.1 Gain Equations
- 1.7.2 Frequency Equations
- 1.7.3 Recommended Default Values
- 2 Applications
- 2.1 AGC Input
- 2.2 VCO Power Pin Ripple Requirement
- 2.3 Transmission Lines
- 2.4 Example Schematic
- 2.5 Typical Performance Curves
- 3 Parametric Data and Specifications
- 3.1 Electrical Specifications
- 3.1.1 Standard Operating Conditions
- 3.2 Mechanical Specifications
Rev. 01 — 13 November 2008 Product data sheet Document information Info Content Keywords Abstract
CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 2 Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com NXP Semiconductors CX24109 Digital Satellite Tuner
Ordering information
Type number Description Package CX24109-11 Digital Satellite Tuner 48-pin eTQFP CX24109-11Z
Revision history
01 20081113 First NXP version based on the Conexant 102031A data sheet.
CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 3 NXP Semiconductors CX24109 Digital Satellite Tuner General description The CX24109 is a highly integrated, direct down-conversion satellite tuner intended for high-volume digital video, audio, and data receivers. When combined with the CX24121 QPSK demodulator/FEC decoder, the chip set provides a complete broadband satellite front-end solution capable of operating from 1–45 MSps in the most demanding satellite environments. It is compatible with international standards such as DVB and DSS. The highly integrated CX24109 reduces the tuner BOM cost and simplifies the RF layout.
Features
Zero-IF architecture eliminates the need for image reject filtering Integrated LNA Integrated LO with onboard VCO and synthesizer Single +5 V supply Reference oscillator output for demodulator
Applications
DBS set-top boxes Commercial digital video, audio, and data receivers Digital VCRs Block diagram RF Input VGA1 VGA2 VGA1 VCA VGA2 Variable Low Pass Filter I Channel Output Variable Low Pass Filter Q Channel Output VCO Reference Oscillator Reference to DEMOD Programming and Control Lock Detect PLL Dividers, Phase Detector, and Charge Pump
CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 4 NXP Semiconductors CX24109 Digital Satellite Tuner
CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 6 NXP Semiconductors CX24109 Digital Satellite Tuner
CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 7 NXP Semiconductors CX24109 Digital Satellite Tuner Figures
CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 8 NXP Semiconductors CX24109 Digital Satellite Tuner
CX24109_N_1 © NXP B.V. 2008. All rights reserved.
CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 10 NXP Semiconductors CX24109 Digital Satellite Tuner
CX24109_N_1 © NXP B.V. 2008. All rights reserved.
1.1 Pinout Information
1.2 Pin Description
Figure 1. CX24109 Pin Diagram Table 1. Pin Description RFIN 4 I RF input signal pin. FILTUNE 36 I Baseband filter control input from the demodulator/FEC IC. Minimum BW occurs at minimum voltage. Zin = 17 kΩ//20 pF.
CX24109_N_1 © NXP B.V. 2008. All rights reserved.
1.3 Application Overview
filter. See Figure 6 and Figure 7. CLKREFOUT 24 O Clock reference output. This pin provides the reference clock for the demodulator/FEC IC. The maximum load allowed at this node is ZLOAD = 10 kΩ//20 pF. these two pins to create the system clock. See Figure 6 and Figure 7. CLK 28 I Serial bus clock signal. EN 26 I Serial bus latch enable. DATA 27 I Serial bus data pin. LD 25 O The lock detect signal to the demodulator/FEC IC. LOAD = 10 kΩ//20 pF. High is the locked state. Table 2. Power Supply and Ground Pins
CX24109_N_1 © NXP B.V. 2008. All rights reserved. CX24109/CX24121 chip set in an STB front end.
1.4 Signal Path
Figure 2. QPSK Demodulation Typical Application Block Diagram
CX24109_N_1 © NXP B.V. 2008. All rights reserved. Figure 3. Detailed Functional Block Diagram
90 Degree
9 Bit
5 Bit
CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 15 NXP Semiconductors CX24109 Chapter 1: Functional Description The L-band output from the LNB enters the IC through the RFIN pin and is immediately amplified by the Voltage Controlled Attenuator block (VCA). The VCA functions as a variable gain LNA. The noise figure and gain of the VCA are the dominant factors for the tuner’s noise figure. The signal is then quadrature downconverted to I and Q baseband channels. Additional amplifiers at baseband provide more variable gain for the AGC loop. Also at baseband, variable low-pass filters provide anti-alias filtering and eliminate noise power from adjacent carriers and spurious signals before they can impact the A/Ds in the demodulator IC.
1.5 AGC and Control
The AGC functionality for the CX24109 is split between the RF and baseband sections, and provides 80 dB of variable gain. The primary control for the AGC is an analog voltage from the demodulator IC. Programmable adjustments to the slope and offset of each variable gain component in the tuner are available through the AGC control registers. Programming information for the VGA and VCA is provided in Tables 4 and 5, respectively. The recommended default values for the programmable control bits versus symbol rate are listed in Table 8.
1.6 Local Oscillator
The local oscillator consists of a synthesizer and a VCO block, and is contained entirely within the CX24109. The VCO block uses an innovative architecture that requires only a 5 V source, eliminating the need for a 28 V power supply. It includes the required tank circuit. The VCO block consists of a bank of eight oscillators operating at twice and four times the input frequency with a continuous range from 2200 MHz to 4400 MHz. The VCOs overlap to cover the frequency range from 950 MHz to 2150 MHz under all voltage, temperature, and process variations. The VCO tuning range, combined with programmable ÷2 or ÷4 frequency dividers, creates the continuous frequencies from 950 MHz to 2150 MHz for the local oscillator. A simple tuning algorithm must be run by the host processor one time at power-up to calibrate the VCO block. Conexant provides this program. The synthesizer is also contained within the CX24109. It uses a 10.111 MHz reference frequency and a reference divider, ÷R, to set the phase comparison frequency. Two programming bits are used to configure the reference divider to divide by 10, 20, or 40, which in turn sets the comparison frequency to 1.0111 MHz, 505 kHz, or 253 kHz, respectively. A reference divider of 10 is recommended. The comparison frequency also determines the frequency step size of the local oscillator. Another programmable divider is provided for the VCO output. It consists of a 32/33 prescaler, a 9-bit N-counter (N-divider), a 5-bit A-counter (A-divider), and a fixed ÷ 2 block. The programmable divider divides the VCO output from its highest frequency to the minimum phase comparison frequency. The programmable charge pump includes output currents of 1 mA, 2 mA, 3 mA, and 4 mA. Programming information for the synthesizer can be found in Table 7 . The recommended values for charge pump current, polarity, and referenced dividers are listed in Tables 9 and 10. The typical loop filter bandwidth is set with external passive components and should be set between 8 kHz and 15 kHz.
1.7 Programming Interface
A three-wire serial interface with Clock, Data, and Enable lines is used to program the CX24109. All digital signals are CMOS-compatible. The serial data carries the binary settings for the programmable dividers, the VCO band select, the voltage-controlled attenuator, and the voltage-controlled amplifiers. When the Enable line is low, data is shifted into an internal shift register on the rising edge of the clock, and when the Enable line goes high, the stored data is latched. The clock signal should be kept low when inactive. The maximum clock rate is 1 MHz. Figure 4 illustrates the relationship between the Clock, Data, and Enable signals.
CX24109_N_1 © NXP B.V. 2008. All rights reserved.
- R means Reserved except for ÷R which means reference divider.
(1) These Reserved locations must be set to zero. All other Reserved location values do not matter. (2) These Divide ratios are binary coded. Table 3. Programming Bit Mapping (Sheet 2 of 2)
CX24109_N_1 © NXP B.V. 2008. All rights reserved. Table 4. Band Select Programming
CX24109_N_1 © NXP B.V. 2008. All rights reserved. Table 5. VGA Programming
CX24109_N_1 © NXP B.V. 2008. All rights reserved. Table 6. VCA Programming
CX24109_N_1 © NXP B.V. 2008. All rights reserved.
1.7.1 Gain Equations
The RF block voltage gain (GRF) is equal to the VCA gain + the mixer gain. Table 7. PLL Programming
1 Negative
01 R e s e r v e d
10 R e s e r v e d
CX24109_N_1 © NXP B.V. 2008. All rights reserved.
1.7.2 Frequency Equations
1.7.3 Recommended Default Values
Table 8. Recommended AGC Programming Values setting. Theoretical settings are given in parentheses. (2) These values are for reference only. They are not programmable. Table 9. Recommended VCO Frequency vs. Charge Pump Current Table 10. Recommended Charge Pump Polarity and Reference Divider Values
CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 23 CX24109 Chapter 2: Applications Rev. 01 — 13 November 2008 Product data sheet
2.1 AGC Input
To prevent excessive current draw, a 10 kΩ resistor on the AGC pin is recommended. See Figure 6.
2.2 VCO Power Pin Ri pple Requirement
Care must be taken to reduce the power supply ripple on pin 13 (VCO power supply) in order to reduce phase noise. The power supply conditioning circuitry given in Figure 6 is suitable for most circumstances.
2.3 Transmission Lines
Though the CX24109’s RF layout is simple, there are two transmission lines that must be designed. The first transmission line is the LNB power line, which is located at the connector. The second transmission line is between the connector and the RF IN pin. The input transmission line must have a characteristic impedance of 75 Ω. The schematic gives recommended dimensions assuming a two-layer FR-4 board.
2.4 Example Schematic
Figure 6 provides a simplified version of the CX24109/CX24121 reference design. For complete and current reference design information, contact your local Conexant sales office.
CX24109_N_1 © NXP B.V. 2008. All rights reserved. Figure 6. Simplified Application Schematic (Page 1 of 2)
5 V_RF
CX24109_N_1 © NXP B.V. 2008. All rights reserved. Figure 7. Simplified Application Schematic (Page 2 of 2)
CX24109_N_1 © NXP B.V. 2008. All rights reserved.
2.5 Typical Performance Curves
Figure 8. Reflection Coefficient at Input of CX24109
CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 30 NXP Semiconductors CX24109 Chapter 2: Applications
CX24109_N_1 © NXP B.V. 2008. All rights reserved.
3.1 Electrical Specifications
3.1.1 Standard Operating Conditions
Table 11. Absolute Maximum Ratings Table 12. Operating Conditions
CX24109_N_1 © NXP B.V. 2008. All rights reserved. Table 13. DC Electrical Characteristics (1) Using 15–45 MSps programming values (see Table 8), Vcc = 5.0 V, VAGC = 1.45 V, VFiltune = 2.7 V. obtained by increasing ground plane coverage or increasing the number of attached printed circuit board layers. Table 14. AC Electrical Characteristics
CX24109_N_1 © NXP B.V. 2008. All rights reserved. Figure 15. Serial Programming Example Table 15. RF Electrical Char acteristics (Sheet 1 of 3)
CX24109_N_1 © NXP B.V. 2008. All rights reserved. Table 15. RF Electrical Char acteristics (Sheet 2 of 3)
CX24109_N_1 © NXP B.V. 2008. All rights reserved.
- Values in this table are valid under the operating conditions listed in Tables 8, 9,
(1) This measurement is made at RFIN of CX24109. (2) Aggregate average power of 40 QPSK modulated carriers. level to obtain the desired output level of 0.5 Vpp. (4) This level is derived assuming –23 dBm is the maximum level of all other transponders and that the operating symbol rate is 1 MSps. Assume C/I of 7 dB and a bandwidth scaling of 10 log (20 MHz / 1 MHz), thus, Pin = –23 dBm – 7 dB – 10 log (20 / 1) = –43 dBm. (6) This level is derived assuming –23 dBm is the maximum level of all other transponders and that the operating symbol rate is 7 MSps. Assume C/I of 7 dB and a bandwidth scaling of 10 log (20 MHz / 7 MHz), thus, Pin = –23 dBm – 7 dB – 10 log 20 / 7 = –34.5 dBm. (9) Assume a symbol rate of 20 MSps. Table 15. RF Electrical Char acteristics (Sheet 3 of 3)
CX24109_N_1 © NXP B.V. 2008. All rights reserved.
3.2 Mechanical Specifications
Table 16. Baseband Frequency Response Figure 16. 48-pin eTQFP Land Pattern
CX24109_N_1 © NXP B.V. 2008. All rights reserved. Figure 17. 48-pin eTQFP Package Diagram
1.20 MAX
9.00 BSC
7.00 BSC
4.50 REF
1.00 REF
0.50 BSC
0.08 MAX
0.047 MAX
0.354 BSC
0.275 BSC
0.177 REF
0.039 REF
0.020 BSC
0.003 MAX
CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 38 NXP Semiconductors CX24109 Chapter 3: Parametric Data and Specifications
CX24109_N_1 © NXP B.V. 2008. All rights reserved. Product data sheet Rev. 01 — 13 November 2008 39 NXP Semiconductors CX24109 Digital Satellite Tuner Legal information Data sheet status [1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com. Definitions Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Disclaimers General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This docu ment contains the product specification.
NXP Semiconductors CX24109 Digital Satellite Tuner © NXP B.V. 2008. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 13 November 2008 Document identifier: CX24109_N_1 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 40