CSTCC8.00MGA0H6

ST72334J_03 STMICROELECTRONICS | Alldatasheet

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Rev. 2.5 April 2003 1/153 ST72334J/N, ST72314J/N, ST72124J 8-BIT MCU WITH SINGLE VOLTAGE FLASH MEMORY , ADC, 16-BIT TIMERS, SPI, SCI INTERFACES ■ Memories – 8K or 16K Program memory (ROM or single voltage FLASH) with read-out protection and in-situ programming (remote ISP) – 256 bytes EEPROM Data memory (with read- out protection option in ROM devices) – 384 or 512 bytes RAM ■ Clock, Reset and Supply Management – Enhanced reset system – Enhanced low voltage supply supervisor with 3 programmable levels – Clock sources: crystal/ceramic resonator os- cillators or RC oscillators, external clock, backup Clock Security System – 4 Power Saving Modes: Halt, Active-Halt, Wait and Slow – Beep and clock-out capabilities ■ Interrupt Management – 10 interrupt vectors plus TRAP and RESET – 15 external interrupt lines (4 vectors) ■ 44 or 32 I/O Ports – 44 or 32 multifunctional bidirectional I/O lines: – 21 or 19 alternate function lines – 12 or 8 high sink outputs ■ 4 Timers – Configurable watchdog timer – Realtime base – Two 16-bit timers with: 2 input captures (only one on timer A), 2 output compares (only one on timer A), External clock input on timer A, PWM and Pulse generator modes ■ 2 Communications Interfaces – SPI synchronous serial interface – SCI asynchronous serial interface (LIN com- patible) ■ 1 Analog Peripheral – 8-bit ADC with 8 input channels (6 only on ST72334Jx, not available on ST72124J2) ■ Instruction Set – 8-bit data manipulation – 63 basic instructions – 17 main addressing modes – 8 x 8 unsigned multiply instruction – True bit manipulation ■ Development Tools – Full hardware/software development package Device Summary TQFP44 10 x 10 PSDIP42PSDIP56 TQFP64 14 x 14 Features ST72124J2 ST72314J2 ST72314J4 ST72314N2 ST72314N4 ST72334J2 ST72334J4 ST72334N2 ST72334N4 Program memory - bytes 8K 8K 16K 8K 16K 8K 16K 8K 16K RAM (stack) - bytes 384 (256) 384 (256) 512 (256) 384 (256) 512 (256) 384 (256) 512 (256) 384 (256) 512 (256) EEPROM - bytes - - - -- 256 256 256 256 Peripherals Watchdog, Two 16-bit Timers, SPI, SCI -A D C Operating Supply 3.2V to 5.5V CPU Frequency Up to 8 MHz (with up to 16 MHz oscillator) Operating Temperature -40°C to +85°C (-40°C to +105/125°C optional)

ST72334J/N, ST72314J/N, ST72124J To obtain the most recent version of this datasheet, please check at www.st.com>products>technical literature>datasheet. Please also pay special attention to the Section “IMPORTANT NOTES” on page 151

ST72334J/N, ST72314J/N, ST72124J

1 PREAMBLE: ST72C334 VERSUS ST72E331 SPECIFICATION

New Features available on the ST72C334 ■ 8 or 16K FLASH/ROM with In-Situ Programming and Read-out protection ■ New ADC with a better accuracy and conversion time ■ New configurable Clock, Reset and Supply system ■ New power saving mode with real time base: Active Halt ■ Beep capability on PF1 ■ New interrupt source: Clock security system (CSS) or Main clock controller (MCC) ST72C334 I/O Configuration and Pinout ■ Same pinout as ST72E331 ■ PA6 and PA7 are true open drain I/O ports without pull-up (same as ST72E331) ■ PA3, PB3, PB4 and PF2 have no pull-up configuration (all I/Os present on TQFP44) ■ PA5:4, PC3:2, PE7:4 and PF7:6 have high sink capabilities (20mA on N-buffer, 2mA on P-buffer and pull-up). On the ST72E331, all these pads (except PA5:4) were 2mA push-pull pads without high sink capabilities. PA4 and PA5 were 20mA true open drains. New Memory Locations in ST72C334 ■ 20h: MISCR register becomes MISCR1 register (naming change) ■ 29h: new control/status register for the MCC module ■ 2Bh: new control/status register for the Clock, Reset and Supply control. This register replaces the WDGSR register keeping the WDOGF flag compatibility. ■ 40h: new MISCR2 register

2 INTRODUCTION

applications but without Data EEPROM. is in idle or standby state. Figure 1. General Block Diagram

3 PIN DESCRIPTION

Figure 2. 64-Pin TQFP Package Pinout (N versions)

Figure 3. 56-Pin SDIP Package Pinout (N versions)

36 VSS_1

34 PA3

29 PC6 / SCK / ISPCLK

Figure 4. 44-Pin TQFP and 42-Pin SDIP Package Pinouts (J versions)

22 PC6 / SCK / ISPCLK

Table 1. Device Pin Description

23 V DD_3 S Digital Main Supply Voltage

ST72334J/N, ST72314J/N, ST72124J

24 V SS_3 S Digital Ground Voltage

25 15 15 10 PF0/MCO I/O C T X ei1 X X Port F0 Main clock output (f OSC /2) 26 16 16 11 PF1/BEEP I/O C T X ei1 X X Port F1 Beep signal output 27 17 17 12 PF2 I/O C T X ei1 X X Port F2

28 NC Not Connected

29 18 18 13 PF4/OCMP1_A I/O C T X X X X Port F4 Timer A Output Compare 1

30 NC Not Connected

31 19 19 14 PF6 (HS)/ICAP1_A I/O C T HS X X X X Port F6 Timer A Input Capture 1 32 20 20 15 PF7 (HS)/EXTCLK_A I/O CT HS X X X X Port F7 Timer A External Clock Source 33 21 21 V DD_0 S Digital Main Supply Voltage 34 22 22 V SS_0 S Digital Ground Voltage 35 23 23 16 PC0/OCMP2_B I/O C T X X X X Port C0 Timer B Output Compare 2 36 24 24 17 PC1/OCMP1_B I/O C T X X X X Port C1 Timer B Output Compare 1 37 25 25 18 PC2 (HS)/ICAP2_B I/O C T HS X X X X Port C2 Timer B Input Capture 2 38 26 26 19 PC3 (HS)/ICAP1_B I/O C T HS X X X X Port C3 Timer B Input Capture 1 39 27 27 20 PC4/MISO I/O C T X X X X Port C4 SPI Master In / Slave Out Data 40 28 28 21 PC5/MOSI I/O C T X X X X Port C5 SPI Master Out / Slave In Data 41 29 29 22 PC6/SCK I/O C T X X X X Port C6 SPI Serial Clock 42 30 30 23 PC7/SS I/O C T X X X X Port C7 SPI Slave Select (active low) 43 31 PA0 I/O C T X ei0 X X Port A0 44 32 PA1 I/O C T X ei0 X X Port A1 45 33 PA2 I/O C T X ei0 X X Port A2 46 34 31 24 PA3 I/O C T X ei0 X X Port A3 47 35 32 25 VDD_1 S Digital Main Supply Voltage 48 36 33 26 VSS_1 S Digital Ground Voltage 49 37 34 27 PA4 (HS) I/O C T HS X X X X Port A4 50 38 35 28 PA5 (HS) I/O C T HS X X X X Port A5 51 39 36 29 PA6 (HS) I/O C T HS X T Port A6 52 40 37 30 PA7 (HS) I/O C T HS X T Port A7 53 41 38 31 ISPSEL I Must be tied low in user mode. In pro- gramming mode when available, this pin acts as In-Situ Programming mode se- lection. 54 42 39 32 RESET I/O C X X Top priority non maskable interrupt (ac- tive low)

55 NC Not Connected

57 43 40 33 VSS_3 S Digital Ground Voltage 58 44 41 34 OSC2 3) O Resonator oscillator inverter output or capacitor input for RC oscillator Pin n° Pin Name Type Level Port Main function (after reset) Alternate function TQFP64 SDIP56 QFP44 SDIP42 Input Output Input Output float wpu int ana OD PP

ST72334J/N, ST72314J/N, ST72124J Notes: 1. In the interrupt input column, “eix” defines the associated external interrupt vector. If the weak pull-up column (wpu) is merged with the interrupt column (int), then the I/O configuration is pull-up interrupt input, else the configuration is floating interrupt input. 2. In the open drain output column, “T” defines a true open drain I/O (P-Buffer and protection diode to VDD are not implemented). See Section 12 "I/O PORTS" on page 39 and Section 16.8 "I/O PORT PIN CHAR- ACTERISTICS" on page 128 for more details. 3. OSC1 and OSC2 pins connect a crystal or ceramic resonator, an external RC, or an external source to the on-chip oscillator see Section 3 "PIN DESCRIPTION" on page 7 and Section 16.5 "CLOCK AND TIM- ING CHARACTERISTICS" on page 116 for more details. 59 45 42 35 OSC1 3) I External clock input or Resonator oscilla- tor inverter input or resistor input for RC oscillator 60 46 43 36 V DD_3 S Digital Main Supply Voltage 61 47 44 37 PE0/TDO I/O C T X X X X Port E0 SCI Transmit Data Out 62 48 1 38 PE1/RDI I/O C T X X X X Port E1 SCI Receive Data In 63 NC Not Connected64 NC Pin n° Pin Name Type Level Port Main function (after reset) Alternate function TQFP64 SDIP56 QFP44 SDIP42 Input Output Input Output float wpu int ana OD PP

4 REGISTER & MEMORY MAP

Figure 5. Memory Map

256 Bytes Data EEPROM

384 Bytes RAM

512 Bytes RAM

8 KBytes

16 KBytes

Table 2. Hardware Register Map

ST72334J/N, ST72314J/N, ST72124J 002Ah WATCHDOG WDGCR Watchdog Control Register 7Fh R/W 002Bh CRSR Clock, Reset, Supply Control / Status Register 000x 000x R/W 002Ch Data-EEPROM EECSR Data-EEPROM Control/Status Register 00h R/W 002Dh 0030h Reserved Area (4 Bytes) 0031h 0032h 0033h 0034h 0035h 0036h 0037h 0038h 0039h 003Ah 003Bh 003Ch 003Dh 003Eh 003Fh TIMER A TACR2 TACR1 TASR TAIC1HR TAIC1LR TAOC1HR TAOC1LR TACHR TACLR TAACHR TAACLR TAIC2HR TAIC2LR TAOC2HR TAOC2LR Timer A Control Register 2 Timer A Control Register 1 Timer A Status Register Timer A Input Capture 1 High Register Timer A Input Capture 1 Low Register Timer A Output Compare 1 High Register Timer A Output Compare 1 Low Register Timer A Counter High Register Timer A Counter Low Register Timer A Alternate Counter High Register Timer A Alternate Counter Low Register Timer A Input Capture 2 High Register Timer A Input Capture 2 Low Register Timer A Output Compare 2 High Register Timer A Output Compare 2 Low Register 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only 3) R/W 3) R/W 3) 0040h MISCR2 Miscellaneous Register 2 00h R/W 0041h 0042h 0043h 0044h 0045h 0046h 0047h 0048h 0049h 004Ah 004Bh 004Ch 004Dh 004Eh 004Fh TIMER B TBCR2 TBCR1 TBSR TBIC1HR TBIC1LR TBOC1HR TBOC1LR TBCHR TBCLR TBACHR TBACLR TBIC2HR TBIC2LR TBOC2HR TBOC2LR Timer B Control Register 2 Timer B Control Register 1 Timer B Status Register Timer B Input Capture 1 High Register Timer B Input Capture 1 Low Register Timer B Output Compare 1 High Register Timer B Output Compare 1 Low Register Timer B Counter High Register Timer B Counter Low Register Timer B Alternate Counter High Register Timer B Alternate Counter Low Register Timer B Input Capture 2 High Register Timer B Input Capture 2 Low Register Timer B Output Compare 2 High Register Timer B Output Compare 2 Low Register 00h 00h xxh xxh xxh 80h 00h FFh FCh FFh FCh xxh xxh 80h 00h R/W R/W Read Only Read Only Read Only R/W R/W Read Only Read Only Read Only Read Only Read Only Read Only R/W R/W 0050h 0051h 0052h 0053h 0054h 0055h 0056h 0057h SCI SCISR SCIDR SCIBRR SCICR1 SCICR2 SCIERPR SCIETPR SCI Status Register SCI Data Register SCI Baud Rate Register SCI Control Register 1 SCI Control Register 2 SCI Extended Receive Prescaler Register Reserved area SCI Extended Transmit Prescaler Register C0h xxh 00xx xxxx xxh 00h 00h --- 00h Read Only R/W R/W R/W R/W R/W R/W Address Block Register Label Register Name Reset Status Remarks

ST72334J/N, ST72314J/N, ST72124J Legend : x=undefined, R/W=read/write Notes: 1. The contents of the I/O port DR registers are readable only in output configuration. In input configura- tion, the values of the I/O pins are returned instead of the DR register contents. 2. The bits corresponding to unavailable pins are forced to 1 by hardware, affecting accordingly the reset status value. These bits must always keep their reset value. 3. External pin not available. 0058h 006Fh Reserved Area (24 Bytes) 0070h 0071h ADC ADCDR ADCCSR Data Register Control/Status Register xxh 00h Read Only R/W 0072h to 007Fh Reserved Area (14 Bytes) Address Block Register Label Register Name Reset Status Remarks

5 FLASH PROGRAM MEMORY

5.1 INTRODUCTION

5.2 MAIN FEATURES

5.3 STRUCTURAL ORGANISATION

for storing both code and data constants. the reset and interrupt user vector area .

5.4 IN-SITU PROGRAMMING (ISP) MODE

ter the device is mounted on the application board. the ST7 Programming Specification. quence on the dedicated ISPSEL pin. cillator and application crystal circuit for example). board through a pull-down resistor. Figure 6. Typical Remote ISP Interface

5.5 MEMORY READ-OUT PROTECTION

6 DATA EEPROM

6.1 INTRODUCTION

basic access protocol described in this chapter.

6.2 MAIN FEATURES

Figure 7. EEPROM Block Diagram

6.3 MEMORY ACCESS

put on the data bus in less than 1 CPU clock cycle. set by software (the PGM bit remains cleared). Significant Bits of the address can change. It is not possible to read the latched data. This note is ilustrated by the Figure 9. Figure 8. Data EEPROM Programming Flowchart

6.4 POWER SAVING MODES

function in progress, and data may be corrupted.

6.5 ACCESS ERROR HANDLING

data on the bus will not be latched. Figure 9. Data EEPROM Programming Cycle

ST72334J/N, ST72314J/N, ST72124J DATA EEPROM (Cont’d)

6.6 REGISTER DESCRIPTION

CONTROL/STATUS REGISTER (CSR) Read/Write Reset Value: 0000 0000 (00h) Bit 7:3 = Reserved, forced by hardware to 0. Bit 2 = IE Interrupt enable This bit is set and cleared by software. It enables the Data EEPROM interrupt capability when the PGM bit is cleared by hardware. The interrupt request is automatically cleared when the software enters the interrupt routine. 0: Interrupt disabled 1: Interrupt enabled Bit 1 = LAT Latch Access Transfer This bit is set by software. It is cleared by hard- ware at the end of the programming cycle. It can only be cleared by software if PGM bit is cleared. 0: Read mode 1: Write mode Bit 0 = PGM Programming control and status This bit is set by software to begin the programming cycle. At the end of the programming cycle, this bit is cleared by hardware and an interrupt is generated if the ITE bit is set. 0: Programming finished or not yet started 1: Programming cycle is in progress Note: if the PGM bit is cleared during the program- ming cycle, the memory data is not guaranteed

00000 I E L A T P G M

ST72334J/N, ST72314J/N, ST72124J

7 DATA EEPROM Register Map and Reset Values

7.1 READ-OUT PROTECTION OPTION

The Data EEPROM can be optionally read-out protected in ST72334 ROM devices (see option list on page 146). ST72C334 Flash devices do not have this protection option. Address (Hex.) Register Label 76543210 002Ch EECSR Reset Value 00000 IE RWM PGM

8 CENTRAL PROCESSING UNIT

8.1 INTRODUCTION

8.2 MAIN FEATURES

8.3 CPU REGISTERS

temporary storage areas for data manipulation. (Program Counter High which is the MSB). Figure 10. CPU Registers

ST72334J/N, ST72314J/N, ST72124J CPU REGISTERS (Cont’d) CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1xxx The 8-bit Condition Code register contains the in- terrupt mask and four flags representative of the result of the instruction just executed. This register can also be handled by the PUSH and POP in- structions. These bits can be individually tested and/or con- trolled by specific instructions. Bit 4 = H Half carry. This bit is set by hardware when a carry occurs be- tween bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruc- tion. The H bit is useful in BCD arithmetic subrou- tines. Bit 3 = I Interrupt mask. This bit is set by hardware when entering in inter- rupt or by software to disable all interrupts except the TRAP software interrupt. This bit is cleared by software. 0: Interrupts are enabled. 1: Interrupts are disabled. This bit is controlled by the RIM, SIM and IRET in- structions and is tested by the JRM and JRNM in- structions. Note: Interrupts requested while I is set are latched and can be processed when I is cleared. By default an interrupt routine is not interruptable because the I bit is set by hardware at the start of the routine and reset by the IRET instruction at the end of the routine. If the I bit is cleared by software in the interrupt routine, pending interrupts are serviced regardless of the priority level of the cur- rent interrupt routine. Bit 2 = N Negative. This bit is set and cleared by hardware. It is repre- sentative of the result sign of the last arithmetic, logical or data manipulation. It is a copy of the 7th bit of the result. 0: The result of the last operation is positive or null. 1: The result of the last operation is negative (i.e. the most significant bit is a logic 1). This bit is accessed by the JRMI and JRPL instruc- tions. Bit 1 = Z Zero. This bit is set and cleared by hardware. This bit in- dicates that the result of the last arithmetic, logical or data manipulation is zero. 0: The result of the last operation is different from zero. 1: The result of the last operation is zero. This bit is accessed by the JREQ and JRNE test instructions. Bit 0 = C Carry/borrow. This bit is set and cleared by hardware and soft- ware. It indicates an overflow or an underflow has occurred during the last arithmetic operation. 0: No overflow or underflow has occurred. 1: An overflow or underflow has occurred. This bit is driven by the SCF and RCF instructions and tested by the JRC and JRNC instructions. It is also affected by the “bit test and branch”, shift and rotate instructions. 111HINZC

ways pointing to the next free location in the stack. popped from the stack (see Figure 11). mented and the context is pushed on the stack. and the context is popped from the stack. terrupt five locations in the stack area. Figure 11. Stack Manipulation Example

9 SUPPLY, RESET AND CLOCK MANAGEMENT

overview is shown in Figure 12. TICS" on page 107 for more details. Figure 12. Clock, Reset and Supply Block Diagram

9.1 LOW VOLTAGE DETECTOR (LVD)

well as the power-down keeping the ST7 in reset. ning and sinks current on the supply (hysteresis). The LVD function is illustrated in the Figure 13.

1. The LVD allows the device to be used without

any external RESET circuitry.

1. Three different reference levels are selectable

generated and cleared by software (writing zero). Figure 13. Low Voltage Detector vs Reset

9.2 RESET SEQUENCE MANAGER (RSM)

9.2.1 Introduction

ways kept low during the delay phase. dresses FFFEh-FFFFh in the ST7 memory map. taken place from the Reset state. Figure 14. RESET Sequence Phases Figure 15. Reset Block Diagram

4096 CLOCK CYCLES

9.2.2 Asynchronous External RESET pin

output with integrated RON weak pull-up resistor. electrical characteristics section for more details. is pulled low during at least tw(RSTL)out.

9.2.3 Internal Low Voltage Detection RESET

VDD <V IT- (falling edge) as shown in Figure 16.

9.2.4 Internal Watchdog RESET

Watchdog counter overflow is shown in Figure 16. low during at least tw(RSTL)out. Figure 16. RESET Sequences

9.3 MULTI-OSCILLATOR (MO)

electrical characteristics section for more details. the OSC1 pin while the OSC2 pin is tied to ground. cording to the selected oscillator. is fixed by the resistor and the capacitor values. frequency is in the range of several MHz. Table 3. ST7 Clock Sources

9.4 CLOCK SECURITY SYSTEM (CSS)

9.4.1 Clock Filter Control

frequency spikes on the ST7 main clock.

9.4.2 Safe Oscillator Control

quency back-up clock source (see Figure 17). SIE bit has been previously set.

9.4.3 Low Power Modes

9.4.4 Interrupts

mode if this mode is available in the MCU. Figure 17. Clock Filter Function and Safe Oscillator Function device to exit from Wait mode.

9.5 SUPPLY, RESET AND CLOCK REGISTER DESCRIPTION

Bit 7:5 = Reserved, always read as 0. Bit 3 = Reserved, always read as 0. set). It is set and cleared by software. CSSD bit value is forced to 0. flag description is given by the following table. software while an external reset can not. Table 4. Clock, Reset and Supply Register Map and Reset Values

000 LVD

ST72334J/N, ST72314J/N, ST72124J

10 INTERRUPTS

The ST7 core may be interrupted by one of two dif- ferent methods: maskable hardware interrupts as listed in the Interrupt Mapping Table and a non- maskable software interrupt (TRAP). The Interrupt processing flowchart is shown in Figure 18. The maskable interrupts must be enabled by clearing the I bit in order to be serviced. However, disabled interrupts may be latched and processed when they are enabled (see external interrupts subsection). Note: After reset, all interrupts are disabled. When an interrupt has to be serviced: – Normal processing is suspended at the end of the current instruction execution. – The PC, X, A and CC registers are saved onto the stack. – The I bit of the CC register is set to prevent addi- tional interrupts. – The PC is then loaded with the interrupt vector of the interrupt to service and the first instruction of the interrupt service routine is fetched (refer to the Interrupt Mapping Table for vector address- es). The interrupt service routine should finish with the IRET instruction which causes the contents of the saved registers to be recovered from the stack. Note: As a consequence of the IRET instruction, the I bit will be cleared and the main program will resume. Priority Management By default, a servicing interrupt cannot be inter- rupted because the I bit is set by hardware enter- ing in interrupt routine. In the case when several interrupts are simultane- ously pending, an hardware priority defines which one will be serviced first (see the Interrupt Map- ping Table). Interrupts and Low Power Mode All interrupts allow the processor to leave the WAIT low power mode. Only external and specifi- cally mentioned interrupts allow the processor to leave the HALT low power mode (refer to the “Exit from HALT“ column in the Interrupt Mapping Ta- ble).

10.1 NON MASKABLE SOFTWARE

This interrupt is entered when the TRAP instruc- tion is executed regardless of the state of the I bit. It will be serviced according to the flowchart on Figure 18.

10.2 EXTERNAL INTERRUPTS

External interrupt vectors can be loaded into the PC register if the corresponding external interrupt occurred and if the I bit is cleared. These interrupts allow the processor to leave the Halt low power mode. The external interrupt polarity is selected through the miscellaneous register or interrupt register (if available). An external interrupt triggered on edge will be latched and the interrupt request automatically cleared upon entering the interrupt service routine. If several input pins, connected to the same inter- rupt vector, are configured as interrupts, their sig- nals are logically NANDed before entering the edge/level detection block. Caution: The type of sensitivity defined in the Mis- cellaneous or Interrupt register (if available) ap- plies to the ei source. In case of a NANDed source (as described on the I/O ports section), a low level on an I/O pin configured as input with interrupt, masks the interrupt request even in case of rising- edge sensitivity.

10.3 PERIPHERAL INTERRUPTS

Different peripheral interrupt flags in the status register are able to cause an interrupt when they are active if both: – The I bit of the CC register is cleared. – The corresponding enable bit is set in the control register. If any of these two conditions is false, the interrupt is latched and thus remains pending. Clearing an interrupt request is done by: – Writing “0” to the corresponding bit in the status register or – Access to the status register while the flag is set followed by a read or write of an associated reg- ister. Note: the clearing sequence resets the internal latch. A pending interrupt (i.e. waiting for being en- abled) will therefore be lost if the clear sequence is executed.

Figure 18. Interrupt Processing Flowchart Table 5. Interrupt mapping

0 Not used FFFAh-FFFBh

1 MCC/RTC

6 Not used FFEEh-FFEFh

7 SPI SPI Peripheral Interrupts SPISR no FFECh-FFEDh

8 TIMER A TIMER A Peripheral Interrupts TASR FFEAh-FFEBh

9 TIMER B TIMER B Peripheral Interrupts TBSR FFE8h-FFE9h

10 SCI SCI Peripheral Interrupts SCISR FFE6h-FFE7h

11 Data-EEPROM Data EEPROM Interrupt EECSR FFE4h-FFE5h

13 FFE0h-FFE1h

11 POWER SAVING MODES

11.1 INTRODUCTION

Figure 19. Power Saving Mode Transitions

11.2 SLOW MODE

the available supply voltage. Figure 20. SLOW Mode Clock Transitions

11.3 WAIT MODE

sumption mode by stopping the CPU. the interrupt or Reset service routine. or an Interrupt occurs, causing it to wake up. Figure 21. WAIT Mode Flow-chart

1. Before servicing an interrupt, the CC register is

4096 CPU CLOCK CYCLE

11.4 ACTIVE-HALT AND HALT MODES

enable flag (OIE bit in MCCSR register).

11.4.1 ACTIVE-HALT MODE

more details on the MCCSR register). the CC register is cleared to enable interrupts. as external or auxiliary oscillator). HALT mode is provided by the oscillator interrupt. is active does not generate a RESET. than a defined delay in this power saving mode. Figure 22. ACTIVE-HALT Timing Overview Figure 23. ACTIVE-HALT Mode Flow-chart

1. Peripheral clocked with an external clock source
2. Only the MCC/RTC interrupt and some specific
3. Before servicing an interrupt, the CC register is

0 HALT mode

1 ACTIVE-HALT mode

11.4.2 HALT MODE

4096 CPU cycle delay is used to stabilize the os-

the reset vector which woke it up (see Figure 25). cluding the operation of the on-chip peripherals. Section 18.1 on page 144 for more details). Figure 24. HALT Timing Overview Figure 25. HALT Mode Flow-chart

1. WDGHALT is an option bit. See option byte sec-
2. Peripheral clocked with an external clock source
3. Only some specific interrupts can exit the MCU
4. Before servicing an interrupt, the CC register is

ST72334J/N, ST72314J/N, ST72124J

12 I/O PORTS

12.1 INTRODUCTION

The I/O ports offer different functional modes: – transfer of data through digital inputs and outputs and for specific pins: – external interrupt generation – alternate signal input/output for the on-chip pe- ripherals. An I/O port contains up to 8 pins. Each pin can be programmed independently as digital input (with or without interrupt generation) or digital output.

12.2 FUNCTIONAL DESCRIPTION

Each port has 2 main registers: – Data Register (DR) – Data Direction Register (DDR) and one optional register: – Option Register (OR) Each I/O pin may be programmed using the corre- sponding register bits in the DDR and OR regis- ters: bit X corresponding to pin X of the port. The same correspondence is used for the DR register. The following description takes into account the OR register, (for specific ports which do not pro- vide this register refer to the I/O Port Implementa- tion section). The generic I/O block diagram is shown in Figure 26

12.2.1 Input Modes

The input configuration is selected by clearing the corresponding DDR register bit. In this case, reading the DR register returns the digital value applied to the external I/O pin. Different input modes can be selected by software through the OR register. Notes: 1. Writing the DR register modifies the latch value but does not affect the pin status. 2. When switching from input to output mode, the DR register has to be written first to drive the cor- rect level on the pin as soon as the port is config- ured as an output. 3. Do not use read/modify/write instructions (BSET or BRES) to modify the DR register External interrupt function When an I/O is configured as Input with Interrupt, an event on this I/O can generate an external inter- rupt request to the CPU. Each pin can independently generate an interrupt request. The interrupt sensitivity is independently programmable using the sensitivity bits in the Mis- cellaneous register. Each external interrupt vector is linked to a dedi- cated group of I/O port pins (see pinout description and interrupt section). If several input pins are se- lected simultaneously as interrupt source, these are logically NANDed. For this reason if one of the interrupt pins is tied low, it masks the other ones. In case of a floating input with interrupt configura- tion, special care must be taken when changing the configuration (see Figure 27). The external interrupts are hardware interrupts, which means that the request latch (not accessible directly by the application) is automatically cleared when the corresponding interrupt vector is fetched. To clear an unwanted pending interrupt by software, the sensitivity bits in the Miscellane- ous register must be modified.

12.2.2 Output Modes

The output configuration is selected by setting the corresponding DDR register bit. In this case, writ- ing the DR register applies this digital value to the I/O pin through the latch. Then reading the DR reg- ister returns the previously stored value. Two different output modes can be selected by software through the OR register: Output push-pull and open-drain. DR register value and output pin status:

12.2.3 Alternate Functions

When an on-chip peripheral is configured to use a pin, the alternate function is automatically select- ed. This alternate function takes priority over the standard I/O programming. When the signal is coming from an on-chip periph- eral, the I/O pin is automatically configured in out- put mode (push-pull or open drain according to the peripheral). When the signal is going to an on-chip peripheral, the I/O pin must be configured in input mode. In this case, the pin state is also digitally readable by addressing the DR register. Note: Input pull-up configuration can cause unex- pected value at the input of the alternate peripheral input. When an on-chip peripheral use a pin as in- put and output, this pin has to be configured in in- put floating mode. DR Push-pull Open-drain 0V SS Vss 1V DD Floating

Figure 26. I/O Port General Block Diagram Table 6. I/O Port Mode Options vice against positive stress.

Table 7. I/O Port Configurations

1. When the I/O port is in input configuration and the associated alternate function is enabled as an output,

reading the DR register will read the alternate function output status.

1. When the I/O port is in output configuration and the associated alternate function is enabled as an input,

the alternate function reads the pin status given by the DR register content.

12.3 I/O PORT IMPLEMENTATION

such as spurious interrupt generation. Figure 27. Interrupt I/O Port State Transitions

ister is reset (RIM instruction). Table 8. Port Configuration cause the device to exit from WAIT mode. cause the device to exit from HALT mode.

ST72334J/N, ST72314J/N, ST72124J I/O PORTS (Cont’d)

12.5.1 Register Description

DATA REGISTER (DR) Port x Data Register PxDR with x = A, B, C, D, E or F. Read/Write Reset Value: 0000 0000 (00h) Bit 7:0 = D[7:0] Data register 8 bits. The DR register has a specific behaviour accord- ing to the selected input/output configuration. Writ- ing the DR register is always taken into account even if the pin is configured as an input; this allows to always have the expected level on the pin when toggling to output mode. Reading the DR register returns either the DR register latch content (pin configured as output) or the digital value applied to the I/O pin (pin configured as input). DATA DIRECTION REGISTER (DDR) Port x Data Direction Register PxDDR with x = A, B, C, D, E or F. Read/Write Reset Value: 0000 0000 (00h) Bit 7:0 = DD[7:0] Data direction register 8 bits. The DDR register gives the input/output direction configuration of the pins. Each bits is set and cleared by software. 0: Input mode 1: Output mode OPTION REGISTER (OR) Port x Option Register PxOR with x = A, B, C, D, E or F. Read/Write Reset Value: 0000 0000 (00h) Bit 7:0 = O[7:0] Option register 8 bits. For specific I/O pins, this register is not implement- ed. In this case the DDR register is enough to se- lect the I/O pin configuration. The OR register allows to distinguish: in input mode if the pull-up with interrupt capability or the basic pull-up configuration is selected, in output mode if the push-pull or open drain configuration is selected. Each bit is set and cleared by software. Input mode: 0: floating input 1: pull-up input with or without interrupt Output mode: 0: output open drain (with P-Buffer deactivated) 1: output push-pull D7 D6 D5 D4 D3 D2 D1 D0 DD7 DD6 DD5 DD4 DD3 DD2 DD1 DD0 O7 O6 O5 O4 O3 O2 O1 O0

Table 9. I/O Port Register Map and Reset Values 1) The bits corresponding to unavailable pins are forced to 1 by hardware, this affects the reset status value.

13 MISCELLANEOUS REGISTERS

terrupts or the I/O alternate functions.

13.1 I/O PORT INTERRUPT SENSITIVITY

ent external interrupt source sensitivities.

13.2 I/O PORT ALTERNATE FUNCTIONS

function while the SPI is active. Figure 28. Ext. Interrupt Sensitivity

ST72334J/N, ST72314J/N, ST72124J MISCELLANEOUS REGISTERS (Cont’d)

13.3 REGISTERS DESCRIPTION

MISCELLANEOUS REGISTER 1 (MISCR1) Read/Write Reset Value: 0000 0000 (00h) Bit 7:6 = IS1[1:0] ei2 and ei3 sensitivity The interrupt sensitivity, defined using the IS1[1:0] bits, is applied to the following external interrupts: can be written only when the I bit of the CC register is set to 1 (interrupt disabled). Bit 5 = MCO Main clock out selection This bit enables the MCO alternate function on the I/O port. It is set and cleared by software. 0: MCO alternate function disabled (I/O pin free for general-purpose I/O) 1: MCO alternate function enabled OSC /2 on I/O port) Note: To reduce power consumption, the MCO function is not active in ACTIVE-HALT mode. Bit 4:3 = IS2[1:0] ei0 and ei1 sensitivity The interrupt sensitivity, defined using the IS2[1:0] bits, is applied to the following external interrupts:- can be written only when the I bit of the CC register is set to 1 (interrupt disabled). Bit 2:1 = CP[1:0] CPU clock prescaler These bits select the CPU clock prescaler which is applied in the different slow modes. Their action is conditioned by the setting of the SMS bit. These two bits are set and cleared by software Bit 0 = SMS Slow mode select This bit is set and cleared by software. 0: Normal mode. fCPU = fOSC / 2 1: Slow mode. fCPU is given by CP1, CP0 See low power consumption mode and MCC chapters for more details. IS11 IS10 MCO IS21 IS20 CP1 CP0 SMS External Interrupt Sensitivity IS11 IS10 Falling edge & low level 0 0 Rising edge only 0 1 Falling edge only 1 0 Rising and falling edge 1 1 fCPU in SLOW mode CP1 CP0 fOSC / 4 0 0 fOSC / 8 1 0 fOSC / 16 0 1 fOSC / 32 1 1

These 2 bits select the PF1 pin beep capability. It is set and cleared by software. Table 10. Miscellaneous Register Map and Reset Values

14 ON-CHIP PERIPHERALS

14.1 WATCHDOG TIMER (WDG)

14.1.1 Introduction

14.1.2 Main Features

14.1.3 Functional Description

programmed by the user in 64 increments. Figure 29. Watchdog Block Diagram

ST72334J/N, ST72314J/N, ST72124J WATCHDOG TIMER (Cont’d) The application program must write in the CR reg- ister at regular intervals during normal operation to prevent an MCU reset. The value to be stored in the CR register must be between FFh and C0h (see Table 11 .Watchdog Timing (fCPU = 8 MHz)): – The WDGA bit is set (watchdog enabled) – The T6 bit is set to prevent generating an imme- diate reset – The T[5:0] bits contain the number of increments which represents the time delay before the watchdog produces a reset. Table 11.Watchdog Timing (f CPU = 8 MHz) Notes: Following a reset, the watchdog is disa- bled. Once activated it cannot be disabled, except by a reset. The T6 bit can be used to generate a software re- set (the WDGA bit is set and the T6 bit is cleared). If the watchdog is activated, the HALT instruction will generate a Reset.

14.1.4 Hardware Watchdog Option

If Hardware Watchdog is selected by option byte, the watchdog is always active and the WDGA bit in the CR is not used. Refer to the device-specific Option Byte descrip- tion.

14.1.5 Low Power Modes

14.1.6 Interrupts

None.

14.1.7 Register Description

CONTROL REGISTER (CR) Read/Write Reset Value: 0111 1111 (7Fh) Bit 7 = WDGA Activation bit. This bit is set by software and only cleared by hardware after a reset. When WDGA = 1, the watchdog can generate a reset. 0: Watchdog disabled 1: Watchdog enabled Note: This bit is not used if the hardware watch- dog option is enabled by option byte. Bit 6:0 = T[6:0] 7-bit timer (MSB to LSB). These bits contain the decremented value. A reset is produced when it rolls over from 40h to 3Fh (T6 becomes cleared). STATUS REGISTER (SR) Read/Write Reset Value*: 0000 0000 (00h) Bit 0 = WDOGF Watchdog flag. This bit is set by a watchdog reset and cleared by software or a power on/off reset. This bit is useful for distinguishing power/on off or external reset and watchdog reset. 0: No Watchdog reset occurred 1: Watchdog reset occurred * Only by software and power on/off reset Note: This register is not used in versions without LVD Reset. CR Register initial value WDG timeout period (ms) Max FFh 98.304 Min C0h 1.536 Mode Description WAIT No effect on Watchdog. HALT Immediate reset generation as soon as the HALT instruction is executed if the Watchdog is activated (WDGA bit is set). WDGA T6 T5 T4 T3 T2 T1 T0

Table 12. Watchdog Timer Register Map and Reset Values

14.2 MAIN CLOCK CONTROLLER WITH REAL TIME CLOCK TIMER (MCC/RTC)

14.2.1 Programmable CPU clock prescaler

14.2.2 Clock-out capability

pends the clock during ACTIVE-HALT mode.

14.2.3 Real time clock timer (RTC)

register: TB[1:0], OIE and OIF. Figure 30. Main Clock Controller (MCC/RTC) Block Diagram

Bit 7:4 = Reserved, always read as 0. base. They are set and cleared by software. use this time base as a real time clock. This bit set and cleared by software. unintentionally clearing the OIF bit.

14.2.4 Low Power Modes

14.2.5 Interrupts

1. The MCC/RTC interrupt allows to exit from AC-

TIVE-HALT mode, not from HALT mode. Table 13. MCC Register Map and Reset Values

0000 T B 1 T B 0 O I E O I F

No effect on MCC/RTC peripheral. set), the registers are frozen. MCC/RTC counter and registers are frozen.

ST72334J/N, ST72314J/N, ST72124J 14.3 16-BIT TIMER

14.3.1 Introduction

The timer consists of a 16-bit free-running counter driven by a programmable prescaler. It may be used for a variety of purposes, including measuring the pulse lengths of up to two input sig- nals (input capture) or generating up to two output waveforms (output compare and PWM ). Pulse lengths and waveform periods can be mod- ulated from a few microseconds to several milli- seconds using the timer prescaler and the CPU clock prescaler. Some ST7 devices have two on-chip 16-bit timers. They are completely independent, and do not share any resources. They are synchronized after a MCU reset as long as the timer clock frequen- cies are not modified. This description covers one or two 16-bit timers. In ST7 devices with two timers, register names are prefixed with TA (Timer A) or TB (Timer B).

14.3.2 Main Features

■ Programmable prescaler: fCPU divided by 2, 4 or 8. ■ Overflow status flag and maskable interrupt ■ External clock input (must be at least 4 times slower than the CPU clock speed) with the choice of active edge ■ Output compare functions with: – 2 dedicated 16-bit registers – 2 dedicated programmable signals – 2 dedicated status flags – 1 dedicated maskable interrupt ■ Input capture functions with: – 2 dedicated 16-bit registers – 2 dedicated active edge selection signals – 2 dedicated status flags – 1 dedicated maskable interrupt ■ Pulse Width Modulation mode (PWM) ■ One Pulse mode ■ 5 alternate functions on I/O ports (ICAP1, ICAP2, OCMP1, OCMP2, EXTCLK)* The Block Diagram is shown in Figure 31. *Note: Some timer pins may not be available (not bonded) in some ST7 devices. Refer to the device pin out description. When reading an input signal on a non-bonded pin, the value will always be ‘1’.

14.3.3 Functional Description

14.3.3.1 Counter

The main block of the Programmable Timer is a 16-bit free running upcounter and its associated 16-bit registers. The 16-bit registers are made up of two 8-bit registers called high & low. Counter Register (CR): – Counter High Register (CHR) is the most sig- nificant byte (MS Byte). – Counter Low Register (CLR) is the least sig- nificant byte (LS Byte). Alternate Counter Register (ACR) – Alternate Counter High Register (ACHR) is the most significant byte (MS Byte). – Alternate Counter Low Register (ACLR) is the least significant byte (LS Byte). These two read-only 16-bit registers contain the same value but with the difference that reading the ACLR register does not clear the TOF bit (Timer overflow flag), located in the Status register (SR). (See note at the end of paragraph titled 16-bit read sequence). Writing in the CLR register or ACLR register resets the free running counter to the FFFCh value. Both counters have a reset value of FFFCh (this is the only value which is reloaded in the 16-bit tim- er). The reset value of both counters is also FFFCh in One Pulse mode and PWM mode. The timer clock depends on the clock control bits of the CR2 register, as illustrated in Table 14 Clock Control Bits. The value in the counter register re- peats every 131072, 262144 or 524288 CPU clock cycles depending on the CC[1:0] bits. The timer frequency can be f CPU /2, fCPU /4, fCPU /8 or an external frequency.

Figure 31. Timer Block Diagram

ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) 16-bit Read Sequence: (from either the Counter Register or the Alternate Counter Register). The user must read the MS Byte first, then the LS Byte value is buffered automatically. This buffered value remains unchanged until the 16-bit read sequence is completed, even if the user reads the MS Byte several times. After a complete reading sequence, if only the CLR register or ACLR register are read, they re- turn the LS Byte of the count value at the time of the read. Whatever the timer mode used (input capture, out- put compare, One Pulse mode or PWM mode) an overflow occurs when the counter rolls over from FFFFh to 0000h then: – The TOF bit of the SR register is set. – A timer interrupt is generated if: – TOIE bit of the CR1 register is set and – I bit of the CC register is cleared. If one of these conditions is false, the interrupt re- mains pending to be issued as soon as they are both true. Clearing the overflow interrupt request is done in two steps: 1. Reading the SR register while the TOF bit is set. 2. An access (read or write) to the CLR register. Note: The TOF bit is not cleared by accessing the ACLR register. The advantage of accessing the ACLR register rather than the CLR register is that it allows simultaneous use of the overflow function and reading the free running counter at random times (for example, to measure elapsed time) with- out the risk of clearing the TOF bit erroneously. The timer is not affected by WAIT mode. In HALT mode, the counter stops counting until the mode is exited. Counting then resumes from the previous count (MCU awakened by an interrupt) or from the reset count (MCU awakened by a Reset).

14.3.3.2 External Clock

The external clock (where available) is selected if CC0=1 and CC1=1 in the CR2 register. The status of the EXEDG bit in the CR2 register determines the type of level transition on the exter- nal clock pin EXTCLK that will trigger the free run- ning counter. The counter is synchronised with the falling edge of the internal CPU clock. A minimum of four falling edges of the CPU clock must occur between two consecutive active edges of the external clock; thus the external clock fre- quency must be less than a quarter of the CPU clock frequency. is buffered Read At t0 Read Returns the buffered LS Byte value at t0At t0 +Δt Other instructions Beginning of the sequence Sequence completed LS Byte LS Byte MS Byte

ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d)

14.3.3.3 Input Capture

In this section, the index, i, may be 1 or 2 because there are 2 input capture functions in the 16-bit timer. The two input capture 16-bit registers (IC1R and IC2R) are used to latch the value of the free run- ning counter after a transition is detected by the ICAP i pin (see figure 5). The ICiR register is a read-only register. The active transition is software programmable through the IEDGi bit of Control Registers (CRi). Timing resolution is one count of the free running counter: (fCPU /CC[1:0]). Procedure: To use the input capture function, select the fol- lowing in the CR2 register: – Select the timer clock (CC[1:0]) (see Table 14 Clock Control Bits). – Select the edge of the active transition on the ICAP2 pin with the IEDG2 bit (the ICAP2 pin must be configured as a floating input or input with pull-up without interrupt if this configuration is available). And select the following in the CR1 register: – Set the ICIE bit to generate an interrupt after an input capture coming from either the ICAP1 pin or the ICAP2 pin – Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as a floating input or input with pull-up without interrupt if this configuration is available). When an input capture occurs: – The ICF i bit is set. – The ICiR register contains the value of the free running counter on the active transition on the ICAP i pin (see Figure 36). – A timer interrupt is generated if the ICIE bit is set and the I bit is cleared in the CC register. Other- wise, the interrupt remains pending until both conditions become true. Clearing the Input Capture interrupt request (i.e. clearing the ICF i bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. Notes: 1. After reading the ICiHR register, the transfer of input capture data is inhibited and ICFi will never be set until the ICiLR register is also read. 2. The ICiR register contains the free running counter value which corresponds to the most recent input capture. 3. The 2 input capture functions can be used together even if the timer also uses the 2 output compare functions. 4. In One Pulse mode and PWM mode only the input capture 2 function can be used. 5. The alternate inputs (ICAP1 & ICAP2) are always directly connected to the timer. So any transitions on these pins activate the input cap- ture function. Moreover if one of the ICAP i pin is configured as an input and the second one as an output, an interrupt can be generated if the user tog- gles the output pin and if the ICIE bit is set. This can be avoided if the input capture func- tion i is disabled by reading the ICiHR (see note 1). 6. The TOF bit can be used with an interrupt in order to measure events that exceed the timer range (FFFFh). MS Byte LS Byte ICiR IC iHR IC iLR

ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d)

14.3.3.4 Output Compare

In this section, the index, i, may be 1 or 2 because there are 2 output compare functions in the 16-bit timer. This function can be used to control an output waveform or indicate when a period of time has elapsed. When a match is found between the Output Com- pare register and the free running counter, the out- put compare function: – Assigns pins with a programmable value if the OC iE bit is set – Sets a flag in the status register – Generates an interrupt if enabled Two 16-bit registers Output Compare Register 1 (OC1R) and Output Compare Register 2 (OC2R) contain the value to be compared to the counter register each timer clock cycle. These registers are readable and writable and are not affected by the timer hardware. A reset event changes the OC iR value to 8000h. Timing resolution is one count of the free running counter: (fCPU/ CC[1:0]). Procedure: To use the output compare function, select the fol- lowing in the CR2 register: – Set the OCiE bit if an output is needed then the OCMP i pin is dedicated to the output compare i signal. – Select the timer clock (CC[1:0]) (see Table 14 Clock Control Bits). And select the following in the CR1 register: – Select the OLVL i bit to applied to the OCMPi pins after the match occurs. – Set the OCIE bit to generate an interrupt if it is needed. When a match is found between OCRi register and CR register: – OCF i bit is set. – The OCMP i pin takes OLVLi bit value (OCMPi pin latch is forced low during reset). – A timer interrupt is generated if the OCIE bit is set in the CR1 register and the I bit is cleared in the CC register (CC). The OC iR register value required for a specific tim- ing application can be calculated using the follow- ing formula: Where: Δ t = Output compare period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 de- pending on CC[1:0] bits, see Table 14 Clock Control Bits) If the timer clock is an external clock, the formula is: Where: Δ t = Output compare period (in seconds) fEXT = External timer clock frequency (in hertz) Clearing the output compare interrupt request (i.e. clearing the OCFi bit) is done by: 1. Reading the SR register while the OCFi bit is set. 2. An access (read or write) to the OCiLR register. The following procedure is recommended to pre- vent the OCFi bit from being set between the time it is read and the write to the OCiR register: – Write to the OCiHR register (further compares are inhibited). – Read the SR register (first step of the clearance of the OCFi bit, which may be already set). – Write to the OCiLR register (enables the output compare function and clears the OCFi bit). MS Byte LS Byte OC iRO C iHR OC iLR Δ OCiR = Δ t * fCPU PRESC Δ OCiR = Δt * fEXT

1. After a processor write cycle to the OCiHR reg-

iLR register is also written.

1. If the OCiE bit is not set, the OCMPi pin is a

could be generated if the OCIE bit is set.

1. When the timer clock is fCPU /2, OCFi and

ter value plus 1 (see Figure 39 on page 62).

1. The output compare functions can be used both
2. The value in the 16-bit OCiR register and the

waveform or establish a new elapsed timeout. Figure 37. Output Compare Block Diagram

16 BIT FREE RUNNING

ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d)

14.3.3.5 One Pulse Mode

One Pulse mode enables the generation of a pulse when an external event occurs. This mode is selected via the OPM bit in the CR2 register. The One Pulse mode uses the Input Capture1 function and the Output Compare1 function. Procedure: To use One Pulse mode: 1. Load the OC1R register with the value corre- sponding to the length of the pulse (see the for- mula in the opposite column). 2. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be ap- plied to the OCMP1 pin after the pulse. – Using the OLVL2 bit, select the level to be ap- plied to the OCMP1 pin during the pulse. – Select the edge of the active transition on the ICAP1 pin with the IEDG1 bit (the ICAP1 pin must be configured as floating input). 3. Select the following in the CR2 register: – Set the OC1E bit, the OCMP1 pin is then ded- icated to the Output Compare 1 function. – Set the OPM bit. – Select the timer clock CC[1:0] (see Table 14 Clock Control Bits). Then, on a valid event on the ICAP1 pin, the coun- ter is initialized to FFFCh and the OLVL2 bit is loaded on the OCMP1 pin, the ICF1 bit is set and the value FFFDh is loaded in the IC1R register. Because the ICF1 bit is set when an active edge occurs, an interrupt can be generated if the ICIE bit is set. Clearing the Input Capture interrupt request (i.e. clearing the ICF i bit) is done in two steps: 1. Reading the SR register while the ICFi bit is set. 2. An access (read or write) to the ICiLR register. The OC1R register value required for a specific timing application can be calculated using the fol- lowing formula: Where: t = Pulse period (in seconds) f CPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depend- ing on the CC[1:0] bits, see Table 14 Clock Control Bits) If the timer clock is an external clock the formula is: Where: t = Pulse period (in seconds) fEXT = External timer clock frequency (in hertz) When the value of the counter is equal to the value of the contents of the OC1R register, the OLVL1 bit is output on the OCMP1 pin (see Figure 40). Notes: 1. The OCF1 bit cannot be set by hardware in One Pulse mode but the OCF2 bit can generate an Output Compare interrupt. 2. When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one. 3. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. 4. The ICAP1 pin can not be used to perform input capture. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset each time a valid edge occurs on the ICAP1 pin and ICF1 can also generates interrupt if ICIE is set. 5. When One Pulse mode is used OC1R is dedi- cated to this mode. Nevertheless OC2R and OCF2 can be used to indicate that a period of time has elapsed but cannot generate an output waveform because the OLVL2 level is dedi- cated to One Pulse mode. event occurs Counter = OC1R OCMP1 = OLVL1 When When on ICAP1 One Pulse mode cycle OCMP1 = OLVL2 Counter is reset to FFFCh ICF1 bit is set OC iR Value = t * fCPU PRESC - 5 OCiR = t * fEXT -5

ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d)

14.3.3.6 Pulse Width Modulation Mode

Pulse Width Modulation (PWM) mode enables the generation of a signal with a frequency and pulse length determined by the value of the OC1R and OC2R registers. The Pulse Width Modulation mode uses the com- plete Output Compare 1 function plus the OC2R register, and so these functions cannot be used when the PWM mode is activated. Procedure To use Pulse Width Modulation mode: 1. Load the OC2R register with the value corre- sponding to the period of the signal using the formula in the opposite column. 2. Load the OC1R register with the value corre- sponding to the period of the pulse if OLVL1=0 and OLVL2=1, using the formula in the oppo- site column. 3. Select the following in the CR1 register: – Using the OLVL1 bit, select the level to be ap- plied to the OCMP1 pin after a successful comparison with OC1R register. – Using the OLVL2 bit, select the level to be ap- plied to the OCMP1 pin after a successful comparison with OC2R register. 4. Select the following in the CR2 register: – Set OC1E bit: the OCMP1 pin is then dedicat- ed to the output compare 1 function. – Set the PWM bit. – Select the timer clock (CC[1:0]) (see Table 14 Clock Control Bits). If OLVL1=1 and OLVL2=0, the length of the posi- tive pulse is the difference between the OC2R and OC1R registers. If OLVL1=OLVL2 a continuous signal will be seen on the OCMP1 pin. The OC iR register value required for a specific tim- ing application can be calculated using the follow- ing formula: Where: t = Signal or pulse period (in seconds) fCPU = CPU clock frequency (in hertz) PRESC = Timer prescaler factor (2, 4 or 8 depend- ing on CC[1:0] bits, see Table 14 Clock Control Bits) If the timer clock is an external clock the formula is: Where: t = Signal or pulse period (in seconds) fEXT = External timer clock frequency (in hertz) The Output Compare 2 event causes the counter to be initialized to FFFCh (See Figure 41) Notes: 1. After a write instruction to the OCiHR register, the output compare function is inhibited until the OC iLR register is also written. 2. The OCF1 and OCF2 bits cannot be set by hardware in PWM mode, therefore the Output Compare interrupt is inhibited. 3. The ICF1 bit is set by hardware when the coun- ter reaches the OC2R value and can produce a timer interrupt if the ICIE bit is set and the I bit is cleared. 4. In PWM mode the ICAP1 pin can not be used to perform input capture because it is discon- nected from the timer. The ICAP2 pin can be used to perform input capture (ICF2 can be set and IC2R can be loaded) but the user must take care that the counter is reset after each period and ICF1 can also generate an interrupt if ICIE is set. 5. When the Pulse Width Modulation (PWM) and One Pulse mode (OPM) bits are both set, the PWM mode is the only active one. Counter OCMP1 = OLVL2 Counter = OC2R OCMP1 = OLVL1 When When = OC1R Pulse Width Modulation cycle Counter is reset to FFFCh ICF1 bit is set OC iR Value = t * fCPU PRESC - 5 OCiR = t * fEXT -5

ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d)

14.3.4 Low Power Modes

14.3.5 Interrupts

Note: The 16-bit Timer interrupt events are connected to the same interrupt vector (see Interrupts chap- ter). These events generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction).

14.3.6 Summary of Timer modes

1) See note 4 in Section 14.3.3.5 "One Pulse Mode" on page 63 2) See note 5 in Section 14.3.3.5 "One Pulse Mode" on page 63 3) See note 4 in Section 14.3.3.6 "Pulse Width Modulation Mode" on page 65 Mode Description WAIT No effect on 16-bit Timer. Timer interrupts cause the device to exit from WAIT mode. HALT 16-bit Timer registers are frozen. In HALT mode, the counter stops counting until Halt mode is exited. Counting resumes from the previous count when the MCU is woken up by an interrupt with “exit from HALT mode” capability or from the counter reset value when the MCU is woken up by a RESET. If an input capture event occurs on the ICAP i pin, the input capture detection circuitry is armed. Consequent- ly, when the MCU is woken up by an interrupt with “exit from HALT mode” capability, the ICFi bit is set, and the counter value present when exiting from HALT mode is captured into the ICiR register. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt Input Capture 1 event/Counter reset in PWM mode ICF1 ICIE Yes No Input Capture 2 event ICF2 Yes No Output Compare 1 event (not available in PWM mode) OCF1 OCIE Yes No Output Compare 2 event (not available in PWM mode) OCF2 Yes No Timer Overflow event TOF TOIE Yes NoMODES AVAILABLE RESOURCES Input Capture 1 Input Capture 2 Output Compare 1 Output Compare 2 Input Capture (1 and/or 2) Yes Yes Yes Yes Output Compare (1 and/or 2) Yes Yes Yes Yes One Pulse mode No Not Recommended 1) No Partially 2) PWM Mode No Not Recommended 3) No No

ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d)

14.3.7 Register Description

Each Timer is associated with three control and status registers, and with six pairs of data registers (16-bit values) relating to the two input captures, the two output compares, the counter and the al- ternate counter. CONTROL REGISTER 1 (CR1) Read/Write Reset Value: 0000 0000 (00h) Bit 7 = ICIE Input Capture Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the ICF1 or ICF2 bit of the SR register is set. Bit 6 = OCIE Output Compare Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is generated whenever the OCF1 or OCF2 bit of the SR register is set. Bit 5 = TOIE Timer Overflow Interrupt Enable. 0: Interrupt is inhibited. 1: A timer interrupt is enabled whenever the TOF bit of the SR register is set. Bit 4 = FOLV2 Forced Output Compare 2. This bit is set and cleared by software. 0: No effect on the OCMP2 pin. 1: Forces the OLVL2 bit to be copied to the OCMP2 pin, if the OC2E bit is set and even if there is no successful comparison. Bit 3 = FOLV1 Forced Output Compare 1. This bit is set and cleared by software. 0: No effect on the OCMP1 pin. 1: Forces OLVL1 to be copied to the OCMP1 pin, if the OC1E bit is set and even if there is no suc- cessful comparison. Bit 2 = OLVL2 Output Level 2. This bit is copied to the OCMP2 pin whenever a successful comparison occurs with the OC2R reg- ister and OCxE is set in the CR2 register. This val- ue is copied to the OCMP1 pin in One Pulse mode and Pulse Width Modulation mode. Bit 1 = IEDG1 Input Edge 1. This bit determines which type of level transition on the ICAP1 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. Bit 0 = OLVL1 Output Level 1. The OLVL1 bit is copied to the OCMP1 pin when- ever a successful comparison occurs with the OC1R register and the OC1E bit is set in the CR2 register. ICIE OCIE TOIE FOLV2 FOLV1 OLVL2 IEDG1 OLVL1

Output Compare 1 Pin Enable. free for general-purpose I/O). 1: OCMP1 pin alternate function enabled. Output Compare 2 Pin Enable. free for general-purpose I/O). 1: OCMP2 pin alternate function enabled. 0: One Pulse mode is not active. contents of the OC1R register. Table 14. Clock Control Bits on the ICAP2 pin will trigger the capture. 0: A falling edge triggers the capture. 1: A rising edge triggers the capture. 0: A falling edge triggers the counter register. 1: A rising edge triggers the counter register.

ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) The three least significant bits are not used. Bit 7 = ICF1 Input Capture Flag 1. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP1 pin or the counter has reached the OC2R value in PWM mode. To clear this bit, first read the SR register, then read or write the low byte of the IC1R (IC1LR) register. Bit 6 = OCF1 Output Compare Flag 1. 0: No match (reset value). 1: The content of the free running counter matches the content of the OC1R register. To clear this bit, first read the SR register, then read or write the low byte of the OC1R (OC1LR) register. Bit 5 = TOF Timer Overflow Flag. 0: No timer overflow (reset value). 1: The free running counter has rolled over from FFFFh to 0000h. To clear this bit, first read the SR register, then read or write the low byte of the CR (CLR) register. Note: Reading or writing the ACLR register does not clear TOF. Bit 4 = ICF2 Input Capture Flag 2. 0: No input capture (reset value). 1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the SR register, then read or write the low byte of the IC2R (IC2LR) register. Bit 3 = OCF2 Output Compare Flag 2. 0: No match (reset value). 1: The content of the free running counter matches the content of the OC2R register. To clear this bit, first read the SR register, then read or write the low byte of the OC2R (OC2LR) register. Bit 2-0 = Reserved, forced by hardware to 0. INPUT CAPTURE 1 HIGH REGISTER (IC1HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the input capture 1 event). INPUT CAPTURE 1 LOW REGISTER (IC1LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the in- put capture 1 event). OUTPUT COMPARE 1 HIGH REGISTER (OC1HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. OUTPUT COMPARE 1 LOW REGISTER (OC1LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. ICF1 OCF1 TOF ICF2 OCF2 0 0 0 70 MSB LSB MSB LSB MSB LSB MSB LSB

ST72334J/N, ST72314J/N, ST72124J 16-BIT TIMER (Cont’d) OUTPUT COMPARE 2 HIGH REGISTER (OC2HR) Read/Write Reset Value: 1000 0000 (80h) This is an 8-bit register that contains the high part of the value to be compared to the CHR register. OUTPUT COMPARE 2 LOW REGISTER (OC2LR) Read/Write Reset Value: 0000 0000 (00h) This is an 8-bit register that contains the low part of the value to be compared to the CLR register. COUNTER HIGH REGISTER (CHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value. COUNTER LOW REGISTER (CLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after accessing the SR register clears the TOF bit. ALTERNATE COUNTER HIGH REGISTER (ACHR) Read Only Reset Value: 1111 1111 (FFh) This is an 8-bit register that contains the high part of the counter value. ALTERNATE COUNTER LOW REGISTER (ACLR) Read Only Reset Value: 1111 1100 (FCh) This is an 8-bit register that contains the low part of the counter value. A write to this register resets the counter. An access to this register after an access to SR register does not clear the TOF bit in SR register. INPUT CAPTURE 2 HIGH REGISTER (IC2HR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the high part of the counter value (transferred by the Input Capture 2 event). INPUT CAPTURE 2 LOW REGISTER (IC2LR) Read Only Reset Value: Undefined This is an 8-bit read only register that contains the low part of the counter value (transferred by the In- put Capture 2 event). MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB MSB LSB

Table 15. 16-Bit Timer Register Map and Reset Values

14.4 SERIAL PERIPHERAL INTERFACE (SPI)

14.4.1 Introduction

which devices may be either masters or slaves.

14.4.2 Main Features

■ Maximum slave mode frequency = fCPU /4. ■ Master mode fault protection capability.

14.4.3 General description

must be programmed with the same timing mode. Figure 42. Serial Peripheral Interface Master/Slave

Figure 43. Serial Peripheral Interface Block Diagram

ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d)

14.4.4 Functional Description

Figure 42 shows the serial peripheral interface (SPI) block diagram. This interface contains 3 dedicated registers: – A Control Register (CR) – A Status Register (SR) – A Data Register (DR) Refer to the CR, SR and DR registers in Section 14.4.7for the bit definitions.

14.4.4.1 Master Configuration

In a master configuration, the serial clock is gener- ated on the SCK pin. Procedure – Select the SPR0 & SPR1 bits to define the se- rial clock baud rate (see CR register). – Select the CPOL and CPHA bits to define one of the four relationships between the data transfer and the serial clock (see Figure 45). –T h e S S pin must be connected to a high level signal during the complete byte transmit se- quence. – The MSTR and SPE bits must be set (they re- main set only if the SS pin is connected to a high level signal). In this configuration the MOSI pin is a data output and to the MISO pin is a data input. Transmit sequence The transmit sequence begins when a byte is writ- ten the DR register. The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MOSI pin most significant bit first. When data transfer is complete: – The SPIF bit is set by hardware – An interrupt is generated if the SPIE bit is set and the I bit in the CCR register is cleared. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SR register while the SPIF bit is set 2. A read to the DR register. Note: While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read.

ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d)

14.4.4.2 Slave Configuration

In slave configuration, the serial clock is received on the SCK pin from the master device. The value of the SPR0 & SPR1 bits is not used for the data transfer. Procedure – For correct data transfer, the slave device must be in the same timing mode as the mas- ter device (CPOL and CPHA bits). See Figure 45. –T h e S S pin must be connected to a low level signal during the complete byte transmit se- quence. – Clear the MSTR bit and set the SPE bit to as- sign the pins to alternate function. In this configuration the MOSI pin is a data input and the MISO pin is a data output. Transmit Sequence The data byte is parallel loaded into the 8-bit shift register (from the internal bus) during a write cycle and then shifted out serially to the MISO pin most significant bit first. The transmit sequence begins when the slave de- vice receives the clock signal and the most signifi- cant bit of the data on its MOSI pin. When data transfer is complete: – The SPIF bit is set by hardware – An interrupt is generated if SPIE bit is set and I bit in CCR register is cleared. During the last clock cycle the SPIF bit is set, a copy of the data byte received in the shift register is moved to a buffer. When the DR register is read, the SPI peripheral returns this buffered value. Clearing the SPIF bit is performed by the following software sequence: 1. An access to the SR register while the SPIF bit is set. 2.A read to the DR register. Notes: While the SPIF bit is set, all writes to the DR register are inhibited until the SR register is read. The SPIF bit can be cleared during a second transmission; however, it must be cleared before the second SPIF bit in order to prevent an overrun condition (see Section 14.4.4.6). Depending on the CPHA bit, the SS pin has to be set to write to the DR register between each data byte transfer to avoid a write collision (see Section 14.4.4.4).

14.4.4.3 Data Transfer Format

ed do not interfere with the SPI transfer. by software, using the CPOL and CPHA bits. master and the slave device. be driven by the master device. clock edge before the capture clock edge. the occurrence of the second clock transition. currence of the first clock transition. each byte transmitted (see Figure 44). Figure 44. CPHA / SS Timing Diagram

Figure 45. Data Clock Timing Diagram Note: This figure should not be used as a replacement for parametric information. Refer to the Electrical Characteristics chapter.

14.4.4.4 Write Collision Error

the software write will be unsuccessful. nal MISO pin of the slave device. (SCK) is in the process of transfer. is set (the WCOL bit is a status flag only). Figure 46. Clearing the WCOL bit (Write Collision Flag) Software Sequence

ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d)

14.4.4.5 Master Mode Fault

Master mode fault occurs when the master device has its SS pin pulled low, then the MODF bit is set. Master mode fault affects the SPI peripheral in the following ways: – The MODF bit is set and an SPI interrupt is generated if the SPIE bit is set. – The SPE bit is reset. This blocks all output from the device and disables the SPI periph- eral. – The MSTR bit is reset, thus forcing the device into slave mode. Clearing the MODF bit is done through a software sequence: 1. A read or write access to the SR register while the MODF bit is set. 2. A write to the CR register. Notes: To avoid any multiple slave conflicts in the case of a system comprising several MCUs, the SS pin must be pulled high during the clearing se- quence of the MODF bit. The SPE and MSTR bits may be restored to their original state during or af- ter this clearing sequence. Hardware does not allow the user to set the SPE and MSTR bits while the MODF bit is set except in the MODF bit clearing sequence. In a slave device the MODF bit can not be set, but in a multi master configuration the device can be in slave mode with this MODF bit set. The MODF bit indicates that there might have been a multi-master conflict for system control and allows a proper exit from system operation to a re- set or default system state using an interrupt rou- tine.

14.4.4.6 Overrun Condition

An overrun condition occurs when the master de- vice has sent several data bytes and the slave de- vice has not cleared the SPIF bit issuing from the previous data byte transmitted. In this case, the receiver buffer contains the byte sent after the SPIF bit was last cleared. A read to the DR register returns this byte. All other bytes are lost. This condition is not detected by the SPI peripher- al.

14.4.4.7 Single Master and Multimaster Configurations

that time, thus disabling the slave devices. through the serial peripheral interface system. Figure 47. Single Master Configuration

ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d)

14.4.5 Low Power Modes

14.4.6 Interrupts

Note: The SPI interrupt events are connected to the same interrupt vector (see Interrupts chapter). They generate an interrupt if the corresponding Enable Control Bit is set and the interrupt mask in the CC register is reset (RIM instruction). Mode Description WAIT No effect on SPI. SPI interrupt events cause the device to exit from WAIT mode. HALT SPI registers are frozen. In HALT mode, the SPI is inactive. SPI operation resumes when the MCU is woken up by an interrupt with “exit from HALT mode” capability. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt SPI End of Transfer Event SPIF SPIE Yes No Master Mode Fault Event MODF Yes No

14.4.7 Register Description

Serial peripheral interrupt enable. This bit is set and cleared by software. Serial peripheral output enable. eral is not initially connected to the external pins. Bit 5 = SPR2 Divider Enable. set the baud rate. Refer to Table 16. 0: The steady state is a low value at the SCK pin. 1: The steady state is a high value at the SCK pin. This bit is set and cleared by software. Bit 1:0 = SPR[1 :0] Serial peripheral rate. These 2 bits have no effect in slave mode. Table 16. Serial Peripheral Baud Rate

ST72334J/N, ST72314J/N, ST72124J SERIAL PERIPHERAL INTERFACE (Cont’d) STATUS REGISTER (SR) Read Only Reset Value: 0000 0000 (00h) Bit 7 = SPIF Serial Peripheral data transfer flag. This bit is set by hardware when a transfer has been completed. An interrupt is generated if SPIE=1 in the CR register. It is cleared by a soft- ware sequence (an access to the SR register fol- lowed by a read or write to the DR register). 0: Data transfer is in progress or has been ap- proved by a clearing sequence. 1: Data transfer between the device and an exter- nal device has been completed. Note: While the SPIF bit is set, all writes to the DR register are inhibited. Bit 6 = WCOL Write Collision status. This bit is set by hardware when a write to the DR register is done during a transmit sequence. It is cleared by a software sequence (see Figure 46). 0: No write collision occurred 1: A write collision has been detected Bit 5 = Unused. Bit 4 = MODF Mode Fault flag. This bit is set by hardware when the SS pin is pulled low in master mode (see Section 14.4.4.5 "Master Mode Fault" on page 79). An SPI interrupt can be generated if SPIE=1 in the CR register. This bit is cleared by a software sequence (An ac- cess to the SR register while MODF=1 followed by a write to the CR register). 0: No master mode fault detected 1: A fault in master mode has been detected Bits 3-0 = Unused. DATA I/O REGISTER (DR) Read/Write Reset Value: Undefined The DR register is used to transmit and receive data on the serial bus. In the master device only a write to this register will initiate transmission/re- ception of another byte. Notes: During the last clock cycle the SPIF bit is set, a copy of the received data byte in the shift register is moved to a buffer. When the user reads the serial peripheral data I/O register, the buffer is actually being read. Warning: A write to the DR register places data directly into the shift register for transmission. A read to the the DR register returns the value lo- cated in the buffer and not the contents of the shift register (See Figure 43 ). SPIF WCOL - MODF - - - - D7 D6 D5 D4 D3 D2 D1 D0

Table 17. SPI Register Map and Reset Values

ST72334J/N, ST72314J/N, ST72124J

14.5 SERIAL COMMUNICATIONS INTERFACE (SCI)

14.5.1 Introduction

The Serial Communications Interface (SCI) offers a flexible means of full-duplex data exchange with external equipment requiring an industry standard NRZ asynchronous serial data format. The SCI offers a very wide range of baud rates using two baud rate generator systems.

14.5.2 Main Features

■ Full duplex, asynchronous communications ■ NRZ standard format (Mark/Space) ■ Dual baud rate generator systems ■ Independently programmable transmit and receive baud rates up to 250K baud using conventional baud rate generator and up to 500K baud using the extended baud rate generator. ■ Programmable data word length (8 or 9 bits) ■ Receive buffer full, Transmit buffer empty and End of Transmission flags ■ Two receiver wake-up modes: – Address bit (MSB) – Idle line ■ Muting function for multiprocessor configurations ■ LIN compatible (if MCU clock frequency tolerance ≤2%) ■ Separate enable bits for Transmitter and Receiver ■ Three error detection flags: – Overrun error – Noise error – Frame error ■ Five interrupt sources with flags: – Transmit data register empty – Transmission complete – Receive data register full – Idle line received – Overrun error detected

14.5.3 General Description

The interface is externally connected to another device by two pins (see Figure 2.): – TDO: Transmit Data Output. When the transmit- ter is disabled, the output pin returns to its I/O port configuration. When the transmitter is ena- bled and nothing is to be transmitted, the TDO pin is at high level. – RDI: Receive Data Input is the serial data input. Oversampling techniques are used for data re- covery by discriminating between valid incoming data and noise. Through this pins, serial data is transmitted and re- ceived as frames comprising: – An Idle Line prior to transmission or reception – A start bit – A data word (8 or 9 bits) least significant bit first – A Stop bit indicating that the frame is complete. This interface uses two types of baud rate generator: – A conventional type for commonly-used baud rates, – An extended type with a prescaler offering a very wide range of baud rates even with non-standard oscillator frequencies.

14.5.4 LIN Protocol support

For LIN applications where resynchronization is not required (application clock tolerance less than or equal to 2%) the LIN protocol can be efficiently implemented with this standard SCI.

Figure 48. SCI Block Diagram

14.5.5 Functional Description

for the definitions of each bit.

14.5.5.1 Serial Data Format

The TDO pin is in low state during the start bit. The TDO pin is in high state during the stop bit. tra “1” bit to acknowledge the start bit. Figure 49. Word length programming

ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d)

14.5.5.2 Transmitter

The transmitter can send data words of either 8 or 9 bits depending on the M bit status. When the M bit is set, word length is 9 bits and the 9th bit (the MSB) has to be stored in the T8 bit in the CR1 reg- ister. Character Transmission During an SCI transmission, data shifts out least significant bit first on the TDO pin. In this mode, the DR register consists of a buffer (TDR) between the internal bus and the transmit shift register (see Figure 1.). Procedure – Select the M bit to define the word length. – Select the desired baud rate using the BRR and the ETPR registers. – Set the TE bit to assign the TDO pin to the alter- nate function and to send a idle frame as first transmission. – Access the SR register and write the data to send in the DR register (this sequence clears the TDRE bit). Repeat this sequence for each data to be transmitted. Clearing the TDRE bit is always performed by the following software sequence: 1. An access to the SR register 2. A write to the DR register The TDRE bit is set by hardware and it indicates: – The TDR register is empty. – The data transfer is beginning. – The next data can be written in the DR register without overwriting the previous data. This flag generates an interrupt if the TIE bit is set and the I bit is cleared in the CCR register. When a transmission is taking place, a write in- struction to the DR register stores the data in the TDR register and which is copied in the shift regis- ter at the end of the current transmission. When no transmission is taking place, a write in- struction to the DR register places the data directly in the shift register, the data transmission starts, and the TDRE bit is immediately set. When a frame transmission is complete (after the stop bit or after the break frame) the TC bit is set and an interrupt is generated if the TCIE is set and the I bit is cleared in the CCR register. Clearing the TC bit is performed by the following software sequence: 1. An access to the SR register 2. A write to the DR register Note: The TDRE and TC bits are cleared by the same software sequence. Break Characters Setting the SBK bit loads the shift register with a break character. The break frame length depends on the M bit (see Figure 2.). As long as the SBK bit is set, the SCI send break frames to the TDO pin. After clearing this bit by software the SCI insert a logic 1 bit at the end of the last break frame to guarantee the recognition of the start bit of the next frame. Idle Characters Setting the TE bit drives the SCI to send an idle frame before the first data frame. Clearing and then setting the TE bit during a trans- mission sends an idle frame after the current word. Note: Resetting and setting the TE bit causes the data in the TDR register to be lost. Therefore the best time to toggle the TE bit is when the TDRE bit is set i.e. before writing the next byte in the DR.

ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d)

14.5.5.3 Receiver

The SCI can receive data words of either 8 or 9 bits. When the M bit is set, word length is 9 bits and the MSB is stored in the R8 bit in the CR1 reg- ister. Character reception During a SCI reception, data shifts in least signifi- cant bit first through the RDI pin. In this mode, DR register consists in a buffer (RDR) between the in- ternal bus and the received shift register (see Fig- ure 1.). Procedure – Select the M bit to define the word length. – Select the desired baud rate using the BRR and the ERPR registers. – Set the RE bit, this enables the receiver which begins searching for a start bit. When a character is received: – The RDRF bit is set. It indicates that the content of the shift register is transferred to the RDR. – An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register. – The error flags can be set if a frame error, noise or an overrun error has been detected during re- ception. Clearing the RDRF bit is performed by the following software sequence done by: 1. An access to the SR register 2. A read to the DR register. The RDRF bit must be cleared before the end of the reception of the next character to avoid an overrun error. Break Character When a break character is received, the SCI han- dles it as a framing error. Idle Character When a idle frame is detected, there is the same procedure as a data received character plus an in- terrupt if the ILIE bit is set and the I bit is cleared in the CCR register. Overrun Error An overrun error occurs when a character is re- ceived when RDRF has not been reset. Data can not be transferred from the shift register to the TDR register as long as the RDRF bit is not cleared. When a overrun error occurs: – The OR bit is set. – The RDR content will not be lost. – The shift register will be overwritten. – An interrupt is generated if the RIE bit is set and the I bit is cleared in the CCR register. The OR bit is reset by an access to the SR register followed by a DR register read operation. Noise Error Oversampling techniques are used for data recov- ery by discriminating between valid incoming data and noise. When noise is detected in a frame: – The NF is set at the rising edge of the RDRF bit. – Data is transferred from the Shift register to the DR register. – No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The NF bit is reset by a SR register read operation followed by a DR register read operation. Framing Error A framing error is detected when: – The stop bit is not recognized on reception at the expected time, following either a de-synchroni- zation or excessive noise. – A break is received. When the framing error is detected: – the FE bit is set by hardware – Data is transferred from the Shift register to the DR register. – No interrupt is generated. However this bit rises at the same time as the RDRF bit which itself generates an interrupt. The FE bit is reset by a SR register read operation followed by a DR register read operation.

Figure 50. SCI Baud Rate and Extended Prescaler Block Diagram

ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d)

14.5.5.4 Conventional Baud Rate Generation

The baud rate for the receiver and transmitter (Rx and Tx) are set independently and calculated as follows: with: PR = 1, 3, 4 or 13 (see SCP0 & SCP1 bits) (see SCT0, SCT1 & SCT2 bits) (see SCR0,SCR1 & SCR2 bits) All this bits are in the BRR register. Example: If f CPU is 8 MHz (normal mode) and if PR=13 and TR=RR=1, the transmit and receive baud rates are 19200 baud. Caution: The baud rate register (SCIBRR) MUST NOT be written to (changed or refreshed) while the transmitter or the receiver is enabled.

14.5.5.5 Extended Baud Rate Generation

The extended prescaler option gives a very fine tuning on the baud rate, using a 255 value prescal- er, whereas the conventional Baud Rate Genera- tor retains industry standard software compatibili- ty. The extended baud rate generator block diagram is described in the Figure 3.. The output clock rate sent to the transmitter or to the receiver will be the output from the 16 divider divided by a factor ranging from 1 to 255 set in the ERPR or the ETPR register. Note: the extended prescaler is activated by set- ting the ETPR or ERPR register to a value other than zero. The baud rates are calculated as fol- lows: with: ETPR = 1,..,255 (see ETPR register) ERPR = 1,.. 255 (see ERPR register)

14.5.5.6 Receiver Muting and Wake-up Feature

In multiprocessor configurations it is often desira- ble that only the intended message recipient should actively receive the full message contents, thus reducing redundant SCI service overhead for all non addressed receivers. The non addressed devices may be placed in sleep mode by means of the muting function. Setting the RWU bit by software puts the SCI in sleep mode: All the reception status bits can not be set. All the receive interrupt are inhibited. A muted receiver may be awakened by one of the following two ways: – by Idle Line detection if the WAKE bit is reset, – by Address Mark detection if the WAKE bit is set. Receiver wakes-up by Idle Line detection when the Receive line has recognised an Idle Frame. Then the RWU bit is reset by hardware but the IDLE bit is not set. Receiver wakes-up by Address Mark detection when it received a “1” as the most significant bit of a word, thus indicating that the message is an ad- dress. The reception of this particular word wakes up the receiver, resets the RWU bit and sets the RDRF bit, which allows the receiver to receive this word normally and to use it as an address word. Tx = (32 *PR)*TR fCPU Rx = (32*PR)*RR fCPU Tx = 16*ETPR fCPU Rx = 16*ERPR fCPU

ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d)

14.5.6 Low Power Modes

14.5.7 Interrupts

The SCI interrupt events are connected to the same interrupt vector (see Interrupts chapter). These events generate an interrupt if the corre- sponding Enable Control Bit is set and the inter- rupt mask in the CC register is reset (RIM instruc- tion). Mode Description WAIT No effect on SCI. SCI interrupts cause the device to exit from Wait mode. HALT SCI registers are frozen. In Halt mode, the SCI stops transmitting/receiving until Halt mode is exited. Interrupt Event Event Flag Enable Control Bit Exit from Wait Exit from Halt Transmit Data Register Empty TDRE TIE Yes No Transmission Complete TC TCIE Yes No Received Data Ready to be Read RDRF RIE Yes No Overrrun Error Detected OR Yes No Idle Line Detected IDLE ILIE Yes No

ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d)

14.5.8 Register Description

STATUS REGISTER (SR) Read Only Reset Value: 1100 0000 (C0h) Bit 7 = TDRE Transmit data register empty. This bit is set by hardware when the content of the TDR register has been transferred into the shift register. An interrupt is generated if the TIE =1 in the CR2 register. It is cleared by a software se- quence (an access to the SR register followed by a write to the DR register). 0: Data is not transferred to the shift register 1: Data is transferred to the shift register Note: data will not be transferred to the shift regis- ter as long as the TDRE bit is not reset. Bit 6 = TC Transmission complete. This bit is set by hardware when transmission of a frame containing Data, a Preamble or a Break is complete. An interrupt is generated if TCIE=1 in the CR2 register. It is cleared by a software se- quence (an access to the SR register followed by a write to the DR register). 0: Transmission is not complete 1: Transmission is complete Bit 5 = RDRF Received data ready flag. This bit is set by hardware when the content of the RDR register has been transferred into the DR register. An interrupt is generated if RIE=1 in the CR2 register. It is cleared by a software sequence (an access to the SR register followed by a read to the DR register). 0: Data is not received 1: Received data is ready to be read Bit 4 = IDLE Idle line detect. This bit is set by hardware when a Idle Line is de- tected. An interrupt is generated if the ILIE=1 in the CR2 register. It is cleared by a software se- quence (an access to the SR register followed by a read to the DR register). 0: No Idle Line is detected 1: Idle Line is detected Note: The IDLE bit will not be set again until the RDRF bit has been set itself (i.e. a new idle line oc- curs). This bit is not set by an idle line when the re- ceiver wakes up from wake-up mode. Bit 3 = OR Overrun error. This bit is set by hardware when the word currently being received in the shift register is ready to be transferred into the RDR register while RDRF=1. An interrupt is generated if RIE=1 in the CR2 reg- ister. It is cleared by a software sequence (an ac- cess to the SR register followed by a read to the DR register). 0: No Overrun error 1: Overrun error is detected Note: When this bit is set RDR register content will not be lost but the shift register will be overwritten. Bit 2 = NF Noise flag. This bit is set by hardware when noise is detected on a received frame. It is cleared by a software se- quence (an access to the SR register followed by a read to the DR register). 0: No noise is detected 1: Noise is detected Note: This bit does not generate interrupt as it ap- pears at the same time as the RDRF bit which it- self generates an interrupt. Bit 1 = FE Framing error. This bit is set by hardware when a de-synchroniza- tion, excessive noise or a break character is de- tected. It is cleared by a software sequence (an access to the SR register followed by a read to the DR register). 0: No Framing error is detected 1: Framing error or break character is detected Note: This bit does not generate interrupt as it ap- pears at the same time as the RDRF bit which it- self generates an interrupt. If the word currently being transferred causes both frame error and overrun error, it will be transferred and only the OR bit will be set. Bit 0 = Unused. TDRE TC RDRF IDLE OR NF FE -

ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) CONTROL REGISTER 1 (CR1) Read/Write Reset Value: Undefined Bit 7 = R8 Receive data bit 8. This bit is used to store the 9th bit of the received word when M=1. Bit 6 = T8 Transmit data bit 8. This bit is used to store the 9th bit of the transmit- ted word when M=1. Bit 4 = M Word length. This bit determines the word length. It is set or cleared by software. 0: 1 Start bit, 8 Data bits, 1 Stop bit 1: 1 Start bit, 9 Data bits, 1 Stop bit Bit 3 = WAKE Wake-Up method. This bit determines the SCI Wake-Up method, it is set or cleared by software. 0: Idle Line 1: Address Mark CONTROL REGISTER 2 (CR2) Read/Write Reset Value: 0000 0000 (00h) Bit 7 = TIE Transmitter interrupt enable. This bit is set and cleared by software. 0: interrupt is inhibited 1: An SCI interrupt is generated whenever TDRE=1 in the SR register. Bit 6 = TCIE Transmission complete interrupt ena- ble This bit is set and cleared by software. 0: interrupt is inhibited 1: An SCI interrupt is generated whenever TC=1 in the SR register Bit 5 = RIE Receiver interrupt enable. This bit is set and cleared by software. 0: interrupt is inhibited 1: An SCI interrupt is generated whenever OR=1 or RDRF=1 in the SR register Bit 4 = ILIE Idle line interrupt enable. This bit is set and cleared by software. 0: interrupt is inhibited 1: An SCI interrupt is generated whenever IDLE=1 in the SR register. Bit 3 = TE Transmitter enable. This bit enables the transmitter and assigns the TDO pin to the alternate function. It is set and cleared by software. 0: Transmitter is disabled, the TDO pin is back to the I/O port configuration. 1: Transmitter is enabled Note: during transmission, a “0” pulse on the TE bit (“0” followed by “1”) sends a preamble after the current word. Bit 2 = RE Receiver enable. This bit enables the receiver. It is set and cleared by software. 0: Receiver is disabled. 1: Receiver is enabled and begins searching for a start bit. Bit 1 = RWU Receiver wake-up. This bit determines if the SCI is in mute mode or not. It is set and cleared by software and can be cleared by hardware when a wake-up sequence is recognized. 0: Receiver in active mode 1: Receiver in mute mode Bit 0 = SBK Send break. This bit set is used to send break characters. It is set and cleared by software. 0: No break character is transmitted 1: Break characters are transmitted Note: If the SBK bit is set to “1” and then to “0”, the transmitter will send a BREAK word at the end of the current word. R8 T8 - M WAKE - - - TIE TCIE RIE ILIE TE RE RWU SBK

ST72334J/N, ST72314J/N, ST72124J SERIAL COMMUNICATIONS INTERFACE (Cont’d) DATA REGISTER (DR) Read/Write Reset Value: Undefined Contains the Received or Transmitted data char- acter, depending on whether it is read from or writ- ten to. The Data register performs a double function (read and write) since it is composed of two registers, one for transmission (TDR) and one for reception (RDR). The TDR register provides the parallel interface between the internal bus and the output shift reg- ister (see Figure 1.). The RDR register provides the parallel interface between the input shift register and the internal bus (see Figure 1.). BAUD RATE REGISTER (BRR) Read/Write Reset Value: 00xx xxxx (XXh) Bit 7:6= SCP[1:0] First SCI Prescaler These 2 prescaling bits allow several standard clock division ranges: Bit 5:3 = SCT[2:0] SCI Transmitter rate divisor These 3 bits, in conjunction with the SCP1 & SCP0 bits define the total division applied to the bus clock to yield the transmit rate clock in convention- al Baud Rate Generator mode. Note: this TR factor is used only when the ETPR fine tuning factor is equal to 00h; otherwise, TR is replaced by the ETPR dividing factor. Bit 2:0 = SCR[2:0] SCI Receiver rate divisor. These 3 bits, in conjunction with the SCP1 & SCP0 bits define the total division applied to the bus clock to yield the receive rate clock in conventional Baud Rate Generator mode. Note: this RR factor is used only when the ERPR fine tuning factor is equal to 00h; otherwise, RR is replaced by the ERPR dividing factor. DR7 DR6 DR5 DR4 DR3 DR2 DR1 DR0 SCP1 SCP0 SCT2 SCT1 SCT0 SCR2 SCR1 SCR0 PR Prescaling factor SCP1 SCP0 10 0 30 1 41 0 13 1 1 TR dividing factor SCT2 SCT1 SCT0 10 0 0 20 0 1 40 1 0 80 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1 RR dividing factor SCR2 SCR1 SCR0 10 0 0 20 0 1 40 1 0 80 1 1 16 1 0 0 32 1 0 1 64 1 1 0 128 1 1 1

sion factor for the receive circuit. sion factor for the transmit circuit. Table 18. SCI Register Map and Reset Values

14.6.1 Introduction

levels from up to 16 different sources. through a Control/Status Register.

14.6.2 Main Features

The block diagram is shown in Figure 51.

14.6.3 Functional Description

14.6.3.1 Analog Power Supply

loaded or badly decoupled power supply lines. Figure 51. ADC Block Diagram

14.6.3.2 Digital A/D Conversion Result

and never increases if the analog input does not. scale) without overflow indication. version result in the DR register is 00h. the conversion is stored in the ADCDR register.

14.6.3.3 A/D Conversion Phases

analog to digital conversion accuracy. pin in case of single input channel measurement.

14.6.3.4 Software Procedure

tions and to Figure 52 for the timings. sion of the selected channel. – The COCO bit is set by hardware. – No interrupt is generated. valid until the next conversion has ended. Figure 52. ADC Conversion Timings

14.6.4 Low Power Modes

and between single shot conversions.

14.6.5 Interrupts

curate conversions can be performed.

ST72334J/N, ST72314J/N, ST72124J 8-BIT A/D CONVERTER (ADC) (Cont’d)

14.6.6 Register Description

CONTROL/STATUS REGISTER (CSR) Read/Write Reset Value: 0000 0000 (00h) Bit 7 = COCO Conversion Complete This bit is set by hardware. It is cleared by soft- ware reading the result in the DR register or writing to the CSR register. 0: Conversion is not complete 1: Conversion can be read from the DR register Bit 6 = Reserved. must always be cleared. Bit 5 = ADON A/D Converter On This bit is set and cleared by software. 0: A/D converter is switched off 1: A/D converter is switched on Bit 4 = Reserved. must always be cleared. Bits 3:0 = CH[3:0] Channel Selection These bits are set and cleared by software. They select the analog input to convert. *Note: The number of pins AND the channel selec- tion varies according to the device. Refer to the de- vice pinout. DATA REGISTER (DR) Read Only Reset Value: 0000 0000 (00h) Bits 7:0 = D[7:0] Analog Converted Value This register contains the converted analog value in the range 00h to FFh. Note: Reading this register reset the COCO flag. COCO 0 ADON 0 CH3 CH2 CH1 CH0 Channel Pin* CH3 CH2 CH1 CH0 AIN0 0 0 0 0 AIN1 0 0 0 1 AIN2 0 0 1 0 AIN3 0 0 1 1 AIN4 0 1 0 0 AIN5 0 1 0 1 AIN6 0 1 1 0 AIN7 0 1 1 1 AIN8 1 0 0 0 AIN9 1 0 0 1 AIN10 1 0 1 0 AIN11 1 0 1 1 AIN12 1 1 0 0 AIN13 1 1 0 1 AIN14 1 1 1 0 AIN15 1 1 1 1 D7 D6 D5 D4 D3 D2 D1 D0

Table 19. ADC Register Map and Reset Values

15 INSTRUCTION SET

15.1 ST7 ADDRESSING MODES

Table 20. ST7 Addressing Mode Overview

ST72334J/N, ST72314J/N, ST72124J ST7 ADDRESSING MODES (Cont’d)

15.1.1 Inherent

All Inherent instructions consist of a single byte. The opcode fully specifies all the required informa- tion for the CPU to process the operation.

15.1.2 Immediate

Immediate instructions have two bytes, the first byte contains the opcode, the second byte con- tains the operand value.

15.1.3 Direct

In Direct instructions, the operands are referenced by their memory address. The direct addressing mode consists of two sub- modes: Direct (short) The address is a byte, thus requires only one byte after the opcode, but only allows 00 - FF address- ing space. Direct (long) The address is a word, thus allowing 64 Kbyte ad- dressing space, but requires 2 bytes after the op- code.

15.1.4 Indexed (No Offset, Short, Long)

In this mode, the operand is referenced by its memory address, which is defined by the unsigned addition of an index register (X or Y) with an offset. The indirect addressing mode consists of three sub-modes: Indexed (No Offset) There is no offset, (no extra byte after the opcode), and allows 00 - FF addressing space. Indexed (Short) The offset is a byte, thus requires only one byte af- ter the opcode and allows 00 - 1FE addressing space. Indexed (long) The offset is a word, thus allowing 64 Kbyte ad- dressing space and requires 2 bytes after the op- code.

15.1.5 Indirect (Short, Long)

The required data byte to do the operation is found by its memory address, located in memory (point- er). The pointer address follows the opcode. The indi- rect addressing mode consists of two sub-modes: Indirect (short) The pointer address is a byte, the pointer size is a byte, thus allowing 00 - FF addressing space, and requires 1 byte after the opcode. Indirect (long) The pointer address is a byte, the pointer size is a word, thus allowing 64 Kbyte addressing space, and requires 1 byte after the opcode. Inherent Instruction Function NOP No operation TRAP S/W Interrupt WFI Wait For Interrupt (Low Power Mode) HALT Halt Oscillator (Lowest Power Mode) RET Sub-routine Return IRET Interrupt Sub-routine Return SIM Set Interrupt Mask RIM Reset Interrupt Mask SCF Set Carry Flag RCF Reset Carry Flag RSP Reset Stack Pointer LD Load CLR Clear PUSH/POP Push/Pop to/from the stack INC/DEC Increment/Decrement TNZ Test Negative or Zero CPL, NEG 1 or 2 Complement MUL Byte Multiplication SLL, SRL, SRA, RLC, RRC Shift and Rotate Operations SWAP Swap Nibbles Immediate Instruction Function LD Load CP Compare BCP Bit Compare AND, OR, XOR Logical Operations ADC, ADD, SUB, SBC Arithmetic Operations

15.1.6 Indirect Indexed (Short, Long)

er address follows the opcode. and requires 1 byte after the opcode. and requires 1 byte after the opcode. Table 21. Instructions Supporting Direct,

15.1.7 Relative Mode (Direct, Indirect)

register value by adding an 8-bit signed offset to it. The offset follows the opcode.

ST72334J/N, ST72314J/N, ST72124J

15.2 INSTRUCTION GROUPS

The ST7 family devices use an Instruction Set consisting of 63 instructions. The instructions may be subdivided into 13 main groups as illustrated in the following table: Using a pre-byte The instructions are described with one to four bytes. In order to extend the number of available op- codes for an 8-bit CPU (256 opcodes), three differ- ent prebyte opcodes are defined. These prebytes modify the meaning of the instruction they pre- cede. The whole instruction becomes: PC-2 End of previous instruction PC-1 Prebyte PC Opcode PC+1 Additional word (0 to 2) according to the number of bytes required to compute the effective address These prebytes enable instruction in Y as well as indirect addressing modes to be implemented. They precede the opcode of the instruction in X or the instruction using direct addressing mode. The prebytes are: PDY 90 Replace an X based instruction using immediate, direct, indexed, or inherent addressing mode by a Y one. PIX 92 Replace an instruction using direct, di- rect bit, or direct relative addressing mode to an instruction using the corre- sponding indirect addressing mode. It also changes an instruction using X indexed addressing mode to an instruc- tion using indirect X indexed addressing mode. PIY 91 Replace an instruction using X indirect indexed addressing mode by a Y one. Load and Transfer LD CLR Stack operation PUSH POP RSP Increment/Decrement INC DEC Compare and Tests CP TNZ BCP Logical operations AND OR XOR CPL NEG Bit Operation BSET BRES Conditional Bit Test and Branch BTJT BTJF Arithmetic operations ADC ADD SUB SBC MUL Shift and Rotates SLL SRL SRA RLC RRC SWAP SLA Unconditional Jump or Call JRA JRT JRF JP CALL CALLR NOP RET Conditional Branch JRxx Interruption management TRAP WFI HALT IRET Condition Code Flag modification SIM RIM SCF RCF

ST72334J/N, ST72314J/N, ST72124J INSTRUCTION GROUPS (Cont’d) Mnemo Description Function/Example Dst Src H I N Z C ADC Add with Carry A = A + M + C A M H N Z C ADD Addition A = A + M A M H N Z C AND Logical And A = A . M A M N Z BCP Bit compare A, Memory tst (A . M) A M N Z BRES Bit Reset bres Byte, #3 M BSET Bit Set bset Byte, #3 M BTJF Jump if bit is false (0) btjf Byte, #3, Jmp1 M C BTJT Jump if bit is true (1) btjt Byte, #3, Jmp1 M C CALL Call subroutine CALLR Call subroutine relative CLR Clear reg, M 0 1 CP Arithmetic Compare tst(Reg - M) reg M N Z C CPL One Complement A = FFH-A reg, M N Z 1 DEC Decrement dec Y reg, M N Z HALT Halt 0 IRET Interrupt routine return Pop CC, A, X, PC H I N Z C INC Increment inc X reg, M N Z JRA Jump relative always JRT Jump relative JRF Never jump jrf * JRIH Jump if ext. interrupt = 1 JRIL Jump if ext. interrupt = 0 JRH Jump if H = 1 H = 1 ? JRNH Jump if H = 0 H = 0 ? JRM Jump if I = 1 I = 1 ? JRNM Jump if I = 0 I = 0 ? JRMI Jump if N = 1 (minus) N = 1 ? JRPL Jump if N = 0 (plus) N = 0 ? JREQ Jump if Z = 1 (equal) Z = 1 ? JRNE Jump if Z = 0 (not equal) Z = 0 ? JRC Jump if C = 1 C = 1 ? JRNC Jump if C = 0 C = 0 ? JRULT Jump if C = 1 Unsigned < JRUGE Jump if C = 0 Jmp if unsigned >= JRUGT Jump if (C + Z = 0) Unsigned >

ST72334J/N, ST72314J/N, ST72124J INSTRUCTION GROUPS (Cont’d) Mnemo Description Function/Example Dst Src H I N Z C JRULE Jump if (C + Z = 1) Unsigned <= LD Load dst <= src reg, M M, reg N Z MUL Multiply X,A = X * A A, X, Y X, Y, A 0 0 NEG Negate (2's compl) neg $10 reg, M N Z C NOP No Operation OR OR operation A = A + M A M N Z POP Pop from the Stack pop reg reg M pop CC CC M H I N Z C PUSH Push onto the Stack push Y M reg, CC RCF Reset carry flag C = 0 0 RET Subroutine Return RIM Enable Interrupts I = 0 0 RLC Rotate left true C C <= Dst <= C reg, M N Z C RRC Rotate right true C C => Dst => C reg, M N Z C RSP Reset Stack Pointer S = Max allowed SBC Subtract with Carry A = A - M - C A M N Z C SCF Set carry flag C = 1 1 SIM Disable Interrupts I = 1 1 SLA Shift left Arithmetic C <= Dst <= 0 reg, M N Z C SLL Shift left Logic C <= Dst <= 0 reg, M N Z C SRL Shift right Logic 0 => Dst => C reg, M 0 Z C SRA Shift right Arithmetic Dst7 => Dst => C reg, M N Z C SUB Subtraction A = A - M A M N Z C SWAP SWAP nibbles Dst[7..4] <=> Dst[3..0] reg, M N Z TNZ Test for Neg & Zero tnz lbl1 N Z TRAP S/W trap S/W interrupt 1 WFI Wait for Interrupt 0 XOR Exclusive OR A = A XOR M A M N Z

16 ELECTRICAL CHARACTERISTICS

16.1 PARAMETER CONDITIONS

16.1.1 Minimum and Maximum values

times the standard deviation (mean±3Σ).

16.1.2 Typical values

guidelines and are not tested.

16.1.3 Typical curves

given only as design guidelines and are not tested.

16.1.4 Loading capacitor

measurement are shown in Figure 53. Figure 53. Pin loading conditions

16.1.5 Pin input voltage

vice is described in Figure 54. Figure 54. Pin input voltage

ST72334J/N, ST72314J/N, ST72124J

16.2 ABSOLUTE MAXIMUM RATINGS

Stresses above those listed as “absolute maxi- mum ratings” may cause permanent damage to the device. This is a stress rating only and func- tional operation of the device under these condi- tions is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability.

16.2.1 Voltage Characteristics

16.2.2 Current Characteristics Notes:

1. Directly connecting the RESET and I/O pins to VDD or VSS could damage the device if an unintentional internal reset is generated or an unexpected change of the I/O configuration occurs (for example, due to a corrupted program counter). To guarantee safe operation, this connection has to be done through a pull-up or pull-down resistor (typical: 4.7kΩ for RESET , 10kΩ for I/Os). Unused I/O pins must be tied in the same way to VDD or VSS according to their reset configuration. 2. When the current limitation is not possible, the VIN absolute maximum rating must be respected, otherwise refer to IINJ(PIN) specification. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS . 3. All power (VDD ) and ground (VSS ) lines must always be connected to the external supply. 4. Negative injection disturbs the analog performance of the device. In particular, it induces leakage currents throughout the device including the analog inputs. To avoid undesirable effects on the analog functions, care must be taken: - Analog input pins must have a negative injection less than 0.8 mA (assuming that the impedance of the analog voltage is lower than the specified limits) - Pure digital pins must have a negative injection less than 1.6mA. In addition, it is recommended to inject the current as far as possible from the analog input pins. 5. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and negative injected currents (instantaneous values). These results are based on characterisation with ΣIINJ(PIN) maxi- mum current injection on four I/O port pins of the device. 6. True open drain I/O port pins do not accept positive injection. Symbol Ratings Maximum value Unit V DD - VSS Supply voltage 6.5 V VDDA - VSSA Analog Reference Voltage 6.5 VIN 1) & 2) Input voltage on true open drain pin V SS -0.3 to 6.5 Input voltage on any other pin V SS -0.3 to VDD +0.3 |ΔVDDx | and |ΔVSSx | Variations between different digital power pins 50 mVVDDX - VDDA |VSSA - VSSx | Variations between digital and analog power pins 50 VESD(HBM) Electro-static discharge voltage (Human Body Model)see Section 16.7.2 "Absolute Electri- cal Sensitivity" on page 124VESD(MM) Electro-static discharge voltage (Machine Model) Symbol Ratings Maximum value Unit IVDD Total current into VDD power lines (source) 3) 150 mA IVSS Total current out of VSS ground lines (sink) 3) 150 IIO Output current sunk by any standard I/O and control pin 25 Output current sunk by any high sink I/O pin 50 Output current source by any I/Os and control pin - 25 I INJ(PIN) 2) & 4) Injected current on ISPSEL pin ± 5 Injected current on RESET pin ± 5 Injected current on OSC1 and OSC2 pins ± 5 Injected current on any other pin 5) & 6) ± 5 ΣIINJ(PIN) 2) Total injected current (sum of all I/O and control pins) 5) ± 20

ST72334J/N, ST72314J/N, ST72124J ABSOLUTE MAXIMUM RATINGS (Cont’d)

16.2.3 Thermal Characteristics

TSTG Storage temperature range -65 to +150 °C TJ Maximum junction temperature (see Section 18 "DEVICE CONFIGURATION AND ORDER- ING INFORMATION" on page 144 )

16.3 OPERATING CONDITIONS

16.3.1 General Operating Conditions

Figure 55. fOSC Maximum Operating Frequency Versus VDD Supply Voltage for ROM devices 2) Figure 56. fOSC Maximum Operating Frequency Versus VDD Supply Voltage for FLASH devices 2)

1. Guaranteed by construction. A/D operation and resonator oscillator start-up are not guaranteed below 1MHz.
2. Operating conditions with T
3. FLASH programming tested in production at maximum TA with two different conditions: VDD =5.5V, fCPU =6MHz and

1 Suffix Version 0 70

6 Suffix Version -40 85

7 Suffix Version -40 105

3 Suffix Version -40 125

16.3.2 Operating Conditions with Low Voltage Detector (LVD)

Subject to general operating conditions for VDD , fOSC , and TA. Figure 57. High LVD Threshold Versus VDD and fOSC for FLASH devices 3) Figure 58. Medium LVD Threshold Versus VDD and fOSC for FLASH devices 3) Figure 59. Low LVD Threshold Versus VDD and fOSC for FLASH devices 2)4)

1. LVD typical data are based on TA=25°C. They are given only as design guidelines and are not tested.
2. Data based on characterization results, not tested in production.

DD rise time rate condition is needed to insure a correct device power-on and LVD reset. Not tested in production. on phase, but during a power down phase or voltage drop the device will function below this min. level.

16.4 SUPPLY CURRENT CHARACTERISTICS

16.4.1 RUN and SLOW Modes

Figure 63. Typical I

1. Data based on characterization results, tested in production at VDD max. and fCPU max.
2. CPU running with memory access, all I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals

in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled.

1. SLOW mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at VDD or

VSS (no load), all peripherals in reset state; clock input (OSC1) driven by external square wave, CSS and LVD disabled.

16.4.2 WAIT and SLOW WAIT Modes

Figure 65. Typical IDD in WAIT vs. fCPU Figure 66. Typical IDD in SLOW-WAIT vs. fCPU

1. Data based on characterization results, tested in production at VDD max. and fCPU max.
2. All I/O pins in input mode with a static value at VDD or VSS (no load), all peripherals in reset state; clock input (OSC1)

driven by external square wave, CSS and LVD disabled.

1. SLOW-WAIT mode selected with fCPU based on fOSC divided by 32. All I/O pins in input mode with a static value at

ST72334J/N, ST72314J/N, ST72124J SUPPLY CURRENT CHARACTERISTICS (Cont’d)

16.4.3 HALT and ACTIVE-HALT Modes

16.4.4 Supply and Clock Managers

The previous current consumption specified for the ST7 functional operating modes over tempera- ture range does not take into account the clock source current consumption. To get the total de- vice consumption, the two current values must be added (except for HALT mode).

16.4.5 On-Chip Peripherals

Notes: 1. Typical data are based on TA=25°C. 2. All I/O pins in input mode with a static value at VDD or VSS (no load), CSS and LVD disabled. Data based on charac- terization results, tested in production at VDD max. and fCPU max. 3. Data based on design simulation and/or technology characteristics, not tested in production. All I/O pins in input mode with a static value at VDD or VSS (no load); clock input (OSC1) driven by external square wave, LVD disabled. 4. Data based on characterization results, not tested in production. 5. Data based on characterization results done with the external components specified in Section 16.5.3 and Section 16.5.4, not tested in production. 6. As the oscillator is based on a current source, the consumption does not depend on the voltage. 7. Data based on a differential I DD measurement between reset configuration (timer counter running at fCPU /4) and timer counter stopped (selecting external clock capability). Data valid for one timer. 8. Data based on a differential IDD measurement between reset configuration and a permanent SPI master communica- tion (data sent equal to 55h). 9. Data based on a differential IDD measurement between reset configuration and continuous A/D conversions. Symbol Parameter Conditions Typ 1) Max Unit IDD Supply current in HALT mode 2) VDD =5.5V -40°C≤TA≤+85°C µA VDD =3.6V -40°C≤TA≤+85°C 6 Supply current in ACTIVE-HALT mode 3) 50 150 Symbol Parameter Conditions Typ 1) Max 4) Unit IDD(CK) Supply current of internal RC oscillator 500 750 µA Supply current of external RC oscillator 5) 525 750 Supply current of resonator oscillator 5) & 6) LP: Low power oscillator MP: Medium power oscillator MS: Medium speed oscillator HS: High speed oscillator 200 300 450 700 400 550 750 1000 Clock security system supply current 150 350 I DD(LVD) LVD supply current HALT mode 100 150 Symbol Parameter Conditions Typ Unit IDD(TIM) 16-bit Timer supply current 7) fCPU =8MHz VDD =3.4V 50 µA VDD =5.0V 150 IDD(SPI) SPI supply current 8) fCPU =8MHz VDD =3.4V 250 VDD =5.0V 350 IDD(ADC) ADC supply current when converting 9) fADC =4MHz VDD =3.4V 800 VDD =5.0V 1100

16.5 CLOCK AND TIMING CHARACTERISTICS

Subject to general operating conditions for VDD , fOSC , and TA.

16.5.1 General Timings

16.5.2 External Clock Source

Figure 67. Typical Application with an External Clock Source

1. Data based on typical application software.
2. Time measured between interrupt event and interrupt vector fetch. Δtc(INST) is the number of tCPU cycles needed to finish

the current instruction execution.

1. Data based on design simulation and/or technology characteristics, not tested in production.

16.5.3 Crystal and Ceramic Resonator Oscillators

16.5.3.1 Typical Crystal Resonators

Figure 68. Application with a Crystal Resonator

1. Resonator characteristics given by the crystal manufacturer.

quick VDD ramp-up from 0 to 5V (<50µs).

1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value.

Refer to crystal manufacturer for more details.

2 OSC2 driving current

16.5.3.2 Typical Ceramic Resonators

quick VDD ramp-up from 0 to 5V (<50µs). Figure 69. Application with Ceramic Resonator

1. Resonator characteristics given by the ceramic resonator manufacturer.

quick VDD ramp-up from 0 to 5V (<50µs).

1. The oscillator selection can be optimized in terms of supply current using an high quality resonator with small RS value.

Refer to Table 22 and Table 23 and to the ceramic resonator manufacturer’s documentation for more details.

Table 22. Typical Ceramic Resonators Table 23. Resonator Frequency Correlation Factor

1. Values in parentheses refer to the capacitors integrated in the resonator

1 CSB1000JA 100 100

2 CSTS0200MGA06

4 CSTS0400MGA06

8 CSTS0800MGA06

16.5.4 RC Oscillators

Figure 70. Typical Application with RC oscillator Figure 71. Typical Internal RC Oscillator Figure 72. Typical External RC Oscillator

1. Data based on characterization results.
2. Guaranteed frequency range with the specified C

EX and REX ranges taking into account the device process variation. Data based on design simulation.

1. Data based on characterization results done with VDD nominal at 5V, not tested in production.
2. REX must have a positive temperature coefficient (ppm/°C), carbon resistors should therefore not be used.
3. Important: when no external CEX is applied, the capacitance to be considered is the global parasitic capacitance which

trying out several resistor values.

16.5.5 Clock Security System (CSS)

Figure 73. Typical Safe Oscillator Frequencies

1. Data based on characterization results, tested in production between 90KHz and 600KHz.

OSC signal. See functional description in Section 9.4 on page 31 for more details.

ST72334J/N, ST72314J/N, ST72124J

16.6 MEMORY CHARACTERISTICS

16.6.1 RAM and Hardware Registers

16.6.2 EEPROM Data Memory

16.6.3 FLASH Program Memory

Notes: 1. Minimum VDD supply voltage without losing data stored in RAM (in HALT mode or under RESET) or in hardware reg- isters (only in HALT mode). Guaranteed by construction, not tested in production. 2. Data based on characterization results, tested in production at TA=25°C. 3. Up to 16 bytes can be programmed at a time for a 4kBytes FLASH block (then up to 32 bytes at a time for an 8k device) 4. The data retention time increases when the T A decreases. 5. Data based on reliability test results and monitored in production. Symbol Parameter Conditions Min Typ Max Unit VRM Data retention mode 1) HALT mode (or RESET) 1.6 V Symbol Parameter Conditions Min Typ Max Unit tprog Programming time for 1~16 bytes 3) -40°C≤TA≤+85°C 20 ms -40°C≤TA≤+125°C 25 tret Data retention 5) TA=+55°C 4) 20 Years N RW Write erase cycles 5) TA=+25°C 300 000 Cycles Symbol Parameter Conditions Min Typ Max Unit TA(prog) Programming temperature range 2) 02 5 7 0 °C tprog Programming time for 1~16 bytes 3) TA=+25°C 8 25 ms Programming time for 4 or 8kBytesTA=+25°C 2.1 6.4 sec tret Data retention 5) TA=+55°C 4) 20 years N RW Write erase cycles 5) TA=+25°C 100 cycles

16.7 EMC CHARACTERISTICS

sis during product characterization.

16.7.1 Functional EMS

until a failure occurs (indicated by the LEDs). conforms with the IEC 1000-4-2 standard. Figure 74. EMC Recommended star network power supply connection

1. Data based on characterization results, not tested in production.
2. The suggested 10µF and 0.1µF decoupling capacitors on the power supply lines are proposed as a good price vs. EMC

dations are given in other sections (I/Os, RESET, OSCx pin characteristics).

16.7.2 Absolute Electrical Sensitivity

fer to the AN1181 ST7 application note.

16.7.2.1 Electro-Static Discharge (ESD)

conforms to the JESD22-A114A/A115A standard. See Figure 75 and the following test sequences. – S1 switches position from generator to R. prior to the delivery of the next pulse. – S1 switches position from generator to ST7. prior to the delivery of the next pulse. sures a slow discharge of the ST7. Figure 75. Typical Equivalent ESD Circuits

1. Data based on characterization results, not tested in production.

16.7.2.2 Static and Dynamic Latch-Up

on 10 parts to assess the latch-up performance. refer to the AN1181 ST7 application note.

16.7.2.3 Designing hardened software to avoid

SET pin or the Oscillator pins for 1 second. Figure 76. Simplified Diagram of the ESD Generator for DLU

1. Class description: A Class is an STMicroelectronics internal specification. All its limits are higher than the JEDEC spec-

JEDEC criteria (international standard).

1. Schaffner NSG435 with a pointed test finger.

16.7.3 ESD Pin Protection Strategy

or heating within their structure. Figure 77. Positive Stress on a Standard Pad vs. VSS Figure 78. Negative Stress on a Standard Pad vs. VDD

16.8 I/O PORT PIN CHARACTERISTICS

16.8.1 General Characteristics

Subject to general operating conditions for VDD , fOSC , and TA unless otherwise specified. Figure 82. Two typical Applications with unused I/O Pin Figure 83. Typical IPU vs. VDD with VIN=V SS

1. Unless otherwise specified, typical data are based on TA=25°C and VDD =5V.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. Configuration not recommended, all unused pins must be kept at a fixed voltage: using the output mode of the I/O for

characteristics, not tested in production. scribed in Figure 83). This data is based on characterization results, tested in production at VDD max.

1. Data based on characterization results, not tested in production.
2. To generate an external interrupt, a minimum pulse width has to be applied on an I/O port pin configured as an external

16.8.2 Output Driving Current

Subject to general operating conditions for VDD , fOSC , and TA unless otherwise specified. Figure 84. Typical VOL at VDD =5V (standard) Figure 85. Typical VOL at VDD =5V (high-sink) Figure 86. Typical VOH at VDD =5V

1. The IIO current sunk must always respect the absolute maximum rating specified in Section 16.2.2 and the sum of IIO

(I/O ports and control pins) must not exceed IVSS .

1. The IIO current sourced must always respect the absolute maximum rating specified in Section 16.2.2 and the sum of

IIO (I/O ports and control pins) must not exceed IVDD . True open drain I/O pins does not have VOH .

16.9 CONTROL PIN CHARACTERISTICS

16.9.1 Asynchronous RESET Pin

Subject to general operating conditions for VDD , fOSC , and TA unless otherwise specified. Figure 90. Typical Application with RESET pin 8)

1. Unless otherwise specified, typical data are based on TA=25°C and VDD =5V.
2. Data based on characterization results, not tested in production.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.

(I/O ports and control pins) must not exceed IVSS .

1. The RON pull-up equivalent resistor is based on a resistive transistor (corresponding ION current characteristics de-

scribed in Figure 91). This data is based on characterization results, not tested in production.

1. To guarantee the reset of the device, a minimum pulse has to be applied to RESET pin. All short pulses applied on

RESET pin with a duration below th(RSTL)in can be ignored.

1. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially in a noisy
2. The output of the external reset circuit must have an open-drain output to drive the ST7 reset pad. Otherwise the device

can be damaged when the ST7 generates an internal reset (LVD or watchdog).

16.9.2 ISPSEL Pin

Subject to general operating conditions for VDD , fOSC , and TA unless otherwise specified. Figure 94. Two typical Applications with ISPSEL Pin 2)

1. Data based on design simulation and/or technology characteristics, not tested in production.
2. When the ISP Remote mode is not required by the application ISPSEL pin must be tied to VSS .

ST72334J/N, ST72314J/N, ST72124J

16.10 TIMER PERIPHERAL CHARACTERISTICS

Subject to general operating conditions for VDD , fOSC , and TA unless otherwise specified. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (output compare, input capture, external clock, PWM output...).

16.10.1 Watchdog Timer

16.10.2 16-Bit Timer Symbol Parameter Conditions Min Typ Max Unit tw(WDG) Watchdog time-out duration 12,288 786,432 t CPU fCPU =8MHz 1.54 98.3 ms Symbol Parameter Conditions Min Typ Max Unit tw(ICAP)in Input capture pulse time 1 t CPU tres(PWM) PWM resolution time 2t CPU fCPU =8MHz 250 ns fEXT Timer external clock frequency 0 f CPU /4 MHz fPWM PWM repetition rate 0 f CPU /4 MHz ResPWM PWM resolution 16 bit

16.11 COMMUNICATION INTERFACE CHARACTERISTICS

16.11.1 SPI - Serial Peripheral Interface

fOSC , and TA unless otherwise specified. Figure 95. SPI Slave Timing Diagram with CPHA=0 3)

1. Data based on design simulation and/or characterisation results, not tested in production.
2. When no communication is on-going the data output line of the SPI (MOSI in master mode, MISO in slave mode) has

its alternate function capability released. In this case, the pin status depends on the I/O port configuration.

1. Measurement points are done at CMOS levels: 0.3xVDD and 0.7xVDD .

ST72334J/N, ST72314J/N, ST72124J COMMUNICATIONS INTERFACE CHARACTERISTICS (Cont’d)

16.11.2 SCI - Serial Communications Interface

Subject to general operating condition for VDD , fO- SC , and TA unless otherwise specified. Refer to I/O port characteristics for more details on the input/output alternate function characteristics (RDI and TDO). Symbol Parameter Conditions Standard Baud Rate Unit fCPU Accuracy vs. Standard Prescaler fTx fRx Communication frequency 8MHz ~0.16% Conventional Mode TR (or RR)=64, PR=13 TR (or RR)=16, PR=13 TR (or RR)= 8, PR=13 TR (or RR)= 4, PR=13 TR (or RR)= 2, PR=13 TR (or RR)= 8, PR= 3 TR (or RR)= 1, PR=13 300 1200 2400 4800 9600 10400 19200 ~300.48 ~1201.92 ~2403.84 ~4807.69 ~9615.38 ~10416.67 ~19230.77 Hz Extended Mode ETPR (or ERPR) = 13 38400 ~38461.54 ~0.79% Extended Mode ETPR (or ERPR) = 35 14400 ~14285.71

Subject to general operating conditions for VDD , fOSC , and TA unless otherwise specified. Figure 98. Typical Application with ADC

1. Unless otherwise specified, typical data are based on TA=25°C and VDD -VSS =5V. They are given only as design guide-
2. When VDDA and VSSA pins are not available on the pinout, the ADC refer to VDD and VSS .
3. Any added external serial resistor will downgrade the ADC accuracy (especially for resistance greater than 10kΩ ). Data

based on characterization results, not tested in production.

1. The stabilization time of the AD converter is masked by the first tLOAD . The first conversion after the enable is then

Figure 99. ADC Accuracy Characteristics

1. ADC Accuracy vs. Negative Injection Current:

DD supply, and worst case temperature.

1. Data based on characterization results with TA=25°C.
2. Data based on characterization results over the whole temperature range.

between the actual and the ideal transfer curves. transition and the first ideal one. transition and the last actual one. between actual steps and the ideal one.

17 PACKAGE CHARACTERISTICS

17.1 PACKAGE MECHANICAL DATA

Figure 100. 64-Pin Thin Quad Flat Package Figure 101. 56-Pin Plastic Dual In-Line Package, Shrink 600-mil Width

ST72334J/N, ST72314J/N, ST72124J and PPORT is the port power dissipation determined by the user. 2. The average chip-junction temperature can be obtained from the formula TJ = TA + PD x RthJA. Symbol Ratings Value Unit R thJA Package thermal resistance (junction to ambient) TQFP64 SDIP56 TQFP44 SDIP42 °C/W P D Power dissipation 1) 500 mW TJmax Maximum junction temperature 2) 150 °C

17.2 SOLDERING AND GLUEABILITY INFORMATION

as design guidelines in Figure 105 and Figure 106. Figure 105. Recommended Wave Soldering Profile (with 37% Sn and 63% Pb) Figure 106. Recommended Reflow Soldering Oven Profile (MID JEDEC)

18 DEVICE CONFIGURATION AND ORDERING INFORMATION

parts contain the code supplied by the customer. while the ROM devices are factory-configured.

18.1 OPTION BYTES

ration of the microcontroller to be selected. Bit 7:2 = Reserved, must always be 1. whole memory (not including the option bytes). can be selected in the Option List (see page 146). main oscillator as shown in Table 24. lected threshold as shown in Table 25. This option bit selects the watchdog type. Table 24. Main Oscillator Configuration Table 25. LVD Threshold Configuration

0 LVD1 LVD0 WDG

18.2 TRANSFER OF CUSTOMER CODE

used bytes must be set to FFh. Figure 107. ROM Factory Coded Device Types Figure 108. FLASH User Programmable Device Types

ST72334J/N, ST72314J/N, ST72124J MICROCONTROLLER OPTION LIST *The ROM or FASTROM code name is assigned by STMicroelectronics. ROM or FASTROM code must be sent in .S19 format. .Hex extension cannot be processed. STMicroelectronics references ROM Type/Memory Size/Package (check only 1 option): SDIP42: | [ ] ST72124J2B | | | [ ] ST72314J2B | [ ] ST72314J4B | | [ ] ST72334J2B | [ ] ST72334J4B | TQFP44: | [ ] ST72124J2T | | | [ ] ST72314J2T | [ ] ST72314J4T | | [ ] ST72334J2T | [ ] ST72334J4T | SDIP56: | [ ] ST72314N2B | [ ] ST72314N4B | | [ ] ST72334N2B | [ ] ST72334N4B | TQFP64: | [ ] ST72314N2T | [ ] ST72314N4T | | [ ] ST72334N2T | [ ] ST72334N4T | SDIP42: | [ ] ST72P124J2B | | | [ ] ST72P314J2B | [ ] ST72P314J4B | | [ ] ST72P334J2B | [ ] ST72P334J4B | TQFP44: | [ ] ST72P124J2T | | | [ ] ST72P314J2T | [ ] ST72P314J4T | | [ ] ST72P334J2T | [ ] ST72P334J4T | SDIP56: | [ ] ST72P314N2B | [ ] ST72P314N4B | | [ ] ST72P334N2B | [ ] ST72P334N4B | TQFP64: | [ ] ST72P314N2T | [ ] ST72P314N4T | | [ ] ST72P334N2T | [ ] ST72P334N4T | Conditioning (specify for TQFP only): [ ] Tape & Reel [ ] Tray Marking: [ ] Standard marking [ ] Special marking (ROM only): Authorized characters are letters, digits, '.', '-', '/' and spaces only. Please consult your local STMicroelectronics sales office for other marking details if required. Temperature Range: [ ] 0°C to +70°C [ ] -40°C to +85°C [ ] -40°C to +105°C [ ] -40°C to +125°C Clock Source Selection: Resonator: [ ] LP: Low power resonator (1 to 2 MHz) [ ] MP: Medium power resonator (2 to 4 MHz) [ ] MS: Medium speed resonator (4 to 8 MHz) [ ] HS: High speed resonator (8 to 16 MHz) RC Network: [ ] Internal [ ] External External Clock: [ ] Clock Security System: [ ] Disabled [ ] Enabled LVD Reset: [ ] Disabled [ ] Enabled: [ ] Highest threshold [ ] Medium threshold [ ] Lowest threshold Watchdog Selection: [ ] Software Activation [ ] Hardware Activation Watchdog Reset on Halt: [ ] Reset [ ] No reset Program Readout Protection: [ ] Disabled [ ] Enabled Data E2PROM Readout Protection*: [ ] Disabled [ ] Enabled *available on ST72334 only Comments: Supply Operating Range in the application: Notes: Date: Signature:

18.3 DEVELOPMENT TOOLS

ers, emulators and gang programmers. port: see Table 26 and Table 27 for more details. Table 26. STMicroelectronics Tool Features Table 27. Dedicated STMicroelectronics Development Tools

1. In-Situ Programming (ISP) interface for FLASH devices.

18.3.1 Suggested List Of Socket Types

Table 28. Suggested List of TQFP64 Socket Types

ST72334J/N, ST72314J/N, ST72124J

18.4 ST7 APPLICATION NOTES

IDENTIFICATION DESCRIPTION EXAMPLE DRIVERS AN 969 SCI COMMUNICATION BETWEEN ST7 AND PC AN 970 SPI COMMUNICATION BETWEEN ST7 AND EEPROM AN 971 I²C COMMUNICATING BETWEEN ST7 AND M24CXX EEPROM AN 972 ST7 SOFTWARE SPI MASTER COMMUNICATION AN 973 SCI SOFTWARE COMMUNICATION WITH A PC USING ST72251 16-BIT TIMER AN 974 REAL TIME CLOCK WITH ST7 TIMER OUTPUT COMPARE AN 976 DRIVING A BUZZER THROUGH ST7 TIMER PWM FUNCTION AN 979 DRIVING AN ANALOG KEYBOARD WITH THE ST7 ADC AN 980 ST7 KEYPAD DECODING TECHNIQUES, IMPLEMENTING WAKE-UP ON KEYSTROKE AN1017 USING THE ST7 UNIVERSAL SERIAL BUS MICROCONTROLLER AN1041 USING ST7 PWM SIGNAL TO GENERATE ANALOG OUTPUT (SINUSOID) AN1042 ST7 ROUTINE FOR I²C SLAVE MODE MANAGEMENT AN1044 MULTIPLE INTERRUPT SOURCES MANAGEMENT FOR ST7 MCUS AN1045 ST7 S/W IMPLEMENTATION OF I²C BUS MASTER AN1046 UART EMULATION SOFTWARE AN1047 MANAGING RECEPTION ERRORS WITH THE ST7 SCI PERIPHERALS AN1048 ST7 SOFTWARE LCD DRIVER AN1078 PWM DUTY CYCLE SWITCH IMPLEMENTING TRUE 0% & 100% DUTY CYCLE AN1082 DESCRIPTION OF THE ST72141 MOTOR CONTROL PERIPHERAL REGISTERS AN1083 ST72141 BLDC MOTOR CONTROL SOFTWARE AND FLOWCHART EXAMPLE AN1105 ST7 PCAN PERIPHERAL DRIVER AN1129 PERMANENT MAGNET DC MOTOR DRIVE. AN1130 AN INTRODUCTION TO SENSORLESS BRUSHLESS DC MOTOR DRIVE APPLICATIONS WITH THE ST72141 AN1148 USING THE ST7263 FOR DESIGNING A USB MOUSE AN1149 HANDLING SUSPEND MODE ON A USB MOUSE AN1180 USING THE ST7263 KIT TO IMPLEMENT A USB GAME PAD AN1276 BLDC MOTOR START ROUTINE FOR THE ST72141 MICROCONTROLLER AN1321 USING THE ST72141 MOTOR CONTROL MCU IN SENSOR MODE AN1325 USING THE ST7 USB LOW-SPEED FIRMWARE V4.X AN1445 USING THE ST7 SPI TO EMULATE A 16-BIT SLAVE AN1475 DEVELOPING AN ST7265X MASS STORAGE APPLICATION AN1504 STARTING A PWM SIGNAL DIRECTLY AT HIGH LEVEL USING THE ST7 16-BIT TIMER PRODUCT EVALUATION AN 910 PERFORMANCE BENCHMARKING AN 990 ST7 BENEFITS VERSUS INDUSTRY STANDARD AN1077 OVERVIEW OF ENHANCED CAN CONTROLLERS FOR ST7 AND ST9 MCUS AN1086 U435 CAN-DO SOLUTIONS FOR CAR MULTIPLEXING AN1150 BENCHMARK ST72 VS PC16 AN1151 PERFORMANCE COMPARISON BETWEEN ST72254 & PC16F876 AN1278 LIN (LOCAL INTERCONNECT NETWORK) SOLUTIONS PRODUCT MIGRATION AN1131 MIGRATING APPLICATIONS FROM ST72511/311/214/124 TO ST72521/321/324 AN1322 MIGRATING AN APPLICATION FROM ST7263 REV.B TO ST7263B AN1365 GUIDELINES FOR MIGRATING ST72C254 APPLICATION TO ST72F264 PRODUCT OPTIMIZATION

ST72334J/N, ST72314J/N, ST72124J AN 982 USING ST7 WITH CERAMIC RESONATOR AN1014 HOW TO MINIMIZE THE ST7 POWER CONSUMPTION AN1015 SOFTWARE TECHNIQUES FOR IMPROVING MICROCONTROLLER EMC PERFORMANCE AN1040 MONITORING THE VBUS SIGNAL FOR USB SELF-POWERED DEVICES AN1070 ST7 CHECKSUM SELF-CHECKING CAPABILITY AN1324 CALIBRATING THE RC OSCILLATOR OF THE ST7FLITE0 MCU USING THE MAINS AN1477 EMULATED DATA EEPROM WITH XFLASH MEMORY AN1502 EMULATED DATA EEPROM WITH ST7 HDFLASH MEMORY AN1529 EXTENDING THE CURRENT & VOLTAGE CAPABILITY ON THE ST7265 VDDF SUPPLY AN1530 ACCURATE TIMEBASE FOR LOW-COST ST7 APPLICATIONS WITH INTERNAL RC OSCIL- LATOR PROGRAMMING AND TOOLS AN 978 KEY FEATURES OF THE STVD7 ST7 VISUAL DEBUG PACKAGE AN 983 KEY FEATURES OF THE COSMIC ST7 C-COMPILER PACKAGE AN 985 EXECUTING CODE IN ST7 RAM AN 986 USING THE INDIRECT ADDRESSING MODE WITH ST7 AN 987 ST7 SERIAL TEST CONTROLLER PROGRAMMING AN 988 STARTING WITH ST7 ASSEMBLY TOOL CHAIN AN 989 GETTING STARTED WITH THE ST7 HIWARE C TOOLCHAIN AN1039 ST7 MATH UTILITY ROUTINES AN1064 WRITING OPTIMIZED HIWARE C LANGUAGE FOR ST7 AN1071 HALF DUPLEX USB-TO-SERIAL BRIDGE USING THE ST72611 USB MICROCONTROLLER AN1106 TRANSLATING ASSEMBLY CODE FROM HC05 TO ST7 AN1179 PROGRAMMING ST7 FLASH MICROCONTROLLERS IN REMOTE ISP MODE (IN-SITU PRO- GRAMMING) AN1446 USING THE ST72521 EMULATOR TO DEBUG A ST72324 TARGET APPLICATION AN1478 PORTING AN ST7 PANTA PROJECT TO CODEWARRIOR IDE AN1527 DEVELOPING A USB SMARTCARD READER WITH ST7SCR AN1575 ON-BOARD PROGRAMMING METHODS FOR XFLASH AND HDFLASH ST7 MCUS IDENTIFICATION DESCRIPTION

ST72334J/N, ST72314J/N, ST72124J

19 IMPORTANT NOTES

19.1 SCI Baud rate registers

Caution: The SCI baud rate register (SCIBRR) MUST NOT be written to (changed or refreshed) while the transmitter or the receiver is enabled.

ST72334J/N, ST72314J/N, ST72124J

20 SUMMARY OF CHANGES

Description of the changes between the current release of the specification and the previous one. Revision Main changes Date 2.5 Replaced Note by Caution in “Conventional Baud Rate Generation” on page 91 Changed Watchdog and Halt mode Option to read “Watchdog reset on Halt” in Section 18 Please read carefully the Section “IMPORTANT NOTES” on page 151 April-03

ST72334J/N, ST72314J/N, ST72124J Notes: Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics  2003 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com