CSSTV32852GKFREP

SN74SSTV32852-EP TI1 | Alldatasheet

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SSTL_2 INPUTS AND OUTPUTS SCES700 OCTOBER 2007 www.ti.com Controlled Baseline Supports SSTL_2 Data Inputs One Assembly/Test Site, One Fabrication Outputs Meet SSTL_2 Class II Specifications Site Differential Clock (CLK and CLK Inputs Extended Temperature Performance of C Supports LVCMOS Switching Levels on the to C RESET Input Enhanced Diminishing Manufacturing Sources RESET Input Disables Differential Input (DMS) Support Receivers, Resets All Registers, and Forces Enhanced Product-Change Notification All Outputs Low Qualification Pedigree (1) Pinout Optimizes DIMM PCB Layout Member of the Texas Instruments Widebus One Device Per DIMM Required Family Latch-Up Performance Exceeds 100 mA Per 1-to-2 Outputs Support Stacked DDR DIMMs JESD 78, Class II (1) Component qualification in accordance with JEDEC and ESD Protection Exceeds JESD industry standards to ensure reliable operation over an 2000-V Human-Body Model (A114-A) extended temperature range. This includes, but is not limited to, Highly Accelerated Stress Test (HAST) or biased 85/85, 1000-V Charged-Device Model (C101) temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life. Such qualification testing should not be viewed as justifying use of this component beyond specified performance and environmental limits. This 24-bit to 48-bit registered buffer is designed for 2.3-V to 2.7-V V CC operation. All inputs are SSTL_2, except the LVCMOS reset RESET input. All outputs are SSTL_2, Class II compatible. The SN74SSTV32852 operates from a differential clock (CLK and CLK Data are registered at the crossing of CLK going high and CLK going low. The device supports low-power standby operation. When RESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage REF inputs are allowed. In addition, when RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET input always must be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the low state during power up. ORDERING INFORMATION (1) T A PACKAGE (2) ORDERABLE PART NUMBER TOP-SIDE MARKING C to C LFBGA GKF Tape and reel CSSTV32852GKFREP SV852IEP (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI website at www.ti.com (2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging Please be aware that an important notice concerning availability, standard warranty, and use in critical

applications

sheet. Widebus is a trademark of Texas Instruments. PRODUCTION DATA information is current as of publication date. Copyright 2007, Texas Instruments Incorporated Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

www.ti.com Terminal Assignments GKF□PACKAGE (TOP VIEW) J H G F E D C B A 21 3 4 65 P N M L K T R U W V SN74SSTV32852-EP 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS SCES700 OCTOBER 2007 A Q2A Q1A CLK CLK Q1B Q2B B Q3A V DDQ GND GND V DDQ Q3B C Q5A Q4A V DDQ V DDQ Q4B Q5B D Q7A Q6A GND GND Q6B Q7B E Q8A GND V DDQ V DDQ GND Q8B F Q10A Q9A V DDQ V DDQ Q9B Q10B G Q12A Q11A GND GND Q11B Q12B H Q13A V CC V DDQ V DDQ V CC Q13B J Q14A Q15A GND GND Q15B Q14B K Q17A Q16A V DDQ V DDQ Q16B Q17B L Q18A Q19A GND GND Q19B Q18B M Q20A V DDQ GND GND V DDQ Q20B N Q22A Q21A V DDQ V DDQ Q21B Q22B P Q23A V DDQ GND GND V DDQ Q23B R Q24A V CC RESET V REF V CC Q24B T D18 D13 D14 U D10 D22 D15 D16 V D11 D23 D19 D17 W D12 D24 D21 D20 FUNCTION TABLE INPUTS OUTPUT Q RESET CLK CLK D H H H H L L H L or H L or H X Q L X or floating X or floating X or floating L Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTV32852-EP

www.ti.com R To□23□Other□Channels RESET Q1A A4CLK A3CLK R4VREF T2D1 A5 Q1B One□of□24□Channels ABSOLUTE MAXIMUM RATINGS (1) SN74SSTV32852-EP 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS SCES700 OCTOBER 2007 LOGIC DIAGRAM (POSITIVE LOGIC) over operating free-air temperature range (unless otherwise noted) VALUE UNIT V CC or Supply voltage range 0.5 to 3.6 V V DDQ V I Input voltage range (2) (3) 0.5 to V CC 0.5 V V O Output voltage range (2) (3) 0.5 to V DDQ 0.5 V I IK Input clamp current V I mA I OK Output clamp current V O or V O V DDQ mA I O Continuous output current V O to V DDQ mA Continuous current through each V CC V DDQ or GND 100 mA θ JA Package thermal impedance (4) C/W T stg Storage temperature range to 150 C (1) Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. (3) This value is limited to 3.6 V maximum. (4) The package thermal impedance is calculated in accordance with JESD 51-7. Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN74SSTV32852-EP

www.ti.com RECOMMENDED OPERATING CONDITIONS (1) ELECTRICAL CHARACTERISTICS SN74SSTV32852-EP 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS SCES700 OCTOBER 2007 MIN NOM MAX UNIT V CC Supply voltage V DDQ 2.7 V V DDQ Output supply voltage 2.3 2.7 V V REF Reference voltage REF V DDQ /2) 1.15 1.25 1.35 V V TT Termination voltage V REF mV V REF V REF mV V V I Input voltage VCC V V IH AC high-level input voltage Data inputs V REF 310 mV V V IL AC low-level input voltage Data inputs V REF 310 mV V V IH DC high-level input voltage Data inputs V REF 150 mV V V IL DC low-level input voltage Data inputs V REF 150 mV V V IH High-level input voltage RESET 1.7 V V IL Low-level input voltage RESET 0.7 V V ICR Common-mode input voltage range CLK, CLK 0.97 1.53 V V I(PP) Peak-to-peak input voltage CLK, CLK 360 mV I OH High-level output current mA I OL Low-level output current T A Operating free-air temperature -40 C (1) The RESET input of the device must be held at valid logic voltage levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless RESET is low. Refer to the TI application report, Implications of Slow or Floating CMOS Inputs literature number SCBA004. over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS V CC MIN TYP (1) MAX UNIT V IK I I mA 2.3 V 1.2 V I OH 100 μ A 2.3 V to 2.7 V V DDQ 0.2 V V OH I OH mA 2.3 V 1.95 I OL 100 μ A 2.3 V to 2.7 V 0.2 V V OL I OL mA 2.3 V 0.35 I I All inputs V I V CC or GND 2.7 V μ A Static standby RESET GND I O μ A I CC 2.7 V Static operating RESET V CC V I V IH(AC) or V IL(AC) mA RESET V CC V I V IH(AC) or V IL(AC) I O Dynamic operating μ CLK and CLK switching 50% duty clock only MHz cycle RESET V CC V I V IH(AC) or V IL(AC) I CCD 2.7 V μ CLK and CLK switching 50% duty Dynamic operating clock cycle, one data input switching at per each data input MHz/ one-half clock frequency, 50% duty D input cycle r OH Output high I OH mA 2.3 V to 2.7 V Ω r OL Output low I OL mA 2.3 V to 2.7 V Ω Data inputs V I V REF 310 mV 3.75 4.25 C I CLK, CLK V ICR 1.25 V I(PP) 360 mV 2.5 V 3.5 pF RESET V I V CC or GND 3.5 4.35 (1) All typical values are at V CC 2.5 T A Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTV32852-EP

www.ti.com TIMING REQUIREMENTS SWITCHING CHARACTERISTICS SN74SSTV32852-EP 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS SCES700 OCTOBER 2007 over operating free-air temperature range (unless otherwise noted) (see Figure V CC 2.5 V 0.2 V UNIT MIN MAX f clock Clock frequency 200 MHz t w Pulse duration, CLK, CLK high or low 2.5 ns t act Differential inputs active time (1) ns t inact Differential inputs inactive time (2) ns Fast slew rate (3) (4) 0.75 t su Setup time Data before CLK CLK ns Slow slew rate (5) (4) 0.9 Fast slew rate (3) (4) 0.75 t h Hold time Data after CLK CLK ns Slow slew rate (5) (4) 0.9 (1) V REF must be held at a valid input level, and data inputs must be held low for a minimum time of t act max, after RESET is taken high. (2) V REF data, and clock inputs must be held at valid voltage levels (not floating) for a minimum time of t inact max, after RESET is taken low. (3) Data signal input slew rate V/ns (4) CLK, CLK input slew rates are V/ns. (5) Data signal input slew rate 0.5 V/ns and V/ns over operating free-air temperature range (unless otherwise noted) (see Figure V CC 2.5 V FROM TO 0.2 V PARAMETER UNIT (INPUT) (OUTPUT) MIN MAX f max 200 MHz t pd CLK and CLK Q 1.1 3.1 ns t PHL RESET Q ns Copyright 2007, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): SN74SSTV32852-EP

www.ti.com PARAMETER MEASUREMENT INFORMATION V /2CC VOLTAGE AND□CURRENT□WAVEFORMS INPUTS ACTIVE AND□INACTIVE□TIMES NOTES: A.□□□C includes□probe□and□jig□capacitance.L C. All□input□pulses□are□supplied□by□generators□having□the□following□characteristics:□PRR 10□Mhz,□ZO□=□50 ,≤ Ω Input□slew□rate□=□1□V/ns 20%□(unless□otherwise□noted).± D. The□outputs□are□measured□one□at□a□time□with□one□transition□per□measurement. E.□□□V =□V =□V /2TT REF DDQ F.□□□V =□V +□310□mV□(ac□voltage□levels)□for□differential□inputs.□V =□V for□LVCMOS□input.IH REF IH CC G.□□□V =□V 310□mV□(ac□voltage□levels)□for□differential□inputs.□V =□GND□for□LVCMOS□input.IL REF IL− H.□□□t and□t are□the□same□as□t .PLH PHL pd 0□V VCC LOAD□CIRCUIT 50 Ω C =□30□pFL (see□Note A) Test□Point VTT From□Output Under□Test thtsu VOLTAGE□WAVEFORMS SETUP AND□HOLD□TIMES Timing Input VICR VREFInput VIL VIH VREF VI(PP) tPHL VOH VOL Output VTT VTT tPLH tPHL VIH VIL VOL VOH LVCMOS RESET Input Output VOLTAGE□WAVEFORMS PROPAGATION□DELAY TIMES VTT V /2CC VI(PP) VICR Timing Input VICR VOLTAGE□WAVEFORMS PROPAGATION□DELAY TIMES V /2CC VREFInput VREF tw VOLTAGE□WAVEFORMS PULSE□DURATION VIH VILLVCMOS RESET Input tacttinact 10% 90% I (operating)CC I (standby)CC ICC (see Note□B) SN74SSTV32852-EP 24-BIT TO 48-BIT REGISTERED BUFFER WITH SSTL_2 INPUTS AND OUTPUTS SCES700 OCTOBER 2007 Figure Load Circuit and Voltage Waveforms Submit Documentation Feedback Copyright 2007, Texas Instruments Incorporated Product Folder Link(s): SN74SSTV32852-EP

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W (mm) Pin1 Quadrant CSSTV32852GKFREP BGA MI CROSTA R PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2009 Pack Materials-Page 1

*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSSTV32852GKFREP BGA MICROSTAR GKF 114 1000 346.0 346.0 41.0 PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2009 Pack Materials-Page 2

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