CSPU877

CSPU877 RENESAS | Alldatasheet

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1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE 2006 Integrated Device Technology, Inc. DSC-5962/38c IDTCSPU877 COMMERCIAL TEMPERATURE RANGE 1.8V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER OCTOBER 2006 The IDT logo is a registered trademark of Integrated Device Technology, Inc. FUNCTIONAL BLOCK DIAGRAM NOTE: The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK and CLK. DESCRIPTION: The CSPU877 is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK, CLK ) to 10 differential output pairs (Y [0:9], Y [0:9]) and one differential pair of feedback clock output (FBOUT, FBOUT). External feedback pins (FBIN, FBIN) for synchronization of the outputs to the input reference is provided. OE, OS, and AVDD control the power-down and test mode logic. When AVDD is grounded, the PLL is turned off and bypassed for test mode purposes. When the differential clock inputs (CLK, CLK) are both at logic low, this device will enter a low power-down mode. In this mode, the receivers are disabled, the PLL is turned off, and the output clock drivers are disabled, resulting in a current consumption device of less than 500μA. The CSPU877 requires no external components and has been optimised for very low phase error, skew, and jitter, while maintaining frequency and duty cycle over the operating voltage and temperature range. The CSPU877, designed for use in both module assemblies and system motherboard based solutions, provides an optimum high-performance clock source. The CSPU877 is available in Commercial Temperature Range (0°C to +70°C). See Ordering Information for details. FEATURES:

• 1 to 10 differential clock distribution
• Optimized for clock distribution in DDR2 (Double Data Rate) SDRAM applications
• Operating frequency: 125MHz to 340MHz
• 1.8V AV DD and 1.8V VDDQ
• CMOS control signal input
• Test mode enables buffers while disabling PLL
• Low current power-down mode
• Tolerant of Spread Spectrum input clock
• Available in 52-Ball VFBGA and 40-pin VFQFPN packages APPLICATIONS:
• Meets or exceeds JEDEC standard 82-8 for registered DDR2 clock driver
• Along with SSTU32864/A, DDR2 register, provides complete solution for DDR2 DIMMs FBOUT FBOUT FBIN FBIN PLL CLK CLK POWER DOWN AND TEST MODE LOGIC LD AVDD OE OS LD or OE LD, OS, or OE PLL BYPASS 10KΩ -1 0 0 KΩ

COMMERCIAL TEMPERATURE RANGE IDTCSPU877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER PIN CONFIGURATION

52 BALL VFBGA PACKAGE LAYOUT

6 Y7 FBIN FBOUTY6 FBOUTY6 Y8 Y8Y7 FBIN

5 VDDQOEGNDY5 Y9GND

4 Y9Y5 VDDQ

3 Y4Y0 VDDQ

2 Y0 Y4GND VDDQ GND

1 Y1 Y1 AGND AVDDCLK CLK Y3Y3Y2Y2

0.65mm TOP VIEW A B C D E F G H J K A B C D E F G H J K

1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE ABSOLUTE MAXIMUM RATINGS(1,2) Symbol Rating Max Unit VDDQ, AV DD Supply Voltage Range –0.5 to +2.5 V VI(3) Input Voltage Range –0.5 to VDDQ + 0.5 V VO(3) Voltage range applied to any –0.5 to V DDQ + 0.5 V output in the high or low state IIK Input clamp current ±50 mA (VI <0) IOK Output Clamp Current ±50 mA (VO <0 or VO > VDDQ) IO Continuous Output Current ±50 mA (VO =0 to VDDQ) VDDQ or GND Continuous Current ±100 mA TSTG Storage Temperature Range – 65 to +150 °C NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The maximum package power dissipation is calculated using a junction temperature of 150 °C and a board trace length of 750 mils. 3. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 2.5V max. RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min. Typ. Max. Unit AVDD(1) Supply Voltage V DDQ V VDDQ I/O Supply Voltage 1.7 1.8 1.9 V TA Operating Free-Air Temperature 0 ⎯ +70 °C CAPACITANCE(1) Parameter Description Min. Typ. Max. Unit CIN Input Capacitance 2 — 3 pF VI = VDDQ or GND CIΔ Delta Input Capacitance 0.25 pF CLK, CLK, FBIN, FBIN CL Load Capacitance — 10 — pF NOTE: 1. Unused inputs must be held high or low to prevent them from floating. V DDQ Y Y Y Y Y Y Y Y 40 39 38 37 36 35 34 33 32 31 V DDQ 11 12 13 14 15 16 17 18 19 20 Y Y V DDQY Y Y Y Y Y V DDQ VDDQ FBIN FBIN FBOUT FBOUT OE OS VDDQ GND VDDQ AGND AVDD CLK CLK VDDQ VDDQ GND VFQFPN TOP VIEW NOTE: 1. The PLL is turned off and bypassed for test purposes when AV DD is grounded. During this test mode, V DDQ remains within the recommended operating conditions and no timing parameters are guaranteed. PIN CONFIGURATION

COMMERCIAL TEMPERATURE RANGE IDTCSPU877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER PIN DESCRIPTION (VFBGA) Pin Name Pin Number Description AGND G1 Ground for 1.8V analog supply AVDD H1 1.8V analog supply CLK, CLK E1, F1 Differential clock input with a 10K Ω to 100KΩ pulldown resistor FBIN, FBIN E6, F6 Feedback differential clock input FBOUT, FBOUT G6, H6 Feedback differential clock output GND B2 - B5, C2, C5, H2, H5, J2 - J5 Ground VDDQ D2 - D4, E2, E5, F2, G2 - G5 1.8V supply OE F5 Output Enable OS D5 Output Select (tied to GND or V DDQ) Y[0:9] A3, A4, B1, B6, C1, C6, K1, K2, K5, K6 Buffered output of input clock, CLK Y[0:9] A1, A2, A5, A6, D1, D6, J1, J6, K3, K4 Buffered output of input clock, CLK NB No Ball PIN DESCRIPTION (VFQFPN) Pin Name Pin Number Description AGND 7 Ground for 1.8V analog supply AVDD 8 1.8V analog supply CLK, CLK 4, 5 Differential clock input with a 10K Ω to 100KΩ pulldown resistor FBIN, FBIN 26, 27 Feedback differential clock input FBOUT, FBOUT 24, 25 Feedback differential clock output GND 10 Ground VDDQ 1, 6, 9, 15, 20, 23, 28, 31, 36 1.8V supply OE 22 Output Enable OS 21 Output Select (tied to GND or V DDQ) Y[0:9] 3, 11, 14, 16, 19, 29, 33, 34, 38, 39 Buffered output of input clock, CLK Y[0:9] 2, 12, 13, 17, 18, 30, 32, 35, 37, 40 Buffered output of input clock, CLK

1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care 2. L(z) means the outputs are disabled to a LOW state, meeting the I ODL limit in DC Electrical Characteristics table. 3. The device will enter a low power-down mode when CLK and CLK are both at logic LOW. FUNCTION TABLE(1,2) INPUTS OUTPUTS AVDD OE OS CLK CLK Y Y FBOUT FBOUT PLL G N D H X LH L H LH O F F G N D H X HL H L HL O F F GND L H L H L(z) L(z) L H OFF L(z) L(z) GND L L H L Y 7 Y7 H L OFF Active Active 1.8V (nom) L H L H L(z) L(z) L H O N L(z) L(z) 1.8V (nom) L L H L Y 7 Y7 HL O N Active Active 1.8V (nom) H X L H L H L H ON 1.8V (nom) H X H L H L H L ON 1.8V (nom) X X L (3) L (3) L(z) L(z) L(z) L(z) OFF X X X H H Reserved DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0°C to +70°C Symbol Parameter Conditions Min. Typ. Max. Unit VIK Input Clamp Voltage (All Inputs) V DDQ = 1.7V, II = -18mA ⎯⎯ – 1.2 V VIL(2) Input LOW Voltage (OE, OS, CLK, CLK) ⎯⎯ 0.35VDDQ V VIH(2) Input HIGH Voltage (OE, OS, CLK, CLK) 0.65V DDQ ⎯⎯ VIN(1) Input Signal Voltage -0.3 ⎯ VDDQ + 0.3 V VID(DC)(2) DC Input Differential Voltage 0.3 V DDQ + 0.4 V VOD(3) Output Differential Voltage A VDD/VDDQ = 1.7V 0.5 ⎯⎯ V VOH Output HIGH Voltage I OH = -100μA, VDDQ = 1.7V to 1.9V V DDQ - 0.2 ⎯ V IOH = -9mA, VDDQ = 1.7V 1.1 ⎯ VOL Output LOW Voltage I OL = 100μA, VDDQ = 1.7V to 1.9V 0.1 V IOL = 9mA, VDDQ = 1.7V 0.6 IODL Output Disabled LOW Current OE = L, V ODL = 100mV, AVDD/VDDQ = 1.7V 100 ⎯⎯μ A IIN Input Current CLK, CLK AVDD/VDDQ = Max., VI = 0V to VDDQ ±250 μA OE, OS, FBIN, FBIN ±10 IDDLD Static Supply Current (IDDQ and IADD)A VDD/VDDQ = Max., CLK and CLK = GND 500 μA IDD Dynamic Power Supply Current A VDD/VDDQ = Max., CLK = 270MHz 300 mA (IDDQ and IADD)(4,5) NOTES: 1. V IN specifies the allowable DC excursion of each different output. 2. V ID is the magnitude of the difference between the input level on CLK and the input level on CLK. The CLK and CLK VIH and V IL limits are used to define the DC LOW and HIGH levels for the power down mode. 3. V OD is the magnitude of the difference between the true output level and the complementary level. 4. All Outputs are left open (unconnected to PCB). 5. Total I DD = IDDQ + IADD = FCK * CPD * VDDQ, for Cpd = (IDDQ + IADD) / (FCK * VDDQ) where FCK is the input frequency, VDDQ is the power supply, and CPD is the Power Dissipation Capacitance.

COMMERCIAL TEMPERATURE RANGE IDTCSPU877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TIMING REQUIREMENTS Symbol Parameter Min. Max. Unit fCLK Operating Clock Frequency(1,2,3) 125 340 M H z Application Clock Frequency(2,4) 160 340 M H z tDC Input Clock Duty Cycle 40 60 % tL Stabilization Time(5) ⎯ 15 μs NOTES: 1. 270MHz max clock frequency for parts assembled and tested prior to WW37. 2. The PLL will track a spread spectrum clock input. 3. Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications. To be used only for low speed system debug. 4. Application clock frequency is the range over which timing specifications apply. 5. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its ref erence signal after power up. During normal operation, the stabilization time is also the time required for the PLL circuit to obtain phase lock of its feedback signal to its reference s ignal when CLK and CLK go to a logic LOW state, enters the power-down mode, and later return to active operation. CLK and CLK may be left floating after they have been driven LOW for one complete clock cycle. AC ELECTRICAL CHARACTERISTICS(1) Symbol Description Test Conditions Min. Typ.(2) Max. Unit tPLH(2) LOW to HIGH Level Propagation Delay Time A VDD = GND, OE = H, OS = L, TBD ns CLK to any output tPHL(2) HIGH to LOW Level Propagation Delay Time A VDD = GND, OE = H, OS = L, TBD ns CLK to any output tJIT(CC+) Jitter (cycle-to-cycle) 166/200/266MHz 0 40 ps tJIT(CC-) 0 -40 tJIT(PER)(3) Jitter (period) 166/200/266MHz -40 40 ps tJIT(HPER)(3) Half-Period Jitter 166/200/266MHz -60 60 ps tSLR(O)(1,4) Output Clock Slew Rate (single-ended) 166/200/266MHz (20% to 80%) 1.5 2.5 3 V/ns tSLR(I)(1,4) Output Enable (OE) 0.5 ⎯⎯ V/ns Input Clock Slew Rate 1 2.5 4 t(∅)(5) Static Phase Offset 166/200/266MHz -50 50 ps t(∅)DYN Dynamic Phase Offset TBD TBD tSK(O) Output Skew 40 ps tEN Output Enable to any Y or Y 8n s tDIS Output Disable to any Y or Y 8n s VOX(6) AC Differential Output Crosspoint Voltage Differential outputs terminated with 120Ω (VDDQ/2) -0.1 (V DDQ/2) +0.1 V VID(AC) AC Differential Input Voltage 0.6 V DDQ +0.4 V VIX AC Differential Input Crosspoint Voltage (V DDQ/2) -0.15 (V DDQ/2) +0.15 V The PLL on the CSPU877 will meet all the above test parameters while supporting SSC synthesizers with the following parameters: SSC Modulation Frequency 30 ⎯ 3 3 KHz SSC Clock Input Frequency Deviation 0 ⎯ -0.5 % f3dB PLL Loop Bandwidth 2 MHz NOTES: 1. There are two different terminations that are used with the above AC tests. The output load shown in figure 1 is used to mea sure the input and output differential pair cross-voltage only. The output load shown in figure 2 is used to measure all other tests, including input and output slew rates. For consis tency, use 50Ω equal length cables with SMA connectors on the test board. 2. Refers to transition of non-inverting output. 3. Period jitter and half-period jitter specifications are seperate specifications that must be met independently of each other. 4. To eliminate the impact of input slew rates on static phase offset, the input slew rates of reference clock input (CLK, CLK) and feedback clock input (FBIN, FBIN) are recommended to be nearly equal. The 2.5V/ns slew rates are shown as a recommended target. Compliance with these nominal values is not man datory if it can be adequately demonstrated that alternative characteristics meet the requirements of the registered DDR2 DIMM application. 5. Static phase offset does not include jitter. 6. V OX is specified at the DDR DRAM clock input or test load.

COMMERCIAL TEMPERATURE RANGE IDTCSPU877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER Yx, FBOUT tjit(cc) tcycle n tcycle n+1= Yx, FBOUT tcycle n tcycle n+1 FBIN CLK t(Ø)n t(Ø)n + 1 t(Ø) = N n = N 1 t(Ø)n∑ CLK FBIN (N is a large number of samples) Cycle-to-Cycle jitter Static Phase Offset Yx, FBOUT Yx tsk(o) Yx, FBOUT Yx Output Skew TEST CIRCUIT AND SWITCHING WAVEFORMS

1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE Yx, FBOUT Yx, FBOUT tjit(per) = tcycle n fo Yx, FBOUT Yx, FBOUT tcycle n fo Yx, FBOUT Yx, FBOUT fo tjit(hper) = thalf period n 2*fo Yx, FBOUT Yx, FBOUT thalf period n thalf period n+1 Period jitter Half-Period jitter TEST CIRCUIT AND SWITCHING WAVEFORMS NOTE: fo = Average input frequency measured at CLK / CLK NOTE: fo = Average input frequency measured at CLK / CLK

COMMERCIAL TEMPERATURE RANGE IDTCSPU877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER TEST CIRCUIT AND SWITCHING WAVEFORMS Dynamic Phase Offset FBIN CLK t(Ø)DYN t(Ø) t(Ø)DYN SSC ON SSC OFF CLK FBIN t(Ø)DYN t(Ø) t(Ø)DYN SSC ON SSC OFF OE Y/Y OE 50% VDDQ tEN 50% VDDQ 50% VDDQ tDIS 50% VDDQ Y Y Y Y Time Delay Between Output Enable (OE) and Clock Output (Y, Y)

1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE Input and Output Slew Rates Clock Inputs and Outputs, OE 80% 20% VID, VOD tR(I), tR(O) 80% 20% V20%V80% tSLF(I/O) = tF(I/O) tF(I), tF(O) V20%V80% tSLR(I/O) = tR(I/O)

APPLICATION INFORMATION

Clock Loading on the PLL outputs (pF) Clock Structure # of SDRAM Loads per Clock Min. Max. #1 2 3 5 #2 4 6 10 TEST CIRCUIT AND SWITCHING WAVEFORMS VDDQ GND VIA CARD VIA CARD BEAD 0603 4.7uF 1206 0.1uF 0603 2200pF 0603 AVDD AGND VDDQ GND CSPU877 1 0.1uF 0603 Recommended Filtering for the Analog and Digital Power Supplies (AVDD and VDDQ) NOTES: Place all decoupling capacitors as close to the CSPU877 pins as possible. Use wide traces for A VDD and AGND. Recommended bead: Fair-rite P/N 2506036017Y0 or equivalent (0.8 Ω DC max., 600 Ω at 100MHz).

COMMERCIAL TEMPERATURE RANGE IDTCSPU877 1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER R = 120Ω FBIN FBIN R = 120Ω CLK CLK Feedback path R=1 2 0Ω Z=6 0 Ω Z=6 0 Ω 8m o r e SDRAM SDRAM ~2.5" ~0.3" ~0.6" (split to terminator) C = 10pF CSPU877 R=1 2 0Ω FBIN FBIN R = 120Ω CLK CLK Feedback path R = 120Ω Z=6 0 Ω Z=6 0 Ω 8m o r e SDRAM SDRAM ~2.5" ~0.3" ~0.6" (split to terminator) SDRAM SDRAM Stacked Stacked C = 10pF

1.8V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE

ORDERING INFORMATION

Very Fine Pitch Ball Grid Array Very Fine Pitch Ball Grid Array. Green Thermally Enhanced Plastic Very Fine Pitch Quad Flat Pack No Lead Package 1.8V PLL Differential 1:10 SDRAM Clock Driver Process Blank 0°C to +70°C (Commercial) X

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