CSPT855

CSPT855 RENESAS | Alldatasheet

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2.5V PLL CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 2008 Integrated Device Technology, Inc. DSC-6203/12c IDTCSPT855 COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES 2.5V PHASE LOCKED LOOP CLOCK DRIVER PLL CLK CLK FBIN FBIN PWRDWN 9AVDD POWERDOWN AND TEST LOGIC FBOUT FBOUT NOVEMBER 2008 The IDT logo is a registered trademark of Integrated Device Technology, Inc. FEATURES:

• PLL clock driver for DDR (Double Data Rate) synchronous DRAM applications  Spread spectrum clock compatible  Operating frequency: 60MHz to 220MHz  Low jitter (cycle-to-cycle): ±50ps  Distributes one differential clock input to four differential clock outputs  Enters low power mode and 3-state outputs when input CLK signal is less than 20MHz or PWRDWN is low  Operates from a 2.5V supply  Consumes <200 μμμμμA quiescent current  External feedback pins (FBIN, FBIN) are used to synchronize outputs to input clocks  Available in TSSOP package DESCRIPTION: The CSPT855 is a high-performance, low-skew, low-jitter zero delay buffer that distributes one differential clock input pair(CLK, CLK ) to four differential output pairs (Y [0:3], Y [0:3]) and one differential pair of feedback clock outputs (FBOUT, FBOUT). When PWRDWN is high, the outputs switch in phase and frequency with CLK. When PWRDWN is low, all outputs are disabled to a high- impedance state (3-state), and the PLL is shut down (low-power mode). The device also enters this low-power mode when the input frequency falls below a suggested detection frequency that is below 20MHz (typical 10MHz). An input frequency detection circuit detects the low-frequency condition, and after applying a >20MHz input signal, this detection circuit reactivates the PLL and enables the outputs. When AV DD is tied to GND, the PLL is turned off and bypassed for test purposes. The CSPT855 is also able to track spread spectrum clocking for reduced EMI. Since the CSPT855 is based on PLL circuitry, it requires a stabilization time to achieve phase-lock of the PLL. This stabilization time is required following power up. FUNCTIONAL BLOCK DIAGRAM APPLICATIONS:  For all DDR1 speeds: PC1600 (DDR200), PC2100 (DDR266), PC2700 (DDR333), PC3200 (DDR400)

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDTCSPT855 2.5V PLL CLOCK DRIVER PIN DESCRIPTION Pin Name Pin Number I/O Description AGND 1 0 Ground for analog supply AVDD 9 Analog supply CLK, CLK 6, 7 I Differential clock input FBIN, FBIN 22, 23 I Feedback differential clock input FBOUT, FBOUT 19, 20 O Feedback differential clock output GND 1, 5, 14, 15, 28 Ground PWRDWN 24 I Control input to turn device in the power-down mode VDDQ 4, 8, 11, 18, 21, 25 I/O supply Y[0:3] 3, 12, 17, 26 O Buffered output copies of input clock, CLK Y[0:3] 2, 13, 16, 27 O Buffered output copies of input clock, CLK VDDQ GND 281 V DDQ VDDQ GND GND GND CLK CLK AVDD VDDQ PWRDWN FBIN FBIN FBOUT FBOUT VDDQ GND VDDQ AGND PIN CONFIGURATION TSSOP TOP VIEW ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating Max Unit VDDQ, AV DD Supply Voltage Range –0.5 to +3.6 V VI(2) Input Voltage Range –0.5 to VDDQ + 0.5 V VO(2) Output Voltage Range –0.5 to VDDQ + 0.5 V IIK (VI < 0 or Input Clamp Current ±50 mA VI < VDDQ) IOK (VO < 0 or Output Clamp Current ±50 mA VO > VDDQ) IO Continuous Output Current ±50 mA (VO = 0 to VDDQ) VDDQ or GND Continuous Current ±100 mA θJA(3) Package Thermal Impedance 105.8 °C/W TSTG Storage Temperature Range – 65 to +150 ° C NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. This value is limited to 3.6V maximum. 3. The package thermal impedance is calculated in accordance with JESD 51.

2.5V PLL CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level Z = High-Impedance OFF-State X = Don't Care 2. Typically 10MHz. FUNCTION TABLE(1) INPUTS OUTPUTS AVDD PWRDWN CLK CLK Y Y FBOUT FBOUT PLL GND H L H L H L H Bypassed/OFF GND H H L H L H L Bypassed/OFF X L L H Z Z Z Z OFF X L H L Z Z Z Z OFF 2.5V (nom) H L H L H L H ON 2.5V (nom) H H L H L H L ON 2.5V (nom) X <20MHz (2) <20MHz(2) Z Z Z Z OFF RECOMMENDED OPERATING CONDITIONS(1) Symbol Parameter Min. Typ. Max. Unit AVDD, VDDQ Supply Voltage 2.3 — 2.7 V VIL Input Voltage LOW CLK, CLK, FBIN, FBIN —— V DDQ/2 - 0.18 V PRWDWN - 0.3 — 0.7 VIH Input Voltage HIGH CLK, CLK, FBIN, FBIN VDDQ/2 + 0.18 — — V PRWDWN 1.7 — V DDQ + 0.3 DC Input Signal Voltage(2) - 0.3 — V DDQ V VID Differential Input Signal Voltage(3) CLK, FBIN 0.36 — V DDQ + 0.6 V VO(X) Output Differential Cross-Voltage(4) VDDQ/2 - 0.2 V DDQ/2 V DDQ/2 + 0.2 V VI(X) Input Differential Pair Cross-Voltage(4) VDDQ/2 - 0.2 — V DDQ/2 + 0.2 V IOH HIGH-Level Output Current — — - 12 mA IOL LOW-Level Output Current — — 12 mA SR Input Slew Rate, see figure 8 1 — 4 V/ns TA Operating Free-Air Temperature Commercial 0 — +70 °C Industrial -40 — +85 NOTES: 1. Unused inputs must be held HIGH or LOW to prevent them from floating. 2. DC input signal voltage specifies the allowable DC execution of differential input. 3. Differential input signal voltage specifies the differential voltage | V TR - V CP | required for switching, where V TR is the true input level and V CP is the complementary input level. 4. Differential cross-point voltage is expected to track variations of V DDQ and is the voltage at which the differential signals must be crossing.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDTCSPT855 2.5V PLL CLOCK DRIVER DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0°C to +70°C; Industrial: TA = –40°C to +85°C Symbol Parameter Conditions Min. Typ. (1) Max. Unit VIK Input Voltage (All Inputs) V DDQ = 2.3V, II = -18mA — — – 1.2 V VOH HIGH-Level Output Voltage V DDQ = Min. to Max., IOH = -1mA V DDQ – 0.1 — — V VDDQ = 2.3V, IOH = -12mA 1.7 — — VOL LOW-Level Output Voltage V DDQ = Min. to Max., I OL = 1mA — — 0.1 V VDDQ = 2.3V, IOL = 12mA — — 0.6 IOH HIGH-Level Output Current V DDQ = 2.3V, VO = 1V – 18 – 32 — mA IOL LOW-Level Output Current V DDQ = 2.3V, VO = 1.2V 26 35 — mA VOD Output Voltage Swing D ifferential outputs are terminated with 120Ω 1.1 — V DDQ – 0.4 V VOX Output Differential Cross Voltage(2) Differential outputs are terminated with 120Ω VDDQ/2 – 0.2 V DDQ/2 V DDQ/2 + 0.2 V II Input Current V DDQ = 2.7V, VI = 0V to 2.7V — — ±10 μA IOZ High-Impedance State Output Current V DDQ = 2.7V, VO = VDDQ or GND — — ±10 μA IDD(PD) Power-Down Current on VDDQ and AVDD CLK and CLK = 0MHz, PWRDWN = LOW, — 100 200 μA Σ of IDD and AIDD IDD Dynamic Current on VDDQ CL = 14pF f O = 167MHz, Differential outputs terminated with 120Ω — 150 180 mA CL = 0pF f O = 167MHz, Differential outputs terminated with 120Ω — 130 160 AIDD Supply Current on AVDD fO = 167MHz — 8 10 mA CI Input Capacitance V DDQ = 2.5V, VI = VDDQ or GND 2 2.5 3 pF CO Output Capacitance V DDQ = 2.5V, VI = VDDQ or GND 2.5 3 3.5 pF NOTES: 1. All typical values are at respective nominal V DDQ. 2. Differential cross-point voltage is expected to track variation of V DDQ and is the voltage at which the differential signals must be crossing. TIMING REQUIREMENTS Symbol Parameter Min. Max. Unit fCLK Operating Clock Frequency 60 220 MHz tDC Input Clock Duty Cycle 40 60 % tL Stabilization Time (PLL Mode)(1) —1 0 μs tL Stabilization Time (Bypass Mode)(2) —3 0 n s NOTES: 1. Recovery time required when the device goes from power-down mode into bypass mode (test mode with AV DD at GND). 2. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jitter parame ters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under SSC application.

2.5V PLL CLOCK DRIVER COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS Symbol Description Test Conditions Min. Typ.(1) Max. Unit tPLH(2) LOW to HIGH Level Propagation Delay Time Test mode, CLK to any output — 4.5 — ns tPHL(2) HIGH to LOW Level Propagation Delay Time Test mode, CLK to any output — 4.5 — ns tJIT(PER)(3) Jitter (period), see figure 6 66MHz – 55 — 55 ps 100/ 133/ 167/ 200 MHz – 35 — 35 tJIT(CC)(3) Jitter (cycle-to-cycle), see figure 2 66MHz – 60 — 60 ps 100/ 133/ 167/ 200 MHz – 50 — 50 tJIT(HPER)(3) Half-Period Jitter, see figure 7 66MHz – 130 — 130 100MHz – 90 — 90 ps 133/ 167/ 200 MHz – 75 — 75 tSLR(O) Output Clock Slew Rate (single-ended), see figure 8 Load: 120 Ω / 14pF 1 — 2 V/ns Load: 120Ω / 4pF 1 — 3 66MHz – 180 — 180 SSC Off 100/ 133 MHz – 130 — 130 tD(∅)(3) Dynamic Phase Offset (includes jitter) 167/ 200 MHz – 90 — 90 ps see figure 4 66MHz – 230 — 230 SSC On 100/ 133 MHz – 170 — 170 167/ 200 MHz – 100 — 100 t (∅) Static Phase Offset, see figure 3 66MHz – 150 — 150 100/ 133/ 167 MHz – 100 — 100 ps 200MHz – 50 — 50 tSK(O)(4) Output Skew, see figure 5 — — 50 ps tR, tF Output Rise and Fall Times (20% to 80%) Load: 120 Ω / 14pF 650 — 900 ps NOTES: 1. All typical values are at respective nominal V DDQ. 2. Refers to transition of non-inverting output. 3. This parameter guaranteed by design but not production tested. 4. All differential output pins are terminated with 120 Ω / 14pF.

Figure 8. Input and Output Slew Rates

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES IDTCSPT855 2.5V PLL CLOCK DRIVER

ORDERING INFORMATION

Thin Shrink Small Outline Package TSSOP - Green 2.5V PLL Clock Driver Process Blank I 0°C to +70°C (Commercial) -40°C to +85°C (Industrial) X

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