CSPDDR100 CALMIRCO | Alldatasheet

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Technical content

Features

  • 16 Integrated High frequency Series/Parallel Terminations  Ultra small footprint Chip Scale Package  Ceramic substrate  0.35mm Eutectic Solder Bumps, 0.65mm Pitch Product Description The CSPDDR100 is a high performance Integrated Passive Device (IPD) which provides Series/Parallel terminations suitable for use in SSTL and DDR termina- tion applications. Sixteen (16) Series/Parallel termination channels are provided for a total of 32 integrated resistors. These resistors provide excellent high fre- quency performance in excess of 3GHz and are manu- factured to an absolute tolerance of ±1%. The Chip

Applications

 DDR Memory bus termination  SSTL Termination C1260700 SCHEMATIC DIAGRAM Scale Package provides an ultra small footprint for this Integrated Passive Device and provides minimal parasitics compared to conventional packaging. Typical bump inductance is less than 25pH. The large solder bumps and ceramic substrate allow for standard attach- ment to laminate printed circuit boards without the use of underfill. The 4X9 Bump pattern is arranged for easy flow through routing on the pcb. D C B A 12 34 5 67 8 9 NOITAMROFNIGNIREDROTRAPDRADNATS egakcaP rebmuNtraPgniredrO elytSs pmuBl eeR&epaTg nikraMtraP elacSpihC6 30 01RDDPSC1 ApmubkramottodknI

©2000 California Micro Devices Corp. All rights reserved. 7/21/2000215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com2 CSPDDR100CALIFORNIA MICRO DEVICES Package Diagram (Bumps Up View) D C B A 1 9 Typical PCB Routing Diagram (Bumps Down View) SNOITADNEMMOCERDRAOBTIUCRICDETNIRP BCPnoeziSdaPm m003.0 epahSdaPd nuoR noitinifeDdaP )DMSN(sdaPdenifeDksaMredloSnoN gninepOksaMredloSm m053.0 ssenkcihTlicnetSredloSm m251.0 gninepOerutrepAlicnetSredloS) .qs(mm063.0 oitaRxulFredloS0 5/05 etsaPredloSn aelCoN hsiniFecarTdnoB) A601sulPuCketnE(PSO A B C D 2345678 9 2.44mm 0.381mm 0.65 mm 0.65 mm 0.875mm 0.245 mm 0.35mm Dia. Bumps 0.297mm 5.79mm

© 2000 California Micro Devices Corp. All rights reserved. 7/21/2000 3 CSPDDR100CALIFORNIA MICRO DEVICES 215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com (seulaVrotsiseR ΩΩΩΩΩ) (1R )Ω)Ω)Ω)Ω)Ω (2R )Ω)Ω)Ω)Ω)Ω edoC 520 50 01 PART NUMBER KEY CSP DDR 100 PACKAGE TYPE APPLICATION Resistor Value Code CSP = Chip Scale Package DDR = Double Data Rate Memory Termination 100 = R1 25Ω; R2 50Ω SEULAVDRADNATS eulaVrotsiseR5 2=1R ,Ω 05=2R ,Ω RecnareloTetulosbA% 1± srotsiseRfoRCTm pp001± rotsiseR/gnitaRrewoPW m001 egnaRerutarepmeTgnitarepOC °58otC°04– Typical Solder Reflow Thermal Profile (No Clean Flux) 250 225 200 175 150 125 100 0 48 97 145 Time (s) Temperature ( o 194 242 290 339 387 435 EXHRFZ5Z4EXH PH Z2 Z3 CD

©2000 California Micro Devices Corp. All rights reserved. 7/21/2000215 Topaz Street, Milpitas, California 95035 Tel: (408) 263-3214 Fax: (408) 263-7846 www.calmicro.com4 CSPDDR100CALIFORNIA MICRO DEVICES The CSPDDR100, Chip Scale DDR Termination Array, provides sixteen (16) channels of series/parallel termi- nation for SSTL termination applications such as DDR memory systems. SSTL is the bus standard for DDR SDRAM systems. Applying terminating resistors to DDR SDRAM’s interconnections is a necessity to avoid signal integrity problems in the memory system ’s operation. Improper or no termination on an interconnection that is a transmission line will cause reflections which in turn will affect the performance of the system due to ringing, delays, exceeding IC voltage specifications, or crosstalk. [1] SSTL has four possible configurations. One of them calls for both a series termination resistor and a parallel termination at one end of the bus, as shown in Figure 1. This is the application that the CSPDDR100 satisfies. When a full level signal is sent down the transmission line and no reflection is desired, the parallel load resistance should equal the characteristic impedance 0) of the transmission line. When a less than full level signal is sent down a transmission line, it is desirable to have an intentional mismatch of the parallel termination load resistor so that the higher level reflection voltage (resulting from having R T > Z0) raises the signal to the full signal level so that load switching occurs in only one propagation delay time. The use of a series termination resistor at the source enables the sending of a reduced level signal on the first incident wave. A reduced level signal is beneficial in reducing rise times and EMI. The values of the resistors for DDR/SSTL terminations are user determined. If values different from the ones in the CSPDDR100 specification are desired, please contact California Micro Devices for quotations on other values. [1] James Sutherland, “Understanding Transmission Lines, and High Speed Terminations”, EDN, October 9, 1999 Figure 1. SSTL_2 Class II,