CSP2510D

CSP2510D IDT | Alldatasheet

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0°C TO 85°C TEMPERATURE RANGE IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER OCTOBER 2001 2001 Integrated Device Technology, Inc. DSC-5874/2c IDTCSP2510D 0ºººººC TO 85 ºººººC TEMPERATURE RANGE 3.3V PHASE-LOCK LOOP CLOCK DRIVER ZERO DELAY BUFFER DESCRIPTION: The CSP2510D is a high performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal. It is specifically designed for use with synchronous DRAMs. The CSP2510D operates at 3.3V. One bank of ten outputs provide low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLK. The outputs can be enabled or disabled via the control G input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input is low, the outputs are disabled to the logic-low state. Unlike many products containing PLLs, the CSP2510D does not require external RC networks. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. Because it is based on PLL circuitry, the CSP2510D requires a stabilization time to achieve phase lock of the feedback signal to the reference signal. This stabilization time is required, following power up and application of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or feedback signals. The PLL can be bypassed for the test purposes by strapping AV DD to ground. The CSP2510D is specified for operation from 0°C to +85°C. This device is also available (on special order) in Industrial temperature range (-40°C to +85°C). See ordering information for details. PLL 23AV DD FBIN CLK G FBOUT FUNCTIONAL BLOCK DIAGRAM The IDT logo is a registered trademark of Integrated Device Technology, Inc. FEATURES:

• Phase-Lock Loop Clock Distribution for Synchronous DRAM

Applications

• Distributes one clock input to one bank of ten outputs
• Output enable bank control
• External feedback (FBIN) pin is used to synchronize the outputs to the clock input signal
• No external RC network required for PLL loop stability
• Operates at 3.3V V DD
• tpd Phase Error at 166MHz: < ±150ps
• Jitter (peak-to-peak) at 166MHz: < ±75ps @ 166MHz
• Spread Spectrum Compatible
• Operating frequency 50MHz to 175MHz
• Available in 24-Pin TSSOP package APPLICATIONS:
• SDRAM Modules
• PC Motherboards
• Workstations

0°C TO 85°C TEMPERATURE RANGE IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER PIN CONFIGURATION TSSOP TOP VIEW CLK AV DD VDD GND GND VDD FBIN AGND VDD GND GND VDD G FBOUT ABSOLUTE MAXIMUM RATINGS(1) Symbol Rating Max Unit VDD Supply Voltage Range –0.5 to +4.6 V VI(1) Input Voltage Range –0.5 to +6.5 V VO(1,2) Voltage range applied to any –0.5 to V DD + 0.5 V output in the high or low state IIK Input clamp current –50 mA (VI <0) IOK Terminal Voltage with Respect ±50 mA (VO <0 or to GND (inputs V IH 2.5, VIL 2.5) VO > V DD) IO Continuous Output Current ±50 mA (VO = 0 to VDD) VDD or GND Continuous Current ±100 mA TSTG Storage Temperature Range – 65 to +150 °C TJ Junction Temperature +150 ° C NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. The maximum package power dissipation is calculated using a junction temperature of 150 °C and a board trace length of 750 mils. CAPACITANCE NOTE: 1. Unused inputs must be held HIGH or LOW to prevent them from floating. Parameter Description Min. Typ. Max. Unit CIN Input Capacitance  5  pF VI = VDD or GND CO Output Capacitance  6  pF VO = VDD or GND CL Load Capacitance  30  pF RECOMMENDED OPERATING CONDITIONS Symbol Description Min. Max. Unit VDD, AVDD Power Supply Voltage 3 3.6 V TA Operating Free-Air Temperature 0 +85 °C

0°C TO 85°C TEMPERATURE RANGE IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER STATIC FUNCTION TABLE (AVDD = 0V) DYNAMIC FUNCTION TABLE (AVDD = 3.3V) PIN DESCRIPTION Terminal Name No. Type Description CLK 24 I Clock input. CLK provides the clock signal to be distributed by the CSP2510D clock driver. CLK is used to provide the r eference signal to the integrated PLL that generates the clock output signals. CLK must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal. FBIN 1 3 I Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally zero phase error between CLK and FBIN. G 11 I Output bank enable. G is the output enable for outputs Y(0:9). When G is low, outputs Y(0:9) are disabled to a logic-low state. When G is high, all outputs Y(0:9) are enabled and switch at the same frequency as CLK. FBOUT 12 O Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. Y (0:9) 3, 4, 5, 8, 9, O Clock outputs. These outputs provide low-skew copies of CLK. Output bank Y(0:9) is enabled via the G in put. These outputs can be 15, 16, 17, disabled to a logic-low state by de-asserting the G control input. 20, 21 AVDD 23 Power Analog power supply. AV DD provides the power reference for the analog circuitry. In addition, AVDD can be used to bypass the PLL for test purposes. When AVDD is strapped to ground, PLL is bypassed and CLK is buffered directly to the device outputs. AGND 1 Ground Analog ground. AGND provides the ground reference for the analog circuitry. VDD 2, 10, 14, 22 Power Power supply GND 6, 7, 18, 19 Ground Ground Inputs Outputs G CLK Y (0:9) FBOUT LL L L LH L H HH H H HL L L H running running running Inputs Outputs G CLK Y (0:9) FBOUT XL L L L running L running in phase with CLK LH L H H running running in running in phase with CLK phase with CLK HH H H

0°C TO 85°C TEMPERATURE RANGE IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER DC ELECTRICAL CHARACTERISTICS OVER OPERATING FREE-AIR TEMPERA- TURE RANGE(1) Symbol Description Test Conditions V DD Min. Typ. (2) Max. Unit VIK Input Clamp Voltage I I = -18mA 3V  – 1.2 V VIH Input HIGH Level  2  V VIL Input LOW Level   0.8 V IOH = -100µA Min. to Max. V DD – 0.2  VOH HIGH Level Output Voltage I OH = -12mA 3V 2.1  V IOH = -6mA 3V 2.4  IOL = 100µA Min. to Max.  0.2 VOL LOW Level Output Voltage I OL = 12mA 3V  0.8 V IOL = 6mA 3V  0.55 II Input Current V I = VDD or GND 3.6V  ±5 µA IDD Supply Current V I = VDD or GND, AV DD = GND, 3.6V  10 µA IO = 0, Outputs: LOW or HIGH ∆IDD Change in Supply Current One input at V DD - 0.6V, other inputs at VDD or GND 3.3V to 3.6V  500 µA CPD Power Dissipation Capacitance 3.6V  10 14 pF IDDA (3) AVDD Power Supply Current AV DD = 3.3V  10  mA NOTES: 1. For Industrial devices, operating free-air temperature = -40°C to +85°C. 2. For conditions shown as Min. or Max., use the appropriate value specified under recommended operating conditions. 3. For I DD of AVDD, see TYPICAL CHARACTERISTICS. Min. Max. Unit Clock frequency 50 175 MHz fCLOCK Input clock duty cycle 40% 60% Stabilization time (2)  1m s TIMING REQUIREMENTS OVER OPERATING RANGE OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE(1) NOTES: 1. For Industrial devices, operating free-air temperature = -40°C to +85°C. 2. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew, and jit ter parameters given in the switching characteristics table are not applicable.

0°C TO 85°C TEMPERATURE RANGE IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER SWITCHING CHARACTERISTICS OVER OPERATING RANGE OF SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE, CL = 30pF(1) VDD = 3.3V ± 0.3V Parameter (2) From (Input) To (Output) Min. Typ. Max. Unit tPHASE error 100MHz < CLK ↑ < 166MHz FBIN ↑ – 150  150 ps tPHASE error – jitter(3) CLK↑ = 166MHz FBIN ↑ – 50  50 ps tSK(o) (4) Any Y (166MHz) Any Y  150 ps Jitter (cycle-cycle) CLK = 166MHz Any Y or FBOUT – 75  75 ps (peak-to-peak) Duty cycle reference (5) CLK = 166MHz Any Y or FBOUT 45  55 % tR Any Y or FBOUT 0.8  2.1 ns tF Any Y or FBOUT 0.8  2.5 ns NOTES: 1. For Industrial devices, operating free-air temperature = -40°C to +85°C. See PARAMETER MEASUREMENT INFORMATION. 2. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed. 3. Phase error does not include jitter. 4. The t SK(O) specification is only valid for equal loading of all outputs. 5. See TYPICAL CHARACTERISTICS.

0°C TO 85°C TEMPERATURE RANGE IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER From Output Under Test 500 Ω Y C F FBIN CLK CSP2510D FBOUT PCB TRACE C L = 30pF (2) 500 Ω on each Y output CLK tPHASE ERROR FBIN FBOUT tSK(o) Any Y Any Y tSK(o) Any Y Input Output or FBIN 50% V DD 50% V DD tR tF 0.4V 0.4V tPHASE ERROR V OL V OH C L = 30pF (2) PARAMETER MEASUREMENT INFORMATION(1) NOTES: 1. All inputs pulses are supplied by generators having the following characteristics: P RR ≤ 100MHz Z O = 50 Ω, tR ≤ 1.2 ns, t F≤ 1.2 ns. 2. C L includes probe and jig capacitance. 3. The outputs are measured one at a time with one transition per measurement. 4. Phase error measurements require equal loading at outputs Y and F BOUT. C F = C L – C FBIN – C PCBTRACE; CFBIN ≅ 6pF. Load Circuit and Voltage Waveforms Phase ERROR and Skew Calculations (3,4)

0°C TO 85°C TEMPERATURE RANGE IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER TYPICAL CHARACTERISTICS Phase Error vs Clock Frequency AVDD and V DD = 3.3V Ta = 25C -200 -150 -100 -50 100 150 200 50 66 100 133 166 175 Clock Frequency (MHz) Time (ps) Analog Supply Current vs Clock Frequency AVDD and V DD = 3.3V Ta = 25C 50 66 100 133 166 175 Clock Frequency (MHz) Analog Current (mA)

0°C TO 85°C TEMPERATURE RANGE IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER TYPICAL CHARACTERISTICS (CONT.) Output Duty Cycle vs Clock Frequency AVDD and V DD = 3.3V Ta = 25C 50 66 100 133 166 175 Clock Frequency (MHz) Duty Cycle (%) Jitter vs Clock Frequency AVDD and V DD = 3.3V Ta = 25C 100 120 140 50 66 100 133 166 175 Clock F requency (MH z) Jitter (ps) Peak-to-Peak Cycle-to-Cycle

0°C TO 85°C TEMPERATURE RANGE IDTCSP2510D 3.3V PHASE-LOCK LOOP CLOCK DRIVER

ORDERING INFORMATION

2510D Phase-Lock Loop Clock Driver PG Thin Shrink Small Outline Package Blank I 0°C to +85°C (Standard) -40°C to +85°C (Industrial) XX X Process CORPORATE HEADQUARTERS for SALES: for Tech Support: 2975 Stender Way 800-345-7015 or 408-727-6116 logichelp@idt.com Santa Clara, CA 95054 fax: 408-492-8674 (408) 654-6459 www.idt.com