CSD95485RWJT | DigiCamel IC Datasheet

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Output Current (A) Efficiency () Power Loss (W) 0 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 30 0 40 2.5 50 5 60 7.5 70 10 80 12.5 90 15 100 17.5 VDD = PVDD = 5 V VIN = 12 V VOUT = 1.8 V LOUT = 150 nH fSW = 600 kHz TA = 25 qC D000 D000 D000 Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD95485RWJ SLPS721 –MARCH 2020 CSD95485RWJSynchronousBuckNexFET™ SmartPowerStage

1 Features

1• 75-A continuous operating current capability

Over 95% system efficiency at 30 A
High-frequency operation (up to 1.25 MHz)
Diode emulation function
Temperature compensated bi-directional current sense
Analog temperature output
Fault monitoring
3.3-V and 5-V PWM signal compatible
Tri-state PWM input
Integrated bootstrap switch
Optimized dead time for shoot-through protection
High-density QFN 5-mm × 6-mm footprint
Ultra-low-inductance package
System optimized PCB footprint
Thermally enhanced topside cooling
RoHS compliant – lead-free terminal plating
Halogen free

2 Applications

Multiphase synchronous buck converters – High-frequency applications – High-current, low-duty cycle applications
POL DC-DC converters
Memory and graphic cards
Desktop and server VR12.x / VR13.x V-core synchronous buck converters

3 Description

The CSD95485RWJ NexFET™ power stage is a highly optimized design for use in a high-power, high- density synchronous buck converter. This product integrates the driver IC and power MOSFETs to complete the power stage switching function. This combination produces high-current, high-efficiency, and high-speed switching capability in a small 5-mm × 6-mm outline package. It also integrates the accurate current sensing and temperature sensing functionality to simplify system design and improve accuracy. In addition, the PCB footprint has been optimized to help reduce design time and simplify the completion of the overall system design. Device Information(1) DEVICE MEDIA QTY PACKAGE SHIP CSD95485RWJ 13-Inch Reel 2500 QFN 5.00-mm × 6.00-mm Package Tape and ReelCSD95485RWJT 7-Inch Reel 250 (1) For all available packages, see the orderable addendum at the end of the data sheet. Application Diagram Typical Power Stage Efficiency and Power Loss

9 Mechanical, Packaging, and Orderable

4 Revision History

March 2020 * Initial release.

10 11 12 13 14 15 16 17 18 19 30313233343536373839 VOS AGND VDD PVDD PGND NC PGND PGND PGND PGND PGND PGND PGND PGND SW SW SW SW SW SW SW SW SW SW VIN BOOT PWM EN/FCCM TAO/FLT IOUT REFIN NC BOOTR LSET VIN VIN VIN VIN VIN

40 VIN

5 Pin Configuration and Functions

DESCRIPTION

VOS 1 Output voltage sensing pin for the internal current sensing circuitry. AGND 2 This pin is internally connected to PGND. VDD 3 Supply voltage for internal circuitry. This pin should be bypassed directly to pin 2. PVDD 4 Supply voltage for gate drivers. This pin should be bypassed to PGND. PGND 5 Power ground. NC 6 Not connected. This pin needs to be left floating in application. PGND 7-9 Power ground. VSW 10-19 Phase node connecting the HS MOSFET source and LS MOSFET drain – pin connection to the output inductor. PGND 20-24 Power ground. VIN 25-30 Input voltage pin. Connect input capacitors close to this pin. NC 31 Not connected. This pin needs to be left floating in application. BOOTR 32 Return path for HS gate driver. It is connected to VSW internally. BOOT 33 Bootstrap capacitor connection. Connect a minimum 0.1-µF, 16-V, X5R ceramic capacitor from BOOT to BOOTR pins. The bootstrap capacitor provides the charge to turn on the control FET. The bootstrap diode is integrated. PWM 34 Tri-state input from external controller. Logic low sets control FET gate low and sync FET gate high. Logic high sets control FET gate high and sync FET gate low. Both MOSFET gates are set low if PWM stays in Hi-Z for greater than the tri-state shutdown holdoff time (T3HT). EN/FCCM 35 This dual function pin either enables the diode emulation function or can be used as a simple enable for the device. When this pin is driven into the tri-state window and held there for more than the tri-state holdoff time, diode emulation mode is enabled for sync FET. When the pin is high, device operates in forced continuous conduction mode. When the pin is low, both FETs are held off. An internal resistor pulls this pin low if left floating. TAO/FLT 36 Temperature amplifier output. Reports a voltage proportional to the IC temperature. An ORing diode is integrated in the IC. When used in a multi-phase application, a single wire can be used to connect the TAO pins of all the ICs. Only the highest temperature will be reported. TAO will be pulled up to 3.3 V if thermal shutdown LSOC or HSS detection circuit is tripped. LSET 37 A resistor from this pin to PGND pin sets the inductor value for the internal current sensing circuitry. IOUT 38 Output of current sensing amplifier. V(IOUT) – V(REFIN) is proportional to the phase current. REFIN 39 External reference voltage input for current sensing amplifier. PGND 40 Power ground. NC 41 Not connected. This pin needs to be left floating in application.

SLPS721 –MARCH 2020 www.ti.com Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) ILOAD is defined as the current flowing out of the VSW pins. (3) Should not exceed 7 V.

6 Specifications

6.1 Absolute Maximum Ratings

TA = 25°C (unless otherwise noted)(1) MIN MAX UNIT VIN to PGND –0.3 20 V VIN to VSW –0.3 20 V VIN to VSW (10 ns) ILOAD > 0 A(2) 23 V VSW to PGND –0.3 20 V VSW to PGND (10 ns) ILOAD < 0 A(2) 23 V VSW to PGND (10 ns) –7 V VDD to PGND –0.3 7 V EN/FCCM, TAO/FLT, LSET to PGND(3) –0.3 VDD + 0.3 V IOUT, VOS, PWM to PGND –0.3 7 V REFIN to PGND –0.3 3.6 V BOOT to PGND –0.3 30 V BOOT to BOOT_R(3) –0.3 VDD + 0.3 V TJ Operating junction temperature –55 150 °C Tstg Storage temperature –55 150 °C

6.2 ESD Ratings

V(ESD) Electrostatic discharge Human-body model (HBM) ±2000 V Charged-device model (CDM) ±500 (1) Operating at high VIN can create excessive AC voltage overshoots on the switch node (VSW) during MOSFET switching transients. For reliable operation, the switch node (VSW) to ground voltage must remain at or below the Absolute Maximum Ratings. (2) Measurement made with six 10-µF (TDK C3216X7R1C106KT or equivalent) ceramic capacitors across VIN to PGND pins. (3) System conditions as defined in Note 2. Peak output current is applied for tp = 50 µs.

6.3 Recommended Operating Conditions

TA = 25°C (unless otherwise stated) MIN MAX UNIT VDD Driver supply voltage 4.5 5.5 V PVDD Gate drive voltage 4.5 5.5 V VIN Input supply voltage(1) 4.5 16 V VOUT Output voltage 5.5 V PWM to PGND VDD + 0.3 V IOUT Continuous output current VIN = 12 V, VDD = 5 V, PVDD = 5 V, VOUT = 1.2 V, ƒSW = 500 kHz(2) 75 A IOUT-PK Peak output current(3) 105 A ƒSW Switching frequency CBST = 0.1 µF (min), VOUT = 2.5 V (max) 1250 kHz On-time duty cycle ƒSW = 1 MHz 85% Minimum PWM on-time 20 ns Operating junction temperature –40 125 °C

6.4 Thermal Information

TA = 25°C (unless otherwise stated) THERMAL METRIC MIN TYP MAX UNIT θJC Thermal resistance, junction-to-case (top of package) 7.4 °C/W θJB Thermal resistance, junction-to-board(1) 2.2 °C/W ΨJT Junction-to-top characterization parameter 0.9 °C/W

7 Application Schematic

Figure 1. Application Schematic

8 Device and Documentation Support

8.1 Trademarks

NexFET is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

8.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

8.3 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

C

1.05 MAX

13X 0.3 0.2 0.05 0.00 16X 0.3 0.2 10X 0.3 0.2 16X 0.45 0.35 2.25 0.1 .000 PKG 0.3 0.1 0.4 0.1 0.8 0.1 0.1 0.1 2.2 0.1 2.6 0.1

0.13 TYP

14X 0.45 1.75 0.1 .000 PKG 0.9 0.1 0.4 0.1 TYP 2.225 0.1 9X 0.45 10X 0.45 2.275 2.175 2.05 1.95 2.025 1.3 0.1 2.05 R0.05 TYP A 6.1 5.9 B 5.1 4.9 (0.203) TYP 4221590/C 01/2017 PIN 1 INDEX AREA 0.08 SEATING PLANE 9 20 10 19 X0.3) (45 PIN 1 ID

0.1 C A B

9 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

9.1 Mechanical Drawing

All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pads must be soldered to the printed circuit board for optimal thermal and mechanical performance.

.0000 .000 PKG 0 ( ) 2.4 ( ) 2 ( )1.75 ( )1.55 3X ( )0.875 ( ) 0.2 ( ) 0.4 3X ( )1.15 ( ) TYP2.22 ( ) TYP2.7 2X ( )2.11 ( ) 2.9 ( )2.25 ( )2.05 ( )1.275 ( ) 0.5 ( ) 0.3 ( ) 0.3 5X ( )1.15 5X ( ) 2 ( ) 2.6 ( ) TYP3.2 ( )0.025 ( ) 2.2 ( ) 0.8 ( ) 0.4 ( ) 0.1 ( ) 0.3 ( )2.25 16X (0.6) 16X (0.25) 14X (0.45) 3X ( ) 2 3X ( ) 1 2X ( ) 1 2X ( ) 2 ( )1.75 ( ) 1.3 ( ) TYP2.7 19X (0.45) ( )1.05 ( )2.025 ( )2.05 ( )2.175 ( ) TYP2.75 20X (0.25) ( ) TYP 2.225 ( ) TYP 2.225 (R0.05) TYP ( ) 0.9 (0.05) MIN TYP ( 0.2) VIA TYP PKG METAL UNDER SOLDER MASK TYP SOLDER MASK OPENING, TYP 10 19 30 39 CSD95485RWJ www.ti.com SLPS721 –MARCH 2020 Submit Documentation FeedbackCopyright © 2020, Texas Instruments Incorporated

9.2 Recommended PCB Land Pattern

All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This package is designed to be soldered to thermal pads on the board. For more information, see QFN/SON PCB Attachment (SLUA271).

.000 PKG .000 PKG 0 29X (0.6) 29X (0.25) 24X (0.45) ( ) TYP2.4 ( ) 2 2X ( )1.665 2X ( )0.975 2X ( )0.775 2X ( )0.085 2X ( )0.42 2X ( )1.05 2X ( )1.25 2X ( ) 1.9 ( ) TYP2.4 4X ( )2.245 4X ( )1.375 4X ( )1.175 4X ( )0.305 3X ( )0.13 3X ( )1.05 3X ( )1.25 4X ( )2.17 ( ) 2.6 ( ) TYP3.2 ( ) TYP2.75 ( )0.375 ( )0.25 ( )0.025 ( ) 0.1 ( ) 0.4 ( )0.84 ( )1.05 2X ( ) 1.9 2X ( ) 1.1 2X ( ) 0.9 2X ( ) 0.1 2X ( ) 0.1 2X ( ) 0.9 ( ) 1.1 ( ) 1.9 10X (0.25) 9X (0.45) ( )2.025 (R0.05) TYP ( )1.75 ( ) 1.3 SOLDER PAST EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED METAL METAL UNDER SOLDER MASK TYP SOLDER MASK OPENING TYP EXPOSED METAL EXPOSED METAL 1 30 39 CSD95485RWJ SLPS721 –MARCH 2020 www.ti.com Submit Documentation Feedback Copyright © 2020, Texas Instruments Incorporated

9.3 Recommended Stencil Opening

All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations.

www.ti.com 5-Mar-2020 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CSD95485RWJ PREVIEW VQFN-CLIP RWJ 41 2500 Pb-Free (RoHS Exempt) SN Level-2-260C-1 YEAR -55 to 150 95485RWJ CSD95485RWJT PREVIEW VQFN-CLIP RWJ 41 250 Pb-Free (RoHS Exempt) SN Level-2-260C-1 YEAR -55 to 150 95485RWJ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

www.ti.com 5-Mar-2020 Addendum-Page 2

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale (www.ti.com/legal/termsofsale.html) or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2020, Texas Instruments Incorporated

Product Information

CSD95485RWJT specifications and overview.

Summary

CSD95485RWJ Synchronous Buck NexFET??Smart Power Stage

Description

CSD95485RWJ Synchronous Buck NexFET??Smart Power Stage

Source title CSD95485RWJT Datasheet(PDF) - Texas Instruments

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