CSD93501-Q1 TI | Alldatasheet
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Technical content
CSD93501-Q1 Synchronous Buck Monolothic Smart Power Stage
1 Features
- 30A TDC current, 60A peak operating current capability
- 91.2% peak system efficiency at 2MHz, 5Vin, 1Vo
- High-frequency operation (up to 2.2 MHz)
- Temperature compensated bi-directional current sense
- Analog temperature output
- 3.3-V and 5-V PWM signal compatible
- Tri-state PWM input
- Integrated bootstrap switch
- Optimized dead-time for shoot-through protection
- Fault Protection – Over temperature (OT) – Pulse-by-pulse over current limiting – Catatraphic Over Current Protection (OCP)
- Fault Detection – High-Side Short (HSS) – Pulse-by-pulse negative Over Current (negOC) detection
- Body Breaking (BB) mode and Diode Emulation Mode (DEM) operation
- 3.5 x 6.25 mm QFN package
- Ultra-low-inductance package
- System optimized PCB footprint
- AEC-Q100 Grade 1 qualified
2 Applications
- Multiphase synchronous buck converters – High-frequency applications – High-current, low-duty cycle applications
3 Description
CSD93501-Q1 is a highly optimized smart power stage for use in a high power, high density applications with 5V input, including automotive. This product integrates the driver IC and power MOSFETs in one silicon die to complete the power stage switching function. It also integrates the accurate current sensing and temperature sensing functionality to simplify system design and improve accuracy. The monolithic design enables high switching frequency with high efficiency, lower noise, and high current- and temperature-sensing accuracy. This product has a small 3.5 x 6.25 mm QFN package. The PCB footprint has been optimized to help reduce design time and simplify the completion of the overall system design. CSD93501-Q1 provides key differentiating features including cycle-by-cycle current limiting/protection based on high-side FET current sense, over temperature protection, negative over current detection, and open pin detection, which improve system reliability. Device Information PART NUMBER PACKAGE(1) BODY SIZE (NOM) CSD93501-Q1 WQFN 3.5 mm × 6.25 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. Simplified Application ADVANCE INFORMATION CSD93501-Q1 SLPS757 – OCTOBER 2022 An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. ADVANCE INFORMATION for preproduction products; subject to change without notice.
8 Mechanical, Packaging, and Orderable Information....7
4 Revision History
October 2022 * Advanced Information CSD93501-Q1 SLPS757 – OCTOBER 2022 www.ti.com ADVANCE INFORMATION
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5 Pin Configuration and Functions
Figure 5-1. RYC Package, 18-PIn WQFN-FCRLF (Top View) Table 5-1. Pin Functions PIN
DESCRIPTION
NAME NO. AGND 1 Analog ground. VDD 2 Supply voltage for internal circuitry. This pin should be bypassed directly to AGND. REFIN 3 External reference voltage input for current sensing amplifier. IOUT 4 Output of current sensing amplifier. V(IOUT) - V(REFIN) is proportional to the phase current. TAO/FLT 5 Temperature Amplifier Output. Reports a voltage proportional to the IC temperature. An ORing diode is integrated in the IC. When used in multiphase applications, a single wire can be used to connect the TAO pins of all the ICs. Only the highest temperature will be reported. TAO will be pulled up to 3.3V if any one of the thermal shutdown, over current protection, or high-side short detection circuits is tripped. PWM 6 Tri-state input from external controller. Logic low sets control FET gate low and sync FET gate high. Logic high sets control FET gate high and sync FET gate low. Either body break or DCM will be inabled if PWM stays in Hi-Z for greater than the tri-state shutdown hold-off time (tSHT). BOOT 7 Bootstrap capacitor connection. Connect a minimum 0.1 µF 10V X7R ceramic capacitor from BOOT to BOOTR pin. The bootstrap capacitor provides the charge to switch the HS FET. The bootstrap diode is integrated. BOOTR 8 Bootstrap capacitor connectioin return path for the HS FET floating driver. Connected to VSW node internally. Connect a minimum 0.1 µF 10V X7R ceramic capacitor from BOOT to BOOTR pin. The bootstrap capacitor provides the charge to switch the HS FET. The bootstrap diode is integrated. VIN 9, 14, 17 Input voltage ping. Connect input capacitors close to this pin. PGND 10, 13, 18 Power ground. VSW 11 Phase node connecting the HS FET source and LS FET drain; pin connection to the output inductor. VDRV 12 Supply voltage for the gate drivers. This pin should be bypassed to PGND. LSET 15 A resistor from this pin to PGND sets the inductor value for the internal current sensing circuitry. EN 16 Enable input pin. The gate driver responds to PWM input when EN is logic high. When EN is logic low, both FET gates are actively driven off. www.ti.com CSD93501-Q1 SLPS757 – OCTOBER 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 3 Product Folder Links: CSD93501-Q1
6 Specifications
6.1 Absolute Maximum Ratings
TA = 25℃ (unless otherwise noted)(1) MIN MAX UNIT VIN to PGND -0.3 11 V VIN to VSW -0.3 11 V VSW to PGND -0.3 11 V VDD to AGND -0.3 6 V VDDRV to PGND -0.3 6 V EN, TAO/FLT, LSET to AGND -0.3 VDD + 0.3 V IOUT, REFIN, VOS, PWM to PGND -0.3 6 V BOOT to BOOTR(2) -0.3 VDD + 0.3 V BOOT to PGND -0.3 17 V TJ Operating junction temperature -40 150 °C Tstg Storage temperature -55 150 °C (1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
6.2 ESD Ratings
V(ESD) Electrostatic discharge Human body model (HBM), per AEC- Q101-001, level H2, all pins -2000 2000 VCharged device model (CDM), per AEC- Q100-011, level C4B, corner pins -750 750 Charged device model (CDM), per AEC- Q100-011, level C4B, all other pins -500 500
6.3 Recommended Operating Conditions
TA = 25 ℃ (unless otherwise noted)(1) MIN MAX UNIT VDD Driver Supply Voltage 4.5 5.5 V VDRV Gate Drive Voltage 4.5 5.5 V VIN Input Supply Voltage(2) 2.7 5.5 V VOUT Output Voltage 2 V PWM to PGND 5.5 V ITDC Thermal Design Current VIN = 5V, VDD = 5V, VDRV = 5V, VOUT = 1V, fSW = 1000 kHz 30 A IOUT-PK Peak Output Current 75 A fSW Switching Frequency CBST = 0.1 µF (min) VIN = 5V, VOUT = 1V 2200 kHz DMAX Max Duty Cycle fSW = 1 MHz, for transient response, not for steady state operation 90 % Minimum PWM On Time 20 ns CSD93501-Q1 SLPS757 – OCTOBER 2022 www.ti.com ADVANCE INFORMATION
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6.3 Recommended Operating Conditions (continued)
TA = 25 ℃ (unless otherwise noted)(1) MIN MAX UNIT TJ Operating Junction Temperature -40 150 °C (1) Exposure to operating conditions beyond those specified in Recommended Operating Conditions may affect the long term reliability of the device. (2) Operating at high VIN can create excessive AC voltage overshoots on the switch node (VSW) during MOSFET switching transients. For reliable operation, the switch node (VSW) to ground voltage must remain at or below the Absolute Maximum Ratings. www.ti.com CSD93501-Q1 SLPS757 – OCTOBER 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 5 Product Folder Links: CSD93501-Q1
7 Device and Documentation Support
7.1 Device Support
7.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
7.2 Documentation Support
7.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on Subscribe to updates to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
7.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight from the experts. Search existing answers or ask your own question to get the quick design help you need. Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use.
7.5 Trademarks
TI E2E™ are trademarks of Texas Instruments. All trademarks are the property of their respective owners.
7.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
7.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions. CSD93501-Q1 SLPS757 – OCTOBER 2022 www.ti.com ADVANCE INFORMATION
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8 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation. www.ti.com CSD93501-Q1 SLPS757 – OCTOBER 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 7 Product Folder Links: CSD93501-Q1
8.1 Package Option Addendum
(1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish MSL Peak Temp (3) Op Temp (°C) Device Marking (4)(5) PCSD93501QRYCTQ1 PRE_PROD WQFN RYC 16 500 PB-Free (RoHS Exempt) CU NIPDAU Level-3-260C-168 HR –40 to 125 P501Q102 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PRE_PROD Unannounced device, not in production, not available for mass market, nor on the web, samples not available. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. space (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) space (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. space (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device space (5) Multiple Device markings will be inside parentheses. Only on Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer: The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. CSD93501-Q1 SLPS757 – OCTOBER 2022 www.ti.com ADVANCE INFORMATION
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8.2 Tape and Reel Information
Reel Width (W1) REEL DIMENSIONS W Dimension designed to accommodate the component length Dimension designed to accommodate the component thickness Overall width of the carrier tape Pitch between successive cavity centers Dimension designed to accommodate the component width TAPE DIMENSIONS B0 W A0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket Quadrants Sprocket Holes Q1 Q1Q2 Q2 Q3 Q3Q4 Q4 Reel Diameter User Direction of Feed Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant www.ti.com CSD93501-Q1 SLPS757 – OCTOBER 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 9 Product Folder Links: CSD93501-Q1
www.ti.com WQFN-FCRLF - 0.7 mm max heightPLASTIC QUAD FLAT PACK- NO LEADRYC0016AA 0.08C 3.63.4
0.70.6 SEATING PLANE
C (0.20) TYP 0.010.000.1CAB0.05C PIN 1 ID(OPTIONAL) B 6.356.15 34X 0.230.1316X 0.30.2 32X 0.52X 5.5 2X 2.516X0.550.45 (0.35)(0.375) 3X (0.5)3X (0.625) 2.275±0.12.375±0.1 0.125±0.10.000 PKG ℄ 0.9±0.1 0.9±0.10.000 PKG ℄ 12 14131211 1096 0.10 MIN(0.1) TYP(0.20) SECTION A-ATYPICAL (0.12) TYP AA CSD93501-Q1 SLPS757 – OCTOBER 2022 www.ti.com ADVANCE INFORMATION
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www.ti.com WQFN-FCRLF - 0.7 mm max heightRYC0016APLASTIC QUAD FLAT PACK- NO LEAD LAND PATTERN EXAMPLEEXPOSED METAL SHOWNSCALE: 15X SOLDER MASK DETAILS 0.05 MAXALL AROUND0.05 MINALL AROUNDMETALSOLDER MASKOPENINGEXPOSED METALSOLDER MASKOPENINGMETAL UNDERSOLDER MASKEXPOSED METALNON- SOLDER MASKDEFINEDSOLDER MASKDEFINED
0.000 PKG ℄
2X (5.5) 2X (2.5) (Ø0.2) TYP 2X (0.6)2X (0.6) (1.6) (1.6) (0.9) (0.9)0.000 PKG ℄ 3X (0.825) 3X (1.175) (2.975) (1.375)(0.275) (2.275) (0.075)(0.05) MINALL AROUNDTYP 34X (0.25) 8X (0.7) 4X (0.375)4X (0.5) (0.325) TYP 1 14131211 1096 6X (1.08) www.ti.com CSD93501-Q1 SLPS757 – OCTOBER 2022 ADVANCE INFORMATION Copyright © 2022 Texas Instruments Incorporated Submit Document Feedback 11 Product Folder Links: CSD93501-Q1
www.ti.com WQFN-FCRLF - 0.7 mm max heightRYC0016APLASTIC QUAD FLAT PACK- NO LEAD SOLDER PASTE EXAMPLEBASED ON 0.1 mm THICK STENCILSOLDER PASTE COVERAGE:PIN 17 : 86%PIN 18 : 81%SCALE: 15X NOTES: (continued)6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternatedesign recommendations. 2X (5.5) 2X (2.5) (1.6) (1.6) (0.825) (2.975) 34X (0.25) 8X (0.7) 4X (0.375)4X (0.5) (0.325) TYP 1 14131211 1096 (0.825)(0.825) 3X (1.63) 1718 CSD93501-Q1 SLPS757 – OCTOBER 2022 www.ti.com ADVANCE INFORMATION
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