CSD87335Q3DG4

CSD87335Q3D_V01 TI | Alldatasheet

Document overview

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Technical content

Output Current (A) Efficiency (%) Power Loss (W) 0 5 10 15 20 25 60 0 70 1.5 80 3 90 4.5 100 6 D000 VGS = 5 V VIN = 12 V VOUT = 1.3 V LOUT = 950 nH fSW = 500 kHz TA = 25qC VDD BOOTVDD ENABLE PWM VIN VIN VOUT Driver IC CSD87335Q3D TG Control FET Sync FET DRVH LL DRVL GND ENABLE PWM VSW PGND TGR BG Copyright © 2017, Texas Instruments Incorporated P0116-01

3 VSW

4 BG5TGR

(Pin□9) 7VIN 8VIN Product Folder Order Now T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD87335Q3D SLPS574B –FEBRUARY 2016–REVISED APRIL 2018 CSD87335Q3DSynchronousBuckNexFET™ PowerBlock

1 Features

1• Half-Bridge Power Block

• Up to 27-V VIN
• 93.5% System Efficiency at 15 A
• Up to 25-A Operation
• High-Frequency Operation (Up to 1.5 MHz)
• High-Density SON 3.3-mm × 3.3-mm Footprint
• Optimized for 5-V Gate Drive
• Low-Switching Losses
• Ultra-Low Inductance Package
• RoHS Compliant
• Halogen Free
• Lead-Free Terminal Plating

2 Applications

• Synchronous Buck Converters – High-Frequency Applications – High-Current, Low-Duty Cycle Applications
• Multiphase Synchronous Buck Converters
• POL DC-DC Converters
• IMVP, VRM, and VRD Applications

3 Description

The CSD87335Q3D NexFET™ power block is an optimized design for synchronous buck applications offering high-current, high-efficiency, and high- frequency capability in a small 3.3-mm × 3.3-mm outline. Optimized for 5-V gate drive applications, this product offers a flexible solution capable of offering a high-density power supply when paired with any 5-V gate drive from an external controller or driver. Top View Device Information(1) DEVICE MEDIA QTY PACKAGE SHIP CSD87335Q3D 13-Inch Reel 2500 SON 3.30-mm × 3.30-mm Plastic Package Tape and ReelCSD87335Q3DT 7-Inch Reel 250 (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Circuit Typical Power Block Efficiency and Power Loss

SLPS574B –FEBRUARY 2016–REVISED APRIL 2018 www.ti.com Product Folder Links: CSD87335Q3D Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated Table of Contents 8.1 Receiving Notification of Documentation Updates.. 17

9 Mechanical, Packaging, and Orderable

4 Revision History

Changes from Revision A (October 2017) to Revision B Page Changes from Original (February 2016) to Revision A Page

www.ti.com SLPS574B –FEBRUARY 2016–REVISED APRIL 2018 Product Folder Links: CSD87335Q3D Submit Documentation FeedbackCopyright © 2016–2018, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Pulse duration ≤ 50 µs, duty cycle ≤ 1%.

5 Specifications

5.1 Absolute Maximum Ratings

TA = 25°C (unless otherwise noted)(1) MIN MAX UNIT Voltage VIN to PGND 30 V VSW to PGND 30 VSW to PGND (10 ns) 32 TG to TGR –8 10 BG to PGND –8 10 Pulsed current rating, IDM(2) 70 A Power dissipation, PD 6 W Avalanche energy, EAS Sync FET, ID = 51 A, L = 0.1 mH 130 mJ Control FET, ID = 33 A, L = 0.1 mH 54 Operating junction and storage temperature, TJ, TSTG –55 150 °C

5.2 Recommended Operating Conditions

TA = 25°C (unless otherwise noted) MIN MAX UNIT VGS Gate drive voltage 4.5 8 V VIN Input supply voltage 27 V ƒSW Switching frequency CBST = 0.1 µF (min) 1500 kHz Operating current 25 A TJ Operating temperature 125 °C (1) RθJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in design. (2) Device mounted on FR4 material with 1-in2 (6.45-cm2) Cu.

5.3 Thermal Information

TA = 25°C (unless otherwise stated) THERMAL METRIC MIN TYP MAX UNIT RθJA Junction-to-ambient thermal resistance (min Cu)(1) 135 °C/W Junction-to-ambient thermal resistance (max Cu)(1)(2) 73 RθJC Junction-to-case thermal resistance (top of package)(1) 29 °C/W Junction-to-case thermal resistance (PGND pin)(1) 2.5 (1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and using a high-current 5-V driver IC.

5.4 Power Block Performance(1)

TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT PLOSS Power loss(1) VIN = 12 V, VGS = 5 V, VOUT = 1.3 V, IOUT = 15 A, ƒSW = 500 kHz, LOUT = 950 nH, TJ = 25°C 1.5 W IQVIN VIN quiescent current TG to TGR = 0 V, BG to PGND = 0 V 10 µA

SLPS574B –FEBRUARY 2016–REVISED APRIL 2018 www.ti.com Product Folder Links: CSD87335Q3D Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated

5.5 Electrical Characteristics

TA = 25°C (unless otherwise stated) PARAMETER TEST CONDITIONS Q1 Control FET Q2 Sync FET UNIT MIN TYP MAX MIN TYP MAX STATIC CHARACTERISTICS BVDSS Drain-to-source voltage VGS = 0 V, IDS = 250 µA 30 30 V IDSS Drain-to-source leakage current VGS = 0 V, VDS = 24 V 1 1 µA IGSS Gate-to-source leakage current VDS = 0 V, VGS = +10 V / –8 V 100 100 nA VGS(th) Gate-to-source threshold voltage VDS = VGS, IDS = 250 µA 1.0 1.9 0.75 1.20 V ZDS(on) Effective AC on-impedance VIN = 12 V, VGS = 5 V, VOUT = 1.3 V, IOUT = 15 A, ƒSW = 500 kHz, LOUT = 950 nH 6.7 1.9 mΩ gfs Transconductance VDS = 3 V, IDS = 15 A 59 107 S DYNAMIC CHARACTERISTICS CISS Input capacitance VGS = 0 V, VDS = 15 V, ƒ = 1 MHz 805 1050 1620 2100 pF COSS Output capacitance 412 536 783 1020 pF CRSS Reverse transfer capacitance 15 20 28 36 pF RG Series gate resistance 1.2 2.4 0.6 1.2 Ω Qg Gate charge total (4.5 V) VDS = 15 V, IDS = 15 A 5.7 7.4 10.7 14.0 nC Qgd Gate charge – gate-to-drain 1.1 1.7 nC Qgs Gate charge – gate-to-source 2.1 2.8 nC Qg(th) Gate charge at Vth 1.1 1.4 nC QOSS Output charge VDS = 15 V, VGS = 0 V 11 19 nC td(on) Turnon delay time VDS = 15 V, VGS = 4.5 V, IDS = 15 A, RG = 2 Ω 8 8 ns tr Rise time 29 27 ns td(off) Turnoff delay time 13 17 ns tf Fall time 4 5 ns DIODE CHARACTERISTICS VSD Diode forward voltage IDS = 15 A, VGS = 0 V 0.8 1.0 0.8 1.0 V Qrr Reverse recovery charge VDS = 15 V, IF = 15 A, di/dt = 300 A/µs 24 40 nC trr Reverse recovery time 17 22 ns Max RθJA = 73°C/W when mounted on 1 in2 (6.45 cm2) of 2-oz (0.071-mm) thick Cu. Max RθJA = 135°C/W when mounted on minimum pad area of 2-oz. (0.071-mm) thick Cu.

400 LFM

200 LFM

100 LFM

5.6 Typical Power Block Device Characteristics

Figure 1. Power Loss vs Output Current Figure 2. Power Loss vs Temperature Figure 3. Safe Operating Area – PCB Horizontal Mount(1) Implementation section for detailed explanation.

5.7 Typical Power Block MOSFET Characteristics

TA = 25°C, unless stated otherwise. Figure 9. Control MOSFET Saturation Figure 10. Sync MOSFET Saturation Figure 11. Control MOSFET Transfer Figure 12. Sync MOSFET Transfer Figure 13. Control MOSFET Gate Charge Figure 14. Sync MOSFET Gate Charge

6 Applications and Implementation

validate and test their design implementation to confirm system functionality.

6.1 Application Information

6.1.1 Equivalent System Performance

Figure 27. Equivalent System Schematic Inductance Consideration for Synchronous Buck Converters (SLPA009).

MOSFETs or dual MOSFETs in a standard package. Table 1. Comparison of RDS(ON) vs. ZDS(ON) normalized graphs allow engineers to predict the product performance in the actual application.

6.2 Power Loss Curves

MOSFET centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices. gate drive loss. Equation 1 is used to generate the power loss curve. under isothermal test conditions.

6.3 Safe Operating Curves (SOA)

3.5 in (L) × 0.062 in (T) and 6 copper layers of 1-oz copper thickness.

6.4 Normalized Curves

subtracted from the SOA curve.

Figure 31. Typical Application

6.5 Calculating Power Loss and SOA

The user can estimate product loss and SOA boundaries by arithmetic means (see Design Example section).

6.5.1 Design Example

• Output current = 15 A
• Input voltage = 14 V
• Output voltage = 1.4 V
• Switching frequency = 750 kHz
• Inductor = 600 nH

6.5.2 Calculating Power Loss

• Power loss at 15 A = 1.92 W (Figure 1)
• Normalized power loss for input voltage ≈ 1.01 (Figure 6)
• Normalized power loss for output voltage ≈ 1.01 (Figure 7)
• Normalized power loss for switching frequency ≈ 1.08 (Figure 5)
• Normalized power loss for output inductor ≈ 1.01 (Figure 8)

6.5.3 Calculating SOA Adjustments

• SOA adjustment for input voltage ≈ 0.14°C (Figure 6)
• SOA adjustment for output voltage ≈ 0.17°C (Figure 7)
• SOA adjustment for switching frequency ≈ 1.32°C (Figure 5)
• SOA adjustment for output inductor ≈ 0.18°C (Figure 8)

www.ti.com SLPS574B –FEBRUARY 2016–REVISED APRIL 2018 Product Folder Links: CSD87335Q3D Submit Documentation FeedbackCopyright © 2016–2018, Texas Instruments Incorporated (1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of Missouri – Rolla

7 Recommended PCB Design Overview

There are two key system-level parameters that can be addressed with a proper PCB design: electrical and thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. A brief description on how to address each parameter is provided.

7.1 Electrical Performance

The power block has the ability to switch voltages at rates greater than 10 kV/µs. Special care must be then taken with the PCB layout design and placement of the input capacitors, driver IC, and output inductor.

• The placement of the input capacitors relative to the power block’s VIN and PGND pins should have the highest priority during the component placement routine. It is critical to minimize these node lengths. As such, ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 33). The example in Figure 33 uses 6 × 10-µF ceramic capacitors (TDK Part # C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the power block, C5, C7, C19, and C8 should follow in order.
• The driver IC should be placed relatively close to the power block gate pins. TG and BG should connect to the outputs of the driver IC. The TGR pin serves as the return path of the high-side gate drive circuitry and should be connected to the phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrap capacitor for the driver IC will also connect to this pin.
• The switching node of the output inductor should be placed relatively close to the power block VSW pins. Minimizing the node length between these two components will reduce the PCB conduction losses and actually reduce the switching noise level. In the event the switch node waveform exhibits ringing that reaches undesirable levels, the use of a boost resistor or RC snubber can be an effective way to easily reduce the peak ring level. The recommended boost resistor value will range between 1 Ω to 4.7 Ω depending on the output characteristics of driver IC used in conjunction with the power block. The RC snubber values can range from 0.5 Ω to 2.2 Ω for the R and 330 pF to 2200 pF for the C. Please refer to Snubber Circuits: Theory, Design and Application (SLUP100) for more details on how to properly tune the RC snubber values. The RC snubber should be placed as close as possible to the Vsw node and PGND (see Figure 33). (1)

7.2 Thermal Performance

• Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
• Use the smallest drill size allowed in your design. The example in Figure 33 uses vias with a 10-mil drill hole and a 16-mil capture pad.
• Tent the opposite side of the via with solder-mask. In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and manufacturing capabilities.

Figure 33. Recommended PCB Layout (Top Down)

www.ti.com SLPS574B –FEBRUARY 2016–REVISED APRIL 2018 Product Folder Links: CSD87335Q3D Submit Documentation FeedbackCopyright © 2016–2018, Texas Instruments Incorporated

8 Device and Documentation Support

8.1 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.

8.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.

8.3 Trademarks

NexFET, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.

8.4 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

8.5 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.

SLPS574B –FEBRUARY 2016–REVISED APRIL 2018 www.ti.com Product Folder Links: CSD87335Q3D Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated

9 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

9.1 Q3D Package Dimensions

A 1.400 1.500 0.055 0.059 b 0.280 0.400 0.011 0.016 b1 0.310 NOM 0.012 NOM c 0.150 0.250 0.006 0.010 c1 0.150 0.250 0.006 0.010 d 0.940 1.040 0.037 0.041 d1 0.160 0.260 0.006 0.010 d2 0.150 0.250 0.006 0.010 d3 0.250 0.350 0.010 0.014 d4 0.175 0.275 0.007 0.011 D1 3.200 3.400 0.126 0.134 D2 2.650 2.750 0.104 0.108 E 3.200 3.400 0.126 0.134 E1 3.200 3.400 0.126 0.134 E2 1.750 1.850 0.069 0.073 e 0.650 TYP 0.026 TYP L 0.400 0.500 0.016 0.020 θ 0.00 — — — K 0.300 TYP 0.012 TYP

0.300□(0.012) 0.300□(0.012) 0.300 (0.012) M0207-01 0.340 (0.013) 0.333 (0.013) 0.100 0.160□(0.005) 2.290 (0.090) 0.350□(0.014) 0.850□(0.033) 0.990 (0.039) 0.200 (0.008) 0.350□(0.014) 0.210 (0.008) M0193-01 0.440 (0.017) 0.210 (0.008) 1.900□(0.075) 0.300□(0.012) 3.600□(0.142) 2.800 (0.110) 0.650 (0.026) 1.090 (0.043) 2.390 (0.094) CSD87335Q3D www.ti.com SLPS574B –FEBRUARY 2016–REVISED APRIL 2018 Product Folder Links: CSD87335Q3D Submit Documentation FeedbackCopyright © 2016–2018, Texas Instruments Incorporated

9.2 Land Pattern Recommendation

NOTE: Dimensions are in mm (inches).

9.3 Stencil Recommendation

NOTE: Dimensions are in mm (inches). For recommended circuit layout for PCB designs, see Reducing Ringing Through PCB Layout Techniques (SLPA005).

4.00 ±0.10 (See Note 1) 2.00 ±0.05 3.60 3.60 1.30 1.75 ±0.10 M0144-01 8.00 ±0.10 12.00 +0.30 –0.10 5.50 ±0.05 Ø 1.50 +0.10 –0.00 CSD87335Q3D SLPS574B –FEBRUARY 2016–REVISED APRIL 2018 www.ti.com Product Folder Links: CSD87335Q3D Submit Documentation Feedback Copyright © 2016–2018, Texas Instruments Incorporated

9.4 Q3D Tape and Reel Information

NOTES: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2. 2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm. 3. Material: black static-dissipative polystyrene. 4. All dimensions are in mm, unless otherwise specified. 5. Thickness: 0.3 ±0.05 mm. 6. MSL1 260°C (IR and convection) PbF reflow compatible.

9.5 Pin Configuration

www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) CSD87335Q3D Active Production LSON-CLIP (DQZ) | 8 2500 | LARGE T&R ROHS Exempt NIPDAU | SN Level-1-260C-UNLIM -55 to 150 87335D CSD87335Q3D.B Active Production LSON-CLIP (DQZ) | 8 2500 | LARGE T&R ROHS Exempt NIPDAU Level-1-260C-UNLIM -55 to 150 87335D CSD87335Q3DG4 Active Production LSON-CLIP (DQZ) | 8 2500 | LARGE T&R ROHS Exempt NIPDAU Level-1-260C-UNLIM -55 to 150 87335D CSD87335Q3DG4.B Active Production LSON-CLIP (DQZ) | 8 2500 | LARGE T&R ROHS Exempt NIPDAU Level-1-260C-UNLIM -55 to 150 87335D CSD87335Q3DT Active Production LSON-CLIP (DQZ) | 8 250 | SMALL T&R ROHS Exempt NIPDAU | SN Level-1-260C-UNLIM -55 to 150 87335D CSD87335Q3DT.B Active Production LSON-CLIP (DQZ) | 8 250 | SMALL T&R ROHS Exempt NIPDAU Level-1-260C-UNLIM -55 to 150 87335D (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

www.ti.com 7-Oct-2025 Addendum-Page 2

www.ti.com PACKAGE OUTLINE C 8X 0.40 0.28 2.7 0.1 8X 0.5 0.4 1.95 1.8 0.1 6X 0.65 1.55 1.45 0.05 0.00 0.32 0.12 B 3.4 3.2 A 3.4 3.2 (0.2) TYP4X (0.2) 2X (0.98) LSON-CLIP - 1.55 mm max heightDQZ0008A PLASTIC SMALL OUTLINE - NO LEAD 4229809/A 07/2023 PIN 1 INDEX AREA SEATING PLANE 0.08 C 4 5

0.1 C A B

0.05 C EXPOSED THERMAL PAD SYMM SYMM NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.600

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

(1.8) 6X (0.65) (3.05) 2X (0.34) 2X (0.65) (2.7) (R0.05) TYP ( 0.2) VIA TYP (0.22) 4X (0.2) 2X (1.18) 6X (0.65) 6X (0.34) 4X (0.5) 2X (1.1) 2X (0.65) LSON-CLIP - 1.55 mm max heightDQZ0008A PLASTIC SMALL OUTLINE - NO LEAD 4229809/A 07/2023 PKG 4 5 PKG LAND PATTERN EXAMPLE SCALE:20X METAL UNDER SOLDER MASK SOLDER MASK OPENING NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 2X (0.34) 2X (0.65) 6X (0.65) (3.05) (R0.05) TYP 6X (0.34)(0.22) 6X (0.65) 2X (1.63) (1.19) (0.695) 2X (1.18) 2X (3.34) LSON-CLIP - 1.55 mm max heightDQZ0008A PLASTIC SMALL OUTLINE - NO LEAD 4229809/A 07/2023 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 9 76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X PKG 4 5 PKG METAL TYP 9METAL UNDER SOLDER MASK

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