CSD86350Q5D_V01 TI | Alldatasheet
Document overview
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Technical content
Output Current (A) Efficiency (%) Power Loss (W) 0 5 10 15 20 25 40 0 50 1 60 2 70 3 80 4 90 5 100 6 G029 VGS = 5V VIN = 12V VOUT = 1.3V LOUT = 0.3,H fSW = 500kHz TA = 25C TGR VIN PGND VSW TG BG S0474-01 ENABLE ENABLE PWM GND BST DRVH LL DRVL CSD86350Q5DDriver IC VDD VI VO VDD Control FET Sync FET PWM P0116-01
3 VSW
4 BG5TGR
(Pin□9) 7VIN 8VIN Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD86350Q5D SLPS223F –MAY 2010–REVISED OCTOBER 2016 CSD86350Q5DSynchronousBuckNexFET™ PowerBlock
1 Features
1• Half-Bridge Power Block
- 90% System Efficiency at 25 A
- Up to 40-A Operation
- High-Frequency Operation (up to 1.5 MHz)
- High-Density SON 5-mm × 6-mm Footprint
- Optimized for 5-V Gate Drive
- Low-Switching Losses
- Ultra-Low Inductance Package
- RoHS Compliant
- Halogen Free
- Lead-Free Terminal Plating
2 Applications
- Synchronous Buck Converters – High-Frequency Applications – High-Current, Low-Duty Cycle Applications
- Multiphase Synchronous Buck Converters
- POL DC-DC Converters
- IMVP, VRM, and VRD Applications
3 Description
The CSD86350Q5D NexFET™ power block is an optimized design for synchronous buck applications offering high-current, high-efficiency, and high- frequency capability in a small 5-mm × 6-mm outline. Optimized for 5-V gate drive applications, this product offers a flexible solution capable of offering a high- density power supply when paired with any 5-V gate drive from an external controller/driver. Top View Device Information(1) DEVICE MEDIA QTY PACKAGE SHIP CSD86350Q5D 13-Inch Reel 2500 SON 5.00-mm × 6.00-mm Plastic Package Tape and ReelCSD86350Q5DT 7-Inch Reel 250 (1) For all available packages, see the orderable addendum at the end of the data sheet. Typical Circuit Typical Power Block Efficiency and Power Loss
SLPS223F –MAY 2010–REVISED OCTOBER 2016 www.ti.com Product Folder Links: CSD86350Q5D Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated Table of Contents 8.2 Receiving Notification of Documentation Updates.. 18
9 Mechanical, Packaging, and Orderable
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision E (October 2011) to Revision F Page Changes from Revision D (September 2011) to Revision E Page Changes from Revision C (November 2010) to Revision D Page Changes from Revision B (September 2010) to Revision C Page Changes from Revision A (May 2010) to Revision B Page
www.ti.com SLPS223F –MAY 2010–REVISED OCTOBER 2016 Product Folder Links: CSD86350Q5D Submit Documentation FeedbackCopyright © 2010–2016, Texas Instruments Incorporated Changes from Original (May 2010) to Revision A Page
- Changed graph title From: TYPICAL EFFICIENCY vs POWER LOSS To: TYPICAL POWER BLOCK EFFICIENCY
SLPS223F –MAY 2010–REVISED OCTOBER 2016 www.ti.com Product Folder Links: CSD86350Q5D Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) Pulse duration ≤ 50 µs, duty cycle ≤ 1%.
5 Specifications
5.1 Absolute Maximum Ratings
TA = 25°C (unless otherwise noted)(1) MIN MAX UNIT Voltage VIN to PGND –0.8 25 VTG to TGR –8 10 BG to PGND –8 10 Pulsed current rating, IDM(2) 120 A Power dissipation, PD 13 W Avalanche energy, EAS Sync FET, ID = 100 A, L = 0.1 mH 500 mJ Control FET, ID = 58 A, L = 0.1 mH 168 Operating junction, TJ –55 150 °C Storage temperature, TSTG –55 150 °C
5.2 Recommended Operating Conditions
TA = 25° (unless otherwise noted) MIN MAX UNIT VGS Gate drive voltage 4.5 8 V VIN Input supply voltage 22 V fSW Switching frequency CBST = 0.1 μF (min) 200 1500 kHz Operating current 40 A TJ Operating temperature 125 °C (1) Device mounted on FR4 material with 1-in2 (6.45-cm2) Cu. (2) RθJC is determined with the device mounted on a 1-in2 (6.45-cm2), 2 oz (0.071-mm) thick Cu pad on a 1.5-in × 1.5-in design.
5.3 Thermal Information
TA = 25°C (unless otherwise stated) THERMAL METRIC MIN TYP MAX UNIT RθJA Junction-to-ambient thermal resistance (min Cu)(1)(2) 102 °C/W Junction-to-ambient thermal resistance (max Cu)(1)(2) 50 °C/W RθJC Junction-to-case thermal resistance (top of package)(2) 20 °C/W Junction-to-case thermal resistance (PGND pin)(2) 2 °C/W (1) Measurement made with six 10-µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and using a high-current 5-V driver IC.
5.4 Power Block Performance
TA = 25° (unless otherwise noted) PARAMETER CONDITIONS MIN TYP MAX UNIT PLOSS Power loss(1) VIN = 12 V, VGS = 5 V, VOUT = 1.3 V, IOUT = 25 A, fSW = 500 kHz, LOUT = 0.3 µH, TJ = 25°C 2.8 W IQVIN VIN quiescent current TG to TGR = 0 V BG to PGND = 0 V 10 µA
86350□5x6□QFN□TTA□MIN□Rev1 LS HS HD HG LG LD M0190-01 86350□5x6□QFN□TTA□MIN□Rev1 LS HS CSD86350Q5D www.ti.com SLPS223F –MAY 2010–REVISED OCTOBER 2016 Product Folder Links: CSD86350Q5D Submit Documentation FeedbackCopyright © 2010–2016, Texas Instruments Incorporated (1) Specified by design.
5.5 Electrical Characteristics
TA = 25°C (unless otherwise stated) PARAMETER TEST CONDITIONS Q1 Control FET Q2 Sync FET UNIT MIN TYP MAX MIN TYP MAX STATIC CHARACTERISTICS BVDSS Drain-to-source voltage VGS = 0 V, IDS = 250 μA 25 25 V IDSS Drain-to-source leakage current VGS = 0 V, VDS = 20 V 1 1 μA IGSS Gate-to-source leakage current VDS = 0 V, VGS = +10 / –8 V 100 100 nA ZDS(on) Drain-to-source on impedance VIN = 12 V, VDD = 5 V, VOUT = 1.3 V, IOUT = 25 A, fSW = 500 kHz, LOUT = 0.3 µH 5 1.1 mΩ gfs Transconductance VDS = 10 V, IDS = 20 A 103 132 S DYNAMIC CHARACTERISTICS CISS Input capacitance(1) VGS = 0 V, VDS = 12.5 V, f = 1 MHz 1440 1870 3080 4000 pF COSS Output capacitance(1) 645 840 1550 2015 pF CRSS Reverse transfer capacitance(1) 22 29 45 59 pF RG Series gate resistance(1) 1.4 2.8 1.4 2.8 Ω Qg Gate charge total (4.5 V)(1) VDS = 12.5 V, IDS = 20 A 8.2 10.7 19.4 25 nC Qgd Gate charge – gate-to-drain 1 2.5 nC Qgs Gate charge – gate-to-source 3.2 5.1 nC Qg(th) Gate charge at Vth 1.9 2.8 nC QOSS Output charge VDS = 12 V, VGS = 0 V 9.9 28 nC td(on) Turnon delay time VDS = 12.5 V, VGS = 4.5 V, IDS = 20 A, RG = 2 Ω 8 9 ns tr Rise time 21 23 ns td(off) Turnoff delay time 9 24 ns tf Fall time 2.3 21 ns DIODE CHARACTERISTICS VSD Diode forward voltage IDS = 20 A, VGS = 0 V 0.85 1 0.77 1 V Qrr Reverse recovery charge Vdd = 12 V, IF = 20 A, di/dt = 300 A/μs 16 40 nC trr Reverse recovery time 22 32 ns Max RθJA = 50°C/W when mounted on 1-in2 (6.45-cm2) of 2-oz (0.071-mm) thick Cu. Max RθJA = 102°C/W when mounted on minimum pad area of 2-oz (0.071-mm) thick Cu.
× 3.5 in (L) x 0.062 in (H) and 6 copper layers of 1-oz copper thickness. See Application and Implementation for detailed explanation.
5.6 Typical Power Block Device Characteristics
TJ = 125°C, unless stated otherwise. Figure 1. Power Loss vs Output Current Figure 2. Normalized Power Loss vs Temperature Figure 3. Safe Operating Area – PCB Vertical Mount (1) Figure 4. Safe Operating Area – PCB Horizontal Mount (1) Figure 5. Typical Safe Operating Area (1)
5.7 Typical Power Block MOSFET Characteristics
TA = 25°C, unless stated otherwise. Figure 10. Control MOSFET Saturation Figure 11. Sync MOSFET Saturation Figure 12. Control MOSFET Transfer Figure 13. Sync MOSFET Transfer Figure 14. Control MOSFET Gate Charge Figure 15. Sync MOSFET Gate Charge
6 Application and Implementation
validate and test their design implementation to confirm system functionality.
6.1 Application Information
6.1.1 Equivalent System Performance
Figure 28. Equivalent System Schematic Inductance Consideration for Synchronous Buck Converters (SLPA009).
MOSFETs or dual MOSFETs in a standard package. Table 1. Comparison of RDS(ON) vs. ZDS(ON) normalized graphs allow engineers to predict the product performance in the actual application.
6.1.2 Power Loss Curves
MOSFET centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices. gate drive loss. Equation 1 is used to generate the power loss curve. under isothermal test conditions.
6.1.3 Safe Operating Area (SOA) Curves
3.5 in (L) × 0.062 in (T) and 6 copper layers of 1-oz copper thickness.
6.1.4 Normalized Curves
subtracted from the SOA curve.
Figure 32. Typical Application
6.1.5 Calculating Power Loss and SOA
6.1.5.1 Design Example
- Output Current = 25 A
- Input Voltage = 7 V
- Output Voltage = 1 V
- Switching Frequency = 800 kHz
- Inductor = 0.2 µH
6.1.5.2 Calculating Power Loss
- Power loss at 25 A = 3.5 W (Figure 1)
- Normalized power loss for input voltage ≈ 1.07 (Figure 7)
- Normalized power loss for output voltage ≈ 0.95 (Figure 8)
- Normalized power loss for switching frequency ≈ 1.11 (Figure 6)
- Normalized power loss for output inductor ≈ 1.07 (Figure 9)
6.1.5.3 Calculating SOA Adjustments
- SOA adjustment for input voltage ≈ 2°C (Figure 7)
- SOA adjustment for output voltage ≈ –1.3°C (Figure 8)
- SOA adjustment for switching frequency ≈ 2.8°C (Figure 6)
- SOA adjustment for output inductor ≈ 1.6°C (Figure 9)
- Final calculated SOA adjustment = 2 + (–1.3) + 2.8 + 1.6 ≈ 5.1°C In the design example above, the estimated power loss of the CSD86350Q5D would increase to 4.23 W. In addition, the maximum allowable board and/or ambient temperature would have to decrease by 5.1°C. Figure 33 graphically shows how the SOA curve would be adjusted accordingly. 1. Start by drawing a horizontal line from the application current to the SOA curve. 2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature.
- Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value.
would yield an increase in allowable board/ambient temperature. Figure 33. Power Block SOA
SLPS223F –MAY 2010–REVISED OCTOBER 2016 www.ti.com Product Folder Links: CSD86350Q5D Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated (1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of Missouri – Rolla
7 Layout
7.1 Layout Guidelines
There are two key system-level parameters that can be addressed with a proper PCB design: electrical and thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. A brief description on how to address each parameter is provided.
7.1.1 Electrical Performance
The power block has the ability to switch voltages at rates greater than 10 kV/µs. Special care must be then taken with the PCB layout design and placement of the input capacitors, driver IC, and output inductor.
- The placement of the input capacitors relative to the power block’s VIN and PGND pins should have the highest priority during the component placement routine. It is critical to minimize these node lengths. As such, ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 34). The example in Figure 34 uses 6 × 10-µF ceramic capacitors (TDK part C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the power block, C5, C7, C19, and C8 should follow in order.
- The driver IC should be placed relatively close to the power block gate pins. TG and BG should connect to the outputs of the driver IC. The TGR pin serves as the return path of the high-side gate drive circuitry and should be connected to the phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrap capacitor for the driver IC will also connect to this pin.
- The switching node of the output inductor should be placed relatively close to the power block VSW pins. Minimizing the node length between these two components will reduce the PCB conduction losses and actually reduce the switching noise level. In the event the switch node waveform exhibits ringing that reaches undesirable levels, the use of a boost resistor or RC snubber can be an effective way to easily reduce the peak ring level. The recommended boost resistor value will range between 1 Ω to 4.7 Ω depending on the output characteristics of driver IC used in conjunction with the power block. The RC snubber values can range from 0.5 Ω to 2.2 Ω for the R and 330 pF to 2200 pF for the C. Please refer to Snubber Circuits: Theory, Design and Application (SLUP100) for more details on how to properly tune the RC snubber values. The RC snubber should be placed as close as possible to the VSW node and PGND see Figure 34. (1)
7.1.2 Thermal Performance
The power block has the ability to utilize the GND planes as the primary thermal path. As such, the use of thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount of solder attach that will wick down the via barrel:
- Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
- Use the smallest drill size allowed in your design. The example in Figure 34 uses vias with a 10-mil drill hole and a 16-mil capture pad.
- Tent the opposite side of the via with solder-mask. In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and manufacturing capabilities.
7.2 Layout Example
Figure 34. Recommended PCB Layout (Top Down View)
SLPS223F –MAY 2010–REVISED OCTOBER 2016 www.ti.com Product Folder Links: CSD86350Q5D Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated
8 Device and Documentation Support
8.1 Documentation Support
8.1.1 Related Documentation
For related documentation see the following:
- Power Loss Calculation With Common Source Inductance Consideration for Synchronous Buck Converters (SLPA009)
- Snubber Circuits: Theory, Design and Application (SLUP100)
8.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
8.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
8.4 Trademarks
NexFET, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.
8.5 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
E /c113 c 5 678 1 2 L f K b L e a Top□View Bottom□View Front□View Side□View 1 2 3 4 /c113 d Pinout Position Designation Pin□1 VIN Pin□2 VIN Pin□3 TG Pin□4 TGR Pin□5 BG Pin□6 VSW Pin□7 VSW Pin□8 VSW Pin□9 PGND Exposed Tie□Bar□May□Vary CSD86350Q5D www.ti.com SLPS223F –MAY 2010–REVISED OCTOBER 2016 Product Folder Links: CSD86350Q5D Submit Documentation FeedbackCopyright © 2010–2016, Texas Instruments Incorporated
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
9.1 Q5D Package Dimensions
a 1.40 1.5 0.055 0.059 b 0.360 0.460 0.014 0.018 c 0.150 0.250 0.006 0.010 c1 0.150 0.250 0.006 0.010 d 1.630 1.730 0.064 0.068 d1 0.280 0.380 0.011 0.015 d2 0.200 0.300 0.008 0.012 d3 0.291 0.391 0.012 0.015 D1 4.900 5.100 0.193 0.201 D2 4.269 4.369 0.168 0.172 E 4.900 5.100 0.193 0.201 E1 5.900 6.100 0.232 0.240 E2 3.106 3.206 0.122 0.126 e 1.27 TYP 0.050 TYP f 0.396 0.496 0.016 0.020 L 0.510 0.710 0.020 0.028 θ 0.00 — — — K 0.812 TYP 0.032 TYP
0.341□(0.013) 0.410□(0.016) 0.250□(0.010) 0.300□(0.012) 0.300□(0.012) Stencil□Opening0.300□(0.012) 0.950□(0.037) PCB□Pattern 1.290□(0.051) 0.610□(0.024) 1.680 (0.066) 1.710 (0.067) M0188-01 0.620□(0.024)0.620 (0.024) 0.415□(0.016) 0.345□(0.014) 3.480□(0.137) 0.530□(0.021) 0.400□(0.016) 6.240□(0.246) 1.920 (0.076) 4.460 (0.176) 4.460 (0.176) 1.270 (0.050) CSD86350Q5D SLPS223F –MAY 2010–REVISED OCTOBER 2016 www.ti.com Product Folder Links: CSD86350Q5D Submit Documentation Feedback Copyright © 2010–2016, Texas Instruments Incorporated
9.2 Land Pattern Recommendation
NOTE: Dimensions are in mm (inches).
9.3 Stencil Recommendation
NOTE: Dimensions are in mm (inches). For recommended circuit layout for PCB designs, see Reducing Ringing Through PCB Layout Techniques (SLPA005).
Ø□1.50 +0.10 –0.00 1.75□±0.10 R□0.30 TYPØ□1.50□MIN 0.30□±0.05 R□0.20□MAX A0□=□5.30□±0.10 B0□=□6.50□±0.10 K0□=□1.90□±0.10 M0191-01 2.00□±0.05 8.00□±0.10 5.50□±0.05 12.00□±0.30 CSD86350Q5D www.ti.com SLPS223F –MAY 2010–REVISED OCTOBER 2016 Product Folder Links: CSD86350Q5D Submit Documentation FeedbackCopyright © 2010–2016, Texas Instruments Incorporated
9.4 Q5D Tape and Reel Information
NOTES: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2. 2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm. 3. Material: black static-dissipative polystyrene. 4. All dimensions are in mm, unless otherwise specified. 5. Thickness: 0.30 ±0.05 mm. 6. MSL1 260°C (IR and convection) PbF reflow compatible.
www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) CSD86350Q5D Active Production LSON-CLIP (DQY) | 8 2500 | LARGE T&R ROHS Exempt NIPDAU | SN Level-1-260C-UNLIM -55 to 150 86350D CSD86350Q5D.B Active Production LSON-CLIP (DQY) | 8 2500 | LARGE T&R ROHS Exempt NIPDAU Level-1-260C-UNLIM -55 to 150 86350D CSD86350Q5DG4 Active Production LSON-CLIP (DQY) | 8 2500 | LARGE T&R ROHS Exempt NIPDAU Level-1-260C-UNLIM -55 to 150 86350D CSD86350Q5DG4.B Active Production LSON-CLIP (DQY) | 8 2500 | LARGE T&R ROHS Exempt NIPDAU Level-1-260C-UNLIM -55 to 150 86350D CSD86350Q5DT Active Production LSON-CLIP (DQY) | 8 250 | SMALL T&R ROHS Exempt NIPDAU | SN Level-1-260C-UNLIM -55 to 150 86350D CSD86350Q5DT.B Active Production LSON-CLIP (DQY) | 8 250 | SMALL T&R ROHS Exempt NIPDAU Level-1-260C-UNLIM -55 to 150 86350D (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
www.ti.com 7-Oct-2025 Addendum-Page 2
PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant CSD86350Q5D LSON- CLIP CSD86350Q5DG4 LSON- CLIP CSD86350Q5DT LSON- CLIP Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSD86350Q5D LSON-CLIP DQY 8 2500 346.0 346.0 33.0 CSD86350Q5DG4 LSON-CLIP DQY 8 2500 346.0 346.0 33.0 CSD86350Q5DT LSON-CLIP DQY 8 250 182.0 182.0 20.0 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C 8X 0.46 0.36 4.319 0.1 6X 0.71 0.51 3.81 3.156 0.1 6X 1.27 1.6 1.4 0.05 0.00 0.71 0.51 (0.45) B 6.1 5.9 A 5.1 4.9 (0.2) TYP 4X (0.25) (1) TYP LSON-CLIP - 1.6 mm max heightDQY0008A PLASTIC SMALL OUTLINE - NO LEAD 4218872/B 11/2024 PIN 1 INDEX AREA SEATING PLANE 0.08 C REFER TO NOTE 4 (OPTIONAL) PIN 1 ID
0.1 C A B
0.05 C THERMAL PAD EXPOSED NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. 4. Exposed metals on side wall may vary or not visible SCALE 2.000
www.ti.com EXAMPLE BOARD LAYOUT (0.45) 6X (0.81)
0.05 MIN
0.05 MAX
(0.05) TYP (3.156) 6X (1.27) (5.59) 2X (0.41) (0.81) (4.319) (R0.05) TYP ( 0.2) VIA TYP 6X (0.41) (0.705) TYP (1.205) (1.328) TYP LSON-CLIP - 1.6 mm max heightDQY0008A PLASTIC SMALL OUTLINE - NO LEAD 4218872/B 11/2024 PKG 4 5 PKG LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE:15X METAL UNDER SOLDER MASK SOLDER MASK OPENING NOTES: (continued) 5. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 6. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED (PADS 1 - 2, OPTIONAL FOR OTHER PADS) EXPOSED METAL METAL EDGE SOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED (PREFERRED FOR PADS 3 - 8) EXPOSED METAL
www.ti.com EXAMPLE STENCIL DESIGN (0.45) 6X (0.81) 8X (0.41) 8X (0.81) 6X (1.27) 6X (1.37) (5.59) (R0.05) TYP (0.785) TYP (1.57) TYP (1.41) (1.21) (0.56) (0.15) LSON-CLIP - 1.6 mm max heightDQY0008A PLASTIC SMALL OUTLINE - NO LEAD 4218872/B 11/2024 NOTES: (continued) 7. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 9: 73% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X PKG 4 5 PKG METAL TYP SOLDER MASK EDGE
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