CSD86330Q3DG4

CSD86330Q3D_V01 TI | Alldatasheet

Document overview

• Manufacturer or author: Provided By alldatasheet.com(free datasheet download site)
• PDF pages: 27

Technical content

Output Current (A) Efficiency (%) Power Loss (W) 0 5 10 15 20 50 0 60 1 70 2 80 3 90 4 100 5 G029 VGS = 5V VIN = 12V VOUT = 1.3V fSW = 500kHz LOUT = 1µH TA = 25°C Efficiency Power Loss G1R D /S2 1 S0474-04 ENABLE ENABLE PWM GND BST DRVH LL DRVL CSD86330Q3DDriver IC VDD VI VO VDD Control FET Sync FET PWM P0116-01

3 VSW

4 BG5TGR

(Pin□9) 7VIN 8VIN Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community CSD86330Q3D SLPS264D –OCTOBER 2010–REVISED MAY 2015 CSD86330Q3DSynchronousBuckNexFET™ PowerBlock

1 Features 3 Description

The CSD86330Q3D NexFET™ power block is an 1• Half-Bridge Power Block optimized design for synchronous buck applications• 90% System Efficiency at 15 A offering high current, high efficiency, and high

• Up to 20 A Operation frequency capability in a small 3.3 mm × 3.3 mm outline. Optimized for 5 V gate drive applications, this• High Frequency Operation (Up To 1.5 MHz) product offers a flexible solution capable of offering a• High Density – SON 3.3 mm × 3.3 mm Footprint high density power supply when paired with any 5 V• Optimized for 5 V Gate Drive gate drive from an external controller/driver.
• Low Switching Losses TEXT ADDED FOR SPACING• Ultra Low Inductance Package Top View• RoHS Compliant
• Halogen Free
• Pb-Free Terminal Plating

2 Applications

• Synchronous Buck Converters – High Frequency Applications – High Current, Low Duty Cycle Applications TEXT ADDED FOR SPACING Ordering Information(1)
• Multiphase Synchronous Buck Converters Device Media Qty Package Ship• POL DC-DC Converters 13-InchCSD86330Q3D 2500• IMVP, VRM, and VRD Applications Reel SON 3.3 mm × 3.3 mm Tape and Plastic Package Reel7-InchCSD86330Q3DT 250Reel (1) For all available packages, see the orderable addendum at the end of the data sheet. Added text for spacing Added text for spacing Added text for spacing Added text for spacing RDS(on) vs VGS Gate Charge An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.

SLPS264D –OCTOBER 2010–REVISED MAY 2015 www.ti.com Table of Contents

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision C (October 2011) to Revision D Page Changes from Revision B (September 2011) to Revision C Page Changes from Revision A (December 2010) to Revision B Page Changes from Original (October 2010) to Revision A Page

2 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated

Product Folder Links: CSD86330Q3D

www.ti.com SLPS264D –OCTOBER 2010–REVISED MAY 2015

5 Specifications

5.1 Absolute Maximum Ratings

TA = 25°C (unless otherwise noted)(1) MIN MAX UNIT VIN to PGND –0.8 25 V Voltage range TG to TGR –8 10 V BG to PGND –8 10 V Pulsed Current Rating, IDM 60 A Power Dissipation, PD 6 W Sync FET, ID = 65 A, L = 0.1 mH 211 Avalanche Energy EAS mJ Control FET, ID = 42 A, L = 0.1 mH 88 Operating junction, TJ –55 150 °C Storage temperature, Tstg –55 150 °C (1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. Exposure to absolute- maximum-rated conditions for extended periods may affect device reliability.

5.2 Recommended Operating Conditions

TA = 25° (unless otherwise noted) MIN MAX UNIT Gate drive voltage, VGS 4.5 8 V Input supply voltage, VIN 22 V Switching frequency, fSW CBST = 0.1 µF (min) 200 1500 kHz Operating current 20 A Operating temperature, TJ 125 °C

5.3 Thermal Information

TA = 25°C (unless otherwise stated) THERMAL METRIC MIN TYP MAX UNIT Junction-to-ambient thermal resistance (Min Cu)(1) 135 RθJA Junction-to-ambient thermal resistance (Max Cu)(1)(2) 73 °C/W Junction-to-case thermal resistance (Top of package)(1) 29 RθJC Junction-to-case thermal resistance (PGND Pin)(1) 2.5 design. (2) Device mounted on FR4 material with 1 inch2 (6.45 cm2) Cu.

5.4 Power Block Performance

TA = 25° (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VIN = 12 V, VGS = 5 V, VOUT = 1.3 V, IOUT = 15 A,Power Loss, PLOSS (1) 1.9 WfSW = 500 kHz, LOUT = 1 µH, TJ = 25ºC TG to TGR = 0 VVIN Quiescent Current, IQVIN 10 µABG to PGND = 0 V (1) Measurement made with six 10 µF (TDK C3216X5R1C106KT or equivalent) ceramic capacitors placed across VIN to PGND pins and using a high current 5 V driver IC. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: CSD86330Q3D

86330Q3D□33x33□□MIN□Rev0. . LS HS HD HG LG LD M0206-01 86330Q3D□33x33□□MIN□Rev0. . LS HS CSD86330Q3D SLPS264D –OCTOBER 2010–REVISED MAY 2015 www.ti.com

5.5 Electrical Characteristics

TA = 25°C (unless otherwise stated) Q1 Control FET Q2 Sync FET UNIT PARAMETER TEST CONDITIONS MIN TYP MAX MIN TYP MAX STATIC CHARACTERISTICS BVDSS Drain-to-Source Voltage VGS = 0 V, IDS = 250 µA 25 25 V Drain-to-Source LeakageIDSS VGS = 0 V, VDS = 20 V 1 1 µACurrent Gate-to-Source LeakageIGSS VDS = 0 V, VGS = +10 / –8 100 100 nACurrent VIN = 12 V, VGS = 5 V, VOUT = 1.3 V, IOUT = 15 A,ZDS(on) Effective AC On-Impedance 8.8 3.3 mΩƒSW = 500 kHz, LOUT = 1 µH gƒs Transconductance VDS = 15 V, IDS = 14 A 52 82 S DYNAMIC CHARACTERISTICS CISS Input Capacitance(1) 710 920 1280 1660 pF COSS Output Capacitance(1) VGS = 0 V, VDS = 12.5 V, 350 455 680 880 pF ƒ = 1 MHzReverse TransferCRSS 18 23 38 49 pFCapacitance(1) RG Series Gate Resistance(1) 1.5 3.0 1.2 2.4 Ω Qg Gate Charge Total (4.5 V)(1) 4.8 6.2 9.2 12 nC Qgd Gate Charge - Gate-to-Drain 0.9 1.6 nC VDS = 12.5 V, Gate Charge - Gate-to- IDS = 14 AQgs 1.6 2.1 nCSource Qg(th) Gate Charge at Vth 0.9 1.2 nC QOSS Output Charge VDS = 15.5 V, VGS = 0 V 7.2 13.6 nC td(on) Turn On Delay Time 4.9 5.3 ns tr Rise Time 7.5 6.3 nsVDS = 12.5 V, VGS = 4.5 V, IDS = 14 A, RG = 2 Ωtd(off) Turn Off Delay Time 8.5 15.8 ns tƒ Fall Time 1.9 4.2 ns DIODE CHARACTERISTICS VSD Diode Forward Voltage IDS = 14 A, VGS = 0 V 0.85 1 0.8 1 V Qrr Reverse Recovery Charge 3.9 7.3 nCVdd = 15.5 V, IF = 14 A, di/dt = 300 A/µstrr Reverse Recovery Time 13.9 19 ns (1) Specified by design Max RθJA = 76°C/W Max RθJA = 140°C/W when mounted on when mounted on 1 inch2 (6.45 cm2) of minimum pad area of 2 oz. (0.071 mm thick) 2 oz. (0.071 mm thick) Cu. Cu.

4 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated

Product Folder Links: CSD86330Q3D

5.6 Typical Power Block Device Characteristics

VIN = 12 V, VDD = 5 V, ƒSW = 500 kHz, VOUT = 1.2 V, LOUT = 1.0 µH, IOUT = 20 A, TJ = 125°C, unless stated otherwise. Figure 1. Power Loss vs Output Current Figure 2. Power Loss vs Temperature Figure 3. Safe Operating Area – PCB Vertical Mount(1) Figure 4. Safe Operating Area – PCB Horizontal Mount(1)

VIN = 12 V, VDD = 5 V, ƒSW = 500 kHz, VOUT = 1.2 V, LOUT = 1.0 µH, IOUT = 20 A, TJ = 125°C, unless stated otherwise. Figure 5. Typical Safe Operating Area(1) Figure 6. Normalized Power Loss vs Switching Frequency Figure 7. Normalized Power Loss vs Input Voltage Figure 8. Normalized Power Loss vs Output Voltage Figure 9. Normalized Power Loss vs Output Inductance

6 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated

5.7 Typical Power Block MOSFET Characteristics

TA = 25°C, unless stated otherwise. Figure 10. Control MOSFET Saturation Figure 11. Sync MOSFET Saturation Figure 12. Control MOSFET Transfer Figure 13. Sync MOSFET Transfer Figure 14. Control MOSFET Gate Charge Figure 15. Sync MOSFET Gate Charge

TA = 25°C, unless stated otherwise. Figure 16. Control MOSFET Capacitance Figure 17. Sync MOSFET Capacitance Figure 18. Control MOSFET VGS(th) Figure 19. Sync MOSFET VGS(th) Figure 20. Control MOSFET RDS(on) vs VGS Figure 21. Sync MOSFET RDS(on) vs VGS

8 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated

SLPS264D –OCTOBER 2010–REVISED MAY 2015 www.ti.com

6 Application and Implementation

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

6.1 Application Information

6.1.1 Equivalent System Performance

Many of today’s high performance computing systems require low power consumption in an effort to reduce system operating temperatures and improve overall system efficiency. This has created a major emphasis on improving the conversion efficiency of today’s Synchronous Buck Topology. In particular, there has been an emphasis in improving the performance of the critical Power Semiconductor in the Power Stage of this Application (see Figure 28). As such, optimization of the power semiconductors in these applications, needs to go beyond simply reducing RDS(ON). Figure 28. The CSD86330Q3D is part of TI’s Power Block product family which is a highly optimized product for use in a synchronous buck topology requiring high current, high efficiency, and high frequency. It incorporates TI’s latest generation silicon which has been optimized for switching performance, as well as minimizing losses associated with QGD, QGS, and QRR. Furthermore, TI’s patented packaging technology has minimized losses by nearly eliminating parasitic elements between the Control FET and Sync FET connections (see Figure 29). A key challenge solved by TI’s patented packaging technology is the system level impact of Common Source Inductance (CSI). CSI greatly impedes the switching characteristics of any MOSFET which in turn increases switching losses and reduces system efficiency. As a result, the effects of CSI need to be considered during the MOSFET selection process. In addition, standard MOSFET switching loss equations used to predict system efficiency need to be modified in order to account for the effects of CSI. Further details behind the effects of CSI and modification of switching loss equations are outlined in TI’s Application Note SLPA009.

10 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated

Product Folder Links: CSD86330Q3D

MOSFETs or dual MOSFETs in a standard package. Table 1. Comparison of RDS(ON) vs ZDS(ON) normalized graphs allow engineers to predict the product performance in the actual application.

6.2 Power Loss Curves

MOSFET centric parameters such as RDS(ON) and Qgd are needed to estimate the loss generated by the devices. gate drive loss. Equation 1 is used to generate the power loss curve. under isothermal test conditions.

6.3 Safe Operating Curves (SOA)

3.5”(L) × 0.062”(T) and 6 copper layers of 1 oz. copper thickness.

6.4 Normalized Curves

subtracted from the SOA curve.

12 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated

Figure 32. Typical Application

6.5 Calculating Power Loss and SOA

6.5.1 Design Example

• Output Current = 15 A
• Input Voltage = 12 V
• Output Voltage = 1.2 V
• Switching Frequency = 1000 kHz
• Inductor = 0.4 µH

6.5.2 Calculating Power Loss

• Power Loss at 15 A = 2.2 W (Figure 1)
• Normalized Power Loss for input voltage ≈ 1.0 (Figure 7)
• Normalized Power Loss for output voltage ≈ 0.98 (Figure 8)
• Normalized Power Loss for switching frequency ≈ 1.17 (Figure 6)
• Normalized Power Loss for output inductor ≈ 1.06 (Figure 9)

6.5.3 Calculating SOA Adjustments

• SOA adjustment for input voltage ≈ 0ºC (Figure 7)
• SOA adjustment for output voltage ≈ –0.29ºC (Figure 8)
• SOA adjustment for switching frequency ≈ 4.1ºC (Figure 6)
• SOA adjustment for output inductor ≈ 1.5ºC (Figure 9)
• Final calculated SOA adjustment = 0 + (–0.29) + 4.1 + 1.5 ≈ 5.3ºC In the design example above, the estimated power loss of the CSD86330Q3D would increase to 2.67 W. In addition, the maximum allowable board and/or ambient temperature would have to decrease by 5.3ºC. Figure 33 graphically shows how the SOA curve would be adjusted accordingly. 1. Start by drawing a horizontal line from the application current to the SOA curve. 2. Draw a vertical line from the SOA curve intercept down to the board/ambient temperature. 3. Adjust the SOA board/ambient temperature by subtracting the temperature adjustment value. In the design example, the SOA temperature adjustment yields a reduction in allowable board/ambient temperature of 5.3ºC. In the event the adjustment value is a negative number, subtracting the negative number would yield an increase in allowable board/ambient temperature.

Figure 33. Power Block SOA

14 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated

www.ti.com SLPS264D –OCTOBER 2010–REVISED MAY 2015

7 Recommended PCB Design Overview

There are two key system-level parameters that can be addressed with a proper PCB design: Electrical and Thermal performance. Properly optimizing the PCB layout will yield maximum performance in both areas. A brief description on how to address each parameter is provided.

7.1 Electrical Performance

The Power Block has the ability to switch voltages at rates greater than 10 kV/µs. Special care must be then taken with the PCB layout design and placement of the input capacitors, Driver IC, and output inductor.

• The placement of the input capacitors relative to the Power Block’s VIN and PGND pins should have the highest priority during the component placement routine. It is critical to minimize these node lengths. As such, ceramic input capacitors need to be placed as close as possible to the VIN and PGND pins (see Figure 34). The example in Figure 34 uses 6 × 10 µF ceramic capacitors (TDK part number C3216X5R1C106KT or equivalent). Notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias interconnecting both layers. In terms of priority of placement next to the Power Block, C5, C7, C19, and C8 should follow in order.
• The Driver IC should be placed relatively close to the Power Block Gate pins. TG and BG should connect to the outputs of the Driver IC. The TGR pin serves as the return path of the high-side gate drive circuitry and should be connected to the Phase pin of the IC (sometimes called LX, LL, SW, PH, etc.). The bootstrap capacitor for the Driver IC will also connect to this pin.
• The switching node of the output inductor should be placed relatively close to the Power Block VSW pins. Minimizing the node length between these two components will reduce the PCB conduction losses and actually reduce the switching noise level.
• In the event the switch node waveform exhibits ringing that reaches undesirable levels, the use of a Boost Resistor or RC snubber can be an effective way to reduce the peak ring level. The recommended Boost Resistor value will range between 1 Ω to 4.7 Ω depending on the output characteristics of Driver IC used in conjunction with the Power Block. The RC snubber values can range from 0.5 Ω to 2.2 Ω for the R and 330 pF to 2200 pF for the C. Refer to TI App Note SLUP100 for more details on how to properly tune the RC snubber values. The RC snubber should be placed as close as possible to the Vsw node and PGND see Figure 34 (1)

7.2 Thermal Performance

The Power Block has the ability to utilize the GND planes as the primary thermal path. As such, the use of thermal vias is an effective way to pull away heat from the device and into the system board. Concerns of solder voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount of solder attach that will wick down the via barrel:

• Intentionally space out the vias from each other to avoid a cluster of holes in a given area.
• Use the smallest drill size allowed in your design. The example in Figure 34 uses vias with a 10 mil drill hole and a 16 mil capture pad.
• Tent the opposite side of the via with solder-mask. In the end, the number and drill size of the thermal vias should align with the end user’s PCB design rules and manufacturing capabilities. (1) Keong W. Kam, David Pommerenke, “EMI Analysis Methods for Synchronous Buck Converter EMI Root Cause Analysis”, University of Missouri – Rolla Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 15 Product Folder Links: CSD86330Q3D

Figure 34. Recommended PCB Layout (Top Down)

16 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated

www.ti.com SLPS264D –OCTOBER 2010–REVISED MAY 2015

8 Device and Documentation Support

8.1 Trademarks

NexFET is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.

8.2 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.

8.3 Glossary

SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 17 Product Folder Links: CSD86330Q3D

E /c113 5 678 1 2 L d2 K b L e A Top□View Bottom□View Side□View 1 2 3 4 /c113 d c Exposed□tie□clips□may□vary Pinout Position Designation Pin□1 VIN Pin□2 VIN Pin□3 TG Pin□4 TGR Pin□5 BG Pin□6 VSW Pin□7 VSW Pin□8 VSW Pin□9 PGND CSD86330Q3D SLPS264D –OCTOBER 2010–REVISED MAY 2015 www.ti.com

9 Mechanical, Packaging, and Orderable Information

9.1 Q3D Package Dimensions

A 1.40 1.5 0.055 0.059 b 0.280 0.400 0.011 0.016 c 0.150 0.250 0.006 0.010 c1 0.150 0.250 0.006 0.010 d 0.940 1.040 0.037 0.041 d1 0.160 0.260 0.006 0.010 d2 0.150 0.250 0.006 0.010 d3 0.250 0.350 0.010 0.014 D1 3.200 3.400 0.126 0.134 D2 2.650 2.750 0.104 0.108 E 3.200 3.400 0.126 0.134 E1 3.200 3.400 0.126 0.134 E2 1.750 1.850 0.069 0.073 e 0.650 TYP 0.026 TYP L 0.400 0.500 0.016 0.020 θ 0.00 — — — K 0.300 TYP 0.012 TYP

18 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated

Product Folder Links: CSD86330Q3D

0.300□(0.012) 0.300□(0.012) 0.300 (0.012) M0207-01 0.340 (0.013) 0.333 (0.013) 0.100 0.160□(0.005) 2.290 (0.090) 0.350□(0.014) 0.850□(0.033) 0.990 (0.039) 0.200 (0.008) 0.350□(0.014) 0.210 (0.008) M0193-01 0.440 (0.017) 0.210 (0.008) 1.900□(0.075) 0.300□(0.012) 3.600□(0.142) 2.800 (0.110) 0.650 (0.026) 1.090 (0.043) 2.390 (0.094) CSD86330Q3D www.ti.com SLPS264D –OCTOBER 2010–REVISED MAY 2015

9.2 Land Pattern Recommendation

NOTE: Dimensions are in mm (inches).

9.3 Stencil Recommendation

NOTE: Dimensions are in mm (inches). For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques. Copyright © 2010–2015, Texas Instruments Incorporated Submit Documentation Feedback 19 Product Folder Links: CSD86330Q3D

4.00 ±0.10 (See Note 1) 2.00 ±0.05 3.60 3.60 1.30 1.75 ±0.10 M0144-01 8.00 ±0.10 12.00 +0.30 –0.10 5.50 ±0.05 Ø 1.50 +0.10 –0.00 CSD86330Q3D SLPS264D –OCTOBER 2010–REVISED MAY 2015 www.ti.com

9.4 Q3D Tape and Reel Information

NOTES: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2 2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm 3. Material: black static-dissipative polystyrene 4. All dimensions are in mm, unless otherwise specified. 5. Thickness: 0.30 ±0.0 5 mm 6. MSL1 260°C (IR and convection) PbF reflow compatible Spacer

20 Submit Documentation Feedback Copyright © 2010–2015, Texas Instruments Incorporated

Product Folder Links: CSD86330Q3D

www.ti.com 7-Oct-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) CSD86330Q3D Active Production LSON-CLIP (DQZ) | 8 2500 | LARGE T&R ROHS Exempt NIPDAU | SN Level-1-260C-UNLIM -55 to 150 86330D CSD86330Q3D.B Active Production LSON-CLIP (DQZ) | 8 2500 | LARGE T&R ROHS Exempt NIPDAU Level-1-260C-UNLIM -55 to 150 86330D CSD86330Q3DG4 Active Production LSON-CLIP (DQZ) | 8 2500 | LARGE T&R ROHS Exempt NIPDAU Level-1-260C-UNLIM -55 to 150 86330D CSD86330Q3DG4.B Active Production LSON-CLIP (DQZ) | 8 2500 | LARGE T&R ROHS Exempt NIPDAU Level-1-260C-UNLIM -55 to 150 86330D (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant CSD86330Q3D LSON- CLIP CSD86330Q3DG4 LSON- CLIP Pack Materials-Page 1

PACKAGE MATERIALS INFORMATION www.ti.com 18-Jun-2025 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSD86330Q3D LSON-CLIP DQZ 8 2500 346.0 346.0 33.0 CSD86330Q3DG4 LSON-CLIP DQZ 8 2500 346.0 346.0 33.0 Pack Materials-Page 2

www.ti.com PACKAGE OUTLINE C 8X 0.40 0.28 2.7 0.1 8X 0.5 0.4 1.95 1.8 0.1 6X 0.65 1.55 1.45 0.05 0.00 0.32 0.12 B 3.4 3.2 A 3.4 3.2 (0.2) TYP4X (0.2) 2X (0.98) LSON-CLIP - 1.55 mm max heightDQZ0008A PLASTIC SMALL OUTLINE - NO LEAD 4229809/A 07/2023 PIN 1 INDEX AREA SEATING PLANE 0.08 C 4 5

0.1 C A B

0.05 C EXPOSED THERMAL PAD SYMM SYMM NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. SCALE 3.600

www.ti.com EXAMPLE BOARD LAYOUT

0.07 MIN

0.07 MAX

(1.8) 6X (0.65) (3.05) 2X (0.34) 2X (0.65) (2.7) (R0.05) TYP ( 0.2) VIA TYP (0.22) 4X (0.2) 2X (1.18) 6X (0.65) 6X (0.34) 4X (0.5) 2X (1.1) 2X (0.65) LSON-CLIP - 1.55 mm max heightDQZ0008A PLASTIC SMALL OUTLINE - NO LEAD 4229809/A 07/2023 PKG 4 5 PKG LAND PATTERN EXAMPLE SCALE:20X METAL UNDER SOLDER MASK SOLDER MASK OPENING NOTES: (continued) 4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 5. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown. SOLDER MASK OPENING SOLDER MASK METAL UNDER SOLDER MASK DEFINED METALSOLDER MASK OPENING SOLDER MASK DETAILS NON SOLDER MASK DEFINED

www.ti.com EXAMPLE STENCIL DESIGN 2X (0.34) 2X (0.65) 6X (0.65) (3.05) (R0.05) TYP 6X (0.34)(0.22) 6X (0.65) 2X (1.63) (1.19) (0.695) 2X (1.18) 2X (3.34) LSON-CLIP - 1.55 mm max heightDQZ0008A PLASTIC SMALL OUTLINE - NO LEAD 4229809/A 07/2023 NOTES: (continued) 6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 9 76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE:20X PKG 4 5 PKG METAL TYP 9METAL UNDER SOLDER MASK

IMPORTANT NOTICE AND DISCLAIMER TI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATA SHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, regulatory or other requirements. These resources are subject to change without notice. TI grants you permission to use these resources only for development of an application that uses the TI products described in the resource. Other reproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third party intellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages, costs, losses, and liabilities arising out of your use of these resources. TI’s products are provided subject to TI’s Terms of Sale or other applicable terms available either on ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’s applicable warranties or warranty disclaimers for TI products. TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265 Copyright © 2025, Texas Instruments Incorporated