CSD25481F4 TI1 | Alldatasheet
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D G S 0.60 mm 1.00 mm 0.35 mm CSD25481F4 SLPS420B –SEPTEMBER 2013–REVISED FEBRUARY 2014 CSD25481F4,20VP-ChannelFemtoFET™ MOSFET .1 Features Product Summary 1• Ultra-Low On Resistance VDS Drain-to-Source Voltage –20 V
- Ultra-Low Qg and Qgd Qg Gate Charge Total (–4.5 V) 913 pC
- High Operating Drain Current Qgd Gate Charge Gate to Drain 153 pC VGS = –1.8 V 395 mΩ• Ultra-Small Footprint (0402 Case Size) RDS(on) Drain-to-Source On Resistance VGS = –2.5 V 145 mΩ– 1.0 mm x 0.6 mm VGS = –4.5 V 90 mΩ• Ultra-Low Profile VGS(th) Threshold Voltage –0.95 V – 0.35 mm Max Height
- Integrated ESD Protection Diode Ordering Information – Rated > 4 kV HBM Device Qty Media Package Ship 7-Inch– Rated > 2 kV CDM CSD25481F4 3000 Femto(0402)Reel Tape and1.0 mm x 0.6 mm• Lead and Halogen Free Reel7-Inch Land Grid Array (LGA)CSD25481F4T 250 Reel• RoHS Compliant
2 Applications Absolute Maximum Ratings
TA = 25°C unless otherwise stated VALUE UNIT• Optimized for Load Switch Applications VDS Drain-to-Source Voltage –20 V• Optimized for General Purpose Switching VGS Gate-to-Source Voltage –12 VApplications ID Continuous Drain Current(1) –2.5 A
- Battery Applications IDM Pulsed Drain Current(2) –10 A
- Handheld and Mobile Applications Continuous Gate Clamp Current –35 IG mA Pulsed Gate Clamp Current(2) –350
3 Description PD Power Dissipation(1) 500 mW
This 90 mΩ, 20 V P-Channel FemtoFET™ MOSFET Human Body Model (HBM) 4 kVESD is designed and optimized to minimize the footprint in Rating Charged Device Model (CDM) 2 kV many handheld and mobile applications. This TJ, Operating Junction and –55 to 150 °Ctechnology is capable of replacing standard small TSTG Storage Temperature Range signal MOSFETs while providing at least a 60% (2) Pulse duration ≤ 300 μs, duty cycle ≤ 2%. Top ViewTypical Part Dimensions An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SLPS420B –SEPTEMBER 2013–REVISED FEBRUARY 2014 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
4 Specifications
4.1 Electrical Characteristics
(TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVDSS Drain-to-Source Voltage VGS = 0 V, IDS = –250 μA –20 V IDSS Drain-to-Source Leakage Current VGS = 0 V, VDS = –16 V –100 nA IGSS Gate-to-Source Leakage Current VDS = 0 V, VGS = –12 V –50 nA VGS(th) Gate-to-Source Threshold Voltage VDS = VGS, IDS = –250 μA –0.70 –0.95 –1.20 V VGS = –1.8 V, IDS = –0.1 A 395 800 mΩ VGS = –2.5 V, IDS = –0.5 A 145 174 mΩ RDS(on) Drain-to-Source On Resistance VGS = –4.5 V, IDS = –0.5 A 90 105 mΩ VGS = –8 V, IDS = –0.5 A 75 88 mΩ gfs Transconductance VDS = –10 V, IDS = –0.5 A 3.3 S Dynamic Characteristics Ciss Input Capacitance 189 pF VGS = 0 V, VDS = –10 V,Coss Output Capacitance 78 pFf = 1 MHz Crss Reverse Transfer Capacitance 5.5 pF RG Series Gate Resistance 20 Ω Qg Gate Charge Total (4.5 V) 913 pC Qgd Gate Charge Gate to Drain 153 pC VDS = –10 V, IDS = –0.5 A Qgs Gate Charge Gate to Source 240 pC Qg(th) Gate Charge at Vth 116 pC Qoss Output Charge VDS = –10 V, VGS = 0 V 1030 pC td(on) Turn On Delay Time 4.1 ns tr Rise Time 3.6 nsVDS = 0 V, VGS = –4.5 V, IDS = –0.5 A,RG = 2 Ωtd(off) Turn Off Delay Time 16.9 ns tf Fall Time 6.7 ns Diode Characteristics VSD Diode Forward Voltage ISD = –0.5 A, VGS = 0 V –0.75 V Qrr Reverse Recovery Charge 1010 pC VDS= –10 V, IF = –0.5 A, di/dt = 100 A/μs trr Reverse Recovery Time 7.5 ns
4.2 Thermal Characteristics
(TA = 25°C unless otherwise stated) PARAMETER Typical Values UNIT Junction-to-Ambient Thermal Resistance(1) 85 °C/W RθJA Junction-to-Ambient Thermal Resistance(2) 245 °C/W (1) Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. (2) Device mounted on FR4 material with minimum Cu mounting area.
2 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated
Product Folder Links: CSD25481F4
5 Typical MOSFET Characteristics
Figure 1. Transient Thermal Impedance Figure 2. Saturation Characteristics Figure 3. Transfer Characteristics
Figure 4. Gate Charge Figure 5. Capacitance Figure 6. Threshold Voltage vs Temperature Figure 7. On-State Resistance vs Gate-to-Source Voltage Figure 8. Normalized On-State Resistance vs Temperature Figure 9. Typical Diode Forward Voltage
4 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated
Figure 10. Maximum Safe Operating Area Figure 11. Maximum Drain Current vs Temperature
SLPS420B –SEPTEMBER 2013–REVISED FEBRUARY 2014 www.ti.com
6 Mechanical Data
6.1 0402 Mechanical Dimensions (1) All linear dimensions are in millimeters (dimensions and tolerancing per AME T14.5M-1994). (2) This drawing is subject to change without notice. (3) This package is a PB-free solder land design. Pin Configuration Position Designation Pin 1 Gate Pin 2 Source Pin 3 Drain
6 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated
Product Folder Links: CSD25481F4
www.ti.com SLPS420B –SEPTEMBER 2013–REVISED FEBRUARY 2014
6.2 Recommended Minimum PCB Layout
(1) All dimensions are in millimeters.
6.3 Recommended Stencil Pattern
(1) All dimensions are in millimeters. Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: CSD25481F4
SLPS420B –SEPTEMBER 2013–REVISED FEBRUARY 2014 www.ti.com
6.4 CSD25481F4 Embossed Carrier Tape Dimensions
(1) Pin 1 is oriented in the top-right quadrant of the tape enclosure (quadrant 2), closest to the carrier tape sprocket holes.
8 Submit Documentation Feedback Copyright © 2013–2014, Texas Instruments Incorporated
Product Folder Links: CSD25481F4
www.ti.com SLPS420B –SEPTEMBER 2013–REVISED FEBRUARY 2014
7 Trademarks
FemtoFET is a trademark of Texas Instruments.
8 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (December 2013) to Revision B Page Changes from Original (September 2013) to Revision A Page Copyright © 2013–2014, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: CSD25481F4
www.ti.com 30-Jan-2014 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CSD25481F4 ACTIVE PICOSTAR YJC 3 3000 Green (RoHS & no Sb/Br) Call TI Level-1-250C-UNLIM -40 to 85 CS CSD25481F4R PREVIEW PICOSTAR YJC 3 18000 TBD Call TI Call TI -40 to 85 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
www.ti.com 30-Jan-2014 Addendum-Page 2 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant CSD25481F4 PICOST AR PACKAGE MATERIALS INFORMATION www.ti.com 30-Jan-2014 Pack Materials-Page 1
*All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSD25481F4 PICOSTAR YJC 3 3000 210.0 185.0 35.0 PACKAGE MATERIALS INFORMATION www.ti.com 30-Jan-2014 Pack Materials-Page 2
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