CSD25402Q3A TI | Alldatasheet
Document overview
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Technical content
-VGS - Gate-To-Source Voltage (V) R DS(on) - On-State Resistance (m:) 0 2 4 6 8 10 12 D007 TC = 25° C, ID = -10 A TC = 125° C, ID = -10 A Q g - Gate Charge (nC) -VGS - Gate-to-Source Voltage (V) 0 2 4 6 8 10 12 14 D004 ID = -10 A VDS = -10 V 1 S S S S S G Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community Reference Design CSD25402Q3A SLPS454B –DECEMBER 2013–REVISED JANUARY 2016 CSD25402Q3A–20VP-ChannelNexFET™ PowerMOSFET
1 Features
1• Ultra-Low Qg and Qgd TA = 25°C TYPICAL VALUE UNIT
- Low Thermal Resistance VDS Drain-to-source voltage –20 V
- Low RDS(on) Qg Gate charge total (–4.5 V) 7.5 nC Qgd Gate charge gate to drain 1.1 nC• Pb and Halogen Free VGS = –1.8 V 74 mΩ• RoHS Compliant RDS(on) Drain-to-source on resistance VGS = –2.5 V 13.3 mΩ• SON 3.3 mm × 3.3 mm Plastic Package VGS = –4.5 V 7.7 mΩ Vth Threshold voltage –0.9 V2 Applications
- DC-DC Converters Ordering Information(1)
- Battery Management DEVICE QTY MEDIA PACKAGE SHIP
- Load Switch CSD25402Q3A 2500 13-Inch Reel SON 3.3 mm × 3.3 Tape and mm Plastic Package ReelCSD25402Q3AT 250 7-Inch Reel• Battery Protection (1) For all available packages, see the orderable addendum at 3 Description the end of the data sheet. This –20-V, 7.7-mΩ NexFET™ power MOSFET is Absolute Maximum Ratingsdesigned to minimize losses in power conversion load TA = 25°C VALUE UNITmanagement applications with a SON 3.3 mm × 3.3 mm package that offers an excellent thermal VDS Drain-to-source voltage –20 V performance for the size of the device. VGS Gate-to-source voltage +12 or –12 V Continuous drain current, TC = 25°C –76 A Top View ID Continuous drain current (package limit) –35 A Continuous drain current(1) –15 A IDM Pulsed drain current(2) –148 A Power dissipation(1) 2.8 PD W Power dissipation, TC = 25°C 69 TJ Operating junction temperature –55 to 150 °C Tstg Storage temperature –55 to 150 °C (1) Typical RθJA = 45°C/W on 1 inch2 Cu (2 oz.) on 0.060 inch thick FR4 PCB. (2) Max RθJC = 2.3°C/W, pulse duration ≤100 μs, duty cycle ≤1% RDS(on) vs VGS Gate Charge An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA.
SLPS454B –DECEMBER 2013–REVISED JANUARY 2016 www.ti.com Table of Contents
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version. Changes from Revision A (July 2015) to Revision B Page Changes from Original (December 2013) to Revision A Page
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Product Folder Links: CSD25402Q3A
www.ti.com SLPS454B –DECEMBER 2013–REVISED JANUARY 2016
5 Specifications
5.1 Electrical Characteristics
(TA = 25°C unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CHARACTERISTICS BVDSS Drain-to-source voltage VGS = 0 V, ID = –250 μA –20 V IDSS Drain-to-source leakage current VGS = 0 V, VDS = –16 V –1 μA IGSS Gate-to-source leakage current VDS = 0 V, VGS = ±12 V –100 nA VGS(th) Gate-to-source threshold voltage VDS = VGS, ID = –250 μA –0.65 –0.90 –1.15 V VGS = –1.8 V, ID = –1 A 74 300 mΩ RDS(on) Drain-to-source on resistance VGS = –2.5 V, ID = –10 A 13.3 15.9 mΩ VGS = –4.5 V, ID = –10 A 7.7 8.9 mΩ gfs Transconductance VDS = –10 V, ID = –10 A 59 S DYNAMIC CHARACTERISTICS CISS Input capacitance 1380 1790 pF VGS = 0 V, VDS = –10 V,COSS Output capacitance 763 992 pFƒ = 1 MHz CRSS Reverse transfer capacitance 39 51 pF RG Series gate resistance 3.7 7.4 Ω Qg Gate charge total (–4.5 V) 7.5 9.7 nC Qgd Gate charge gate to drain 1.1 nC VDS = –10 V, ID = –10 A Qgs Gate charge gate to source 2.4 nC Qg(th) Gate charge at Vth 1.0 nC QOSS Output charge VDS = –10 V, VGS = 0 V 7.6 nC td(on) Turn on delay time 10 ns tr Rise time 7 nsVDS = –10 V, VGS = –4.5 V, ID = –10 A , RG = 5 Ωtd(off) Turn off delay time 25 ns tf Fall time 12 ns DIODE CHARACTERISTICS VSD Diode forward voltage IS = –10 A, VGS = 0 V –0.8 –1 V Qrr Reverse recovery charge 10.3 nCVDS = –8.5 V, IF = –10 A, di/dt = 200 A/μstrr Reverse recovery time 21 ns
5.2 Thermal Information
(TA = 25°C unless otherwise stated) THERMAL METRIC MIN TYP MAX UNIT RθJC Junction-to-case thermal resistance(1) 2.3 °C/W RθJA Junction-to-ambient thermal resistance(1)(2) 55 °C/W (2) Device mounted on FR4 material with 1 inch2 (6.45 cm2), 2 oz. (0.071 mm thick) Cu. Copyright © 2013–2016, Texas Instruments Incorporated Submit Documentation Feedback 3 Product Folder Links: CSD25402Q3A
Max RθJA = 175°C/WMax RθJA = 55°C/W when mounted onwhen mounted on minimum pad area of1 inch2 of 2 oz. Cu. 2 oz. Cu.
5.3 Typical MOSFET Characteristics
Figure 1. Transient Thermal Impedance
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Figure 8. Normalized On-State Resistance vs Temperature Figure 9. Typical Diode Forward Voltage Figure 10. Maximum Safe Operating Area Figure 11. Maximum Drain Current vs Temperature
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6 Device and Documentation Support
6.1 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
6.2 Trademarks
NexFET, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.
6.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
6.4 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions. Copyright © 2013–2016, Texas Instruments Incorporated Submit Documentation Feedback 7 Product Folder Links: CSD25402Q3A
C TYP 3.5 3.1 2X 0.15 MAX
0.9 MAX
0.05 0.00 (0.2) 1.74±0.1 2.45±0.1 0.565±0.1 4X 0.52 0.32 4X 0.55 0.25
0.65 TYP
2X 1.95 8X 0.35 0.25 (0.15) TYP 2X (0.2) 4X 1.45 B 3.1 2.9 A 3.25 3.05 4222499/A 12/2015 PIN 1 INDEX AREA SEATING PLANE
0.1 C B A
0.05 C2X
SLPS454B –DECEMBER 2013–REVISED JANUARY 2016 www.ti.com
7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Q3A Package Dimensions
- All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. 4. Metalized features are supplier options and may not be on the package. 5. All dimensions do not include mold flash or protrusions.
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(3.1) 4X 0.705 4X 1.125 (R ) TYP 0.05 8X (0.6) 8X (0.3) 6X (0.65) (0.208) (0.905) (0.663) (1.325) SYMM SOLDER MASK EDGE PKG 4 5 METAL TYP 4X (0.6) 4X (0.3) (1.775) (2.45)
0.05 MIN
(0.207) (0.975) TYP (R ) TYP 0.05 (0.245) (0.905) TYP (R ) TYP 0.05 (1.55) (0.56) (0.635) TYP ( ) VIA TYP 0.2 4X (0.3) LAND PATTERN EXAMPLE SYMM SOLDER MASK OPENING METAL UNDER SOLDER MASK 4 5 PKG CSD25402Q3A www.ti.com SLPS454B –DECEMBER 2013–REVISED JANUARY 2016
7.2 Q3A Recommended PCB Pattern
- This package is designed to be soldered to a thermal pad on the board. For more information, see QFN/SON PCB Attachment application report, SLUA271. 2. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown. text added for spacing For recommended circuit layout for PCB designs, see application note SLPA005 – Reducing Ringing Through PCB Layout Techniques.
7.3 Q3A Recommended Stencil Pattern
- Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. Copyright © 2013–2016, Texas Instruments Incorporated Submit Documentation Feedback 9 Product Folder Links: CSD25402Q3A
4.00 ±0.10 (See Note 1) 2.00 ±0.05 3.60 3.60 1.30 1.75 ±0.10 M0144-01 8.00 ±0.10 12.00 +0.30 –0.10 5.50 ±0.05 Ø 1.50 +0.10 –0.00 CSD25402Q3A SLPS454B –DECEMBER 2013–REVISED JANUARY 2016 www.ti.com
7.4 Q3A Tape and Reel Information
Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2 2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm 3. Material: black static-dissipative polystyrene 4. All dimensions are in mm, unless otherwise specified 5. Thickness: 0.30 ±0.05 mm 6. MSL1 260°C (IR and convection) PbF reflow compatible
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Product Folder Links: CSD25402Q3A
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) CSD25402Q3A Active Production VSONP (DNH) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -55 to 150 25402 CSD25402Q3A.B Active Production VSONP (DNH) | 8 2500 | LARGE T&R Yes SN Level-1-260C-UNLIM -55 to 150 25402 CSD25402Q3AT Active Production VSONP (DNH) | 8 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -55 to 150 25402 CSD25402Q3AT.B Active Production VSONP (DNH) | 8 250 | SMALL T&R Yes SN Level-1-260C-UNLIM -55 to 150 25402 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jan-2023 TAPE AND REEL INFORMATION Reel Width (W1) REEL DIMENSIONS A0B0K0WDimension designed to accommodate the component lengthDimension designed to accommodate the component thicknessOverall width of the carrier tapePitch between successive cavity centersDimension designed to accommodate the component width TAPE DIMENSIONSK0 P1B0WA0Cavity QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE Pocket QuadrantsSprocket HolesQ1Q1Q2Q2Q3Q3Q4Q4User Direction of Feed P1ReelDiameter *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Reel Diameter (mm) Reel Width W1 (mm) (mm) (mm) (mm) (mm) W (mm) Pin1 Quadrant Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jan-2023 TAPE AND REEL BOX DIMENSIONS Width (mm) W LH *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CSD25402Q3A VSONP DNH 8 2500 340.0 340.0 38.0 CSD25402Q3AT VSONP DNH 8 250 190.0 190.0 30.0 Pack Materials-Page 2
www.ti.com PACKAGE OUTLINE C 3.5
3.1 TYP
2X 0.15 MAX 0.05 0.00 (0.2) 1.74 0.1 2.45 0.1 0.565 0.1 4X 0.52 0.32 4X 0.55 0.25 2X 1.95 8X 0.35 0.25 (0.15) TYP 2X (0.2) 4X 1.45 3.5 3.1 NOTE 6 B 3.1 2.9 NOTE 5 A 3.25 3.05 NOTE 5 (0.685) VSONP - 0.9 mm max heightDNH0008A PLASTIC SMALL OUTLINE - NO LEAD 4222499/C 02/2025 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance. 4. Metalized features are supplier options and may not be on the package. 5. These dimensions do not include mold flash protrusions or gate burrs. 6. These dimensions include interterminal flash or protrusion. Interterminal flash or protrusion shall not exceed 0.25 mm per side. PIN 1 INDEX AREA SEATING PLANE SCALE 4.400
www.ti.com EXAMPLE BOARD LAYOUT 4X (0.6) 4X (0.3) (1.775) (2.45) (0.207) (0.975) TYP (R0.05) TYP (0.245) (0.905) TYP (R0.05) TYP (1.55) (0.56) (0.635) TYP ( 0.2) VIA TYP 4X (0.3) VSONP - 0.9 mm max heightDNH0008A PLASTIC SMALL OUTLINE - NO LEAD 4222499/C 02/2025 NOTES: (continued) 7. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature number SLUA271 (www.ti.com/lit/slua271). 8. Vias are optional depending on application, refer to device data sheet. If some or all are implemented, recommended via locations are shown. LAND PATTERN EXAMPLE SOLDER MASK DEFINED SCALE: 25X SYMM SOLDER MASK OPENING METAL UNDER SOLDER MASK 4 5 PKG
www.ti.com EXAMPLE STENCIL DESIGN (3.1) 4X 0.705 4X 1.125 (R0.05) TYP 8X (0.6) 8X (0.3) 6X (0.65) (0.208) (0.905) (0.663) (1.325) VSONP - 0.9 mm max heightDNH0008A PLASTIC SMALL OUTLINE - NO LEAD 4222499/C 02/2025 NOTES: (continued) 9. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL EXPOSED PAD 9: 76% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE SCALE: 25X SYMM SOLDER MASK EDGE PKG 4 5 METAL TYP
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