CSD23201W10

CSD23201W10_16 TI1 | Alldatasheet

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−VGS − Gate to Source Voltage − V 100 120 140 160 180 200 0 1 2 3 4 5 6 R DS(on) − On-State Resistance − mW G006 ID = −0.5A TC = 125°C TC = 25°C Q g − Gate Charge − nC 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 −VG − Gate Voltage − V G003 ID = −0.5A VDS = −6V CSD23201W10 www.ti.com SLPS209A –AUGUST 2009–REVISED MAY 2010 P-ChannelNexFET™ PowerMOSFET Check forSamples: CSD23201W10 1FEATURES PRODUCT SUMMARY• UltraLow Qg and Qgd VDS DraintoSourceVoltage –12 V

• Small Footprint1mm × 1mm Q g Gate Charge Total(4.5V) 1.8 nC
• Low Profile0.62mm Height Q gd Gate Charge Gate toDrain 0.26 nC
• Pb Free VGS = –1.5V 110 m Ω R DS(on) DraintoSourceOn Resistance VGS = –2.5V 77 m Ω• Gate ESD Protection– 3kV VGS = –4.5V 66 m Ω• RoHS Compliant VGS(th) ThresholdVoltage –0.6 V• Halogen Free ORDERING INFORMATIONAPPLICATIONS Device Package Media Qty Ship• BatteryManagement 1 × 1 Wafer Level Tape andCSD23201W10 7-inchreel 3000• Load Switch Package Reel
• BatteryProtection ABSOLUTE MAXIMUM RATINGS DESCRIPTION TA = 25°C unlessotherwisestated VALUE UNIT VDS DraintoSourceVoltage –12 VThe devicehas been designedto deliverthe lowest VGS Gate toSourceVoltage –6 Von resistanceand gatechargeinthesmallestoutline ID ContinuousDrainCurrent,TC = 25°C (1) –2.2 Apossiblewithexcellentthermalcharacteristicsin an ultralowprofile. IDM PulsedDrainCurrent,TA = 25°C (2) –8.8 A ContinuousGate Clamp Current –0.5 A IGTop View PulsedGate Clamp Current –7 A PD Power Dissipation(1) 1 W TJ, OperatingJunctionand Storage –55 to150 °CTSTG TemperatureRange (1) R qJA = 100°C/W on 1in2 Cu (2oz.)on 0.060"thickFR4 PCB. (2) Pulsewidth≤300ms,dutycycle≤2% R DS(ON) vs VGS Gate Charge Pleasebe aware thatan importantnoticeconcerningavailability,standardwarranty,and use incriticalapplicationsofTexas Instrumentssemiconductorproductsand disclaimerstheretoappearsattheend ofthisdatasheet. PRODUCTION DATA informationiscurrentas ofpublicationdate. Copyright© 2009–2010,Texas InstrumentsIncorporatedProductsconform to specificationsper the terms of the Texas Instrumentsstandardwarranty.Productionprocessingdoes not necessarilyincludetestingofallparameters.

SLPS209A –AUGUST 2009–REVISED MAY 2010 www.ti.com These deviceshave limitedbuilt-inESD protection.The leadsshouldbe shortedtogetherorthedeviceplacedinconductivefoam duringstorageorhandlingtopreventelectrostaticdamage totheMOS gates.

ELECTRICAL CHARACTERISTICS

(TA = 25°C unlessotherwisestated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT StaticCharacteristics BV DSS DraintoSourceVoltage VGS = 0V,ID = –250mA –12 V BV GSS Gate toSourceVoltage; VDS = 0V,IG = –250mA –6.1 –7.2 V IDSS DraintoSourceLeakage Current VGS = 0V,VDS = –9.6V –1 mA IGSS Gate toSourceLeakage Current VDS = 0V,VGS = –6V –100 nA VGS(th) Gate toSourceThresholdVoltage VDS = VGS ,ID = –250mA –0.4 –0.6 –1.0 V VGS = –1.5V,ID = –0.5A 110 138 m Ω R DS(on) DraintoSourceOn Resistance VGS = –2.5V,ID = –0.5A 77 96 m Ω VGS = –4.5V,ID = –0.5A 66 82 m Ω gfs Transconductance VDS = –6.0V,ID = –0.5A 9 S Dynamic Characteristics C ISS InputCapacitance 250 325 pF C OSS OutputCapacitance VGS = 0V,VDS = –6.0V,f= 1MHz 125 155 pF C RSS ReverseTransferCapacitance 32 42 pF Q g Gate Charge Total(–4.5V) 1.8 2.4 nC Q gd Gate Charge Gate toDrain 0.26 nC VDS = –6.0V,ID = –0.5A Q gs Gate Charge Gate toSource 0.28 nC Q g(th) Gate Charge atVth 0.11 nC Q OSS OutputCharge VDS = –6.0V,VGS = 0V 1.7 nC td(on) TurnOn DelayTime 24 ns tr RiseTime 19 nsVDS = –6.0V,VGS = –2.5V,ID = –0.5A R G = 20Ωtd(off) TurnOffDelayTime 68 ns tf FallTime 29 ns Diode Characteristics VSD DiodeForwardVoltage IS = –0.5A,VGS = 0V –0.77 –1.0 V Q rr ReverseRecoveryCharge Vdd= –4.0V,IF = –0.5A,di/dt= 100A/ms 2 nC trr ReverseRecoveryTime Vdd= –4.0V,IF = –0.5A,di/dt= 100A/ms 9.5 ns THERMAL CHARACTERISTICS (TA = 25°C unlessotherwisestated) PARAMETER MIN TYP MAX UNIT R qJC ThermalResistanceJunctiontoAmbient(Minimum Cu area) 245 °C/W R qJA ThermalResistanceJunctiontoAmbient(1in2 Cu area) 125 °C/W

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P-Chan 1.0x1.0 CSP TTA MAX Rev1 M0150-01 P-Chan 1.0x1.0 CSP TTA MIN Rev1 tp – Pulse□Duration–s Z /c113JA – NormalizedThermal□Impedance G012 0.0001 0.01 0.1 0.001 0.1 0.05 0.01 0.02 0.5 0.3 Single□Pulse Duty□Cycle□=□t /t1 2 R/c113 /c113 /c113 JA J JA JA =□195 C/W□(min□Cu) T =□P x□Z x□R /c176 P CSD23201W10 www.ti.com SLPS209A –AUGUST 2009–REVISED MAY 2010 Max R qJA = 245°C/WMax R qJA = 125°C/W when mounted onwhen mounted on minimum pad areaof21inch2 of2 oz.Cu. oz.Cu. TYPICAL MOSFET CHARACTERISTICS (TA = 25°C unlessotherwisestated) Figure1. TransientThermal Impedance Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 3 ProductFolderLink(s):CSD23201W10

−VDS − Drain to Source Voltage − V −ID − Drain Current − A G001 VGS = −1.2VVGS = −2.5V VGS = −4.5V VGS = −3V VGS = −1.5V −VGS − Gate to Source Voltage − V −ID − Drain Current − A G002 VDS = −5V TC = −55°C TC = 25°C TC = 125°C Q g − Gate Charge − nC 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 −VG − Gate Voltage − V G003 ID = −0.5A VDS = −6V −VDS − Drain to Source Voltage − V 100 150 200 250 300 0 2 4 6 8 10 12 C − Capacitance − pF G004 f = 1MHz, VGS = 0V C RSS = CGD C OSS = CDS + CGD C ISS = CGD + CGS TC − Case Temperature − °C 0.0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 −75 −25 25 75 125 175 −VGS(th) − Threshold Voltage − V G005 ID = −250mA −VGS − Gate to Source Voltage − V 100 120 140 160 180 200 0 1 2 3 4 5 6 R DS(on) − On-State Resistance − mW G006 ID = −0.5A TC = 125°C TC = 25°C CSD23201W10 SLPS209A –AUGUST 2009–REVISED MAY 2010 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unlessotherwisestated) Figure2.SaturationCharacteristics Figure3.TransferCharacteristics Figure4.Gate Charge Figure5.Capacitance Figure6.ThresholdVoltagevs.Temperature Figure7.On Resistancevs.Gate Voltage

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TC − Case Temperature − °C 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 −75 −25 25 75 125 175 Normalized On-State Resistance G007 ID = −0.5A VGS = −4.5V −VSD − Source to Drain Voltage − V −ISD − Source to Drain Current − A G008 0.1 0.001 0.0001 0.01 TC = 25°C TC = 125°C TC − Case Temperature − C/c176 0.0 0.5 1.0 1.5 2.0 −50 −25 0 25 50 75 100 125 150 175 D − Drain□Current − A G011 2.5 3.0 −V DS − Drain To□Source□Voltage − V G009 100 0.01 D − Drain□Current − A 0.1 0.1 10 1001 10ms 100 s/c109 DCSingle□Pulse Rθ JA =□195 C/W□(min□Cu)/c176 Area□Limited by□RDS(on) 100ms CSD23201W10 www.ti.com SLPS209A –AUGUST 2009–REVISED MAY 2010 TYPICAL MOSFET CHARACTERISTICS (continued) (TA = 25°C unlessotherwisestated) Figure8.On Resistancevs.Temperature Figure9.TypicalDiode Forward Voltage Figure10.Maximum Safe OperatingArea Figure11. Maximum DrainCurrentvs.Temperature Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 5 ProductFolderLink(s):CSD23201W10

Side□View 0.62□Max Pin□1 Mark A B Bottom□View Seating□Plate 0.50 0.50 A B 0.04 0.62□Max 0.38 Solder□Ball ±0.075Ø□0.311 12 2 Top□View Front□View 1.00 +0.00 –0.10 1.00 +0.00 –0.10 CSD23201W10 SLPS209A –AUGUST 2009–REVISED MAY 2010 www.ti.com MECHANICAL DATA NOTE: Alldimensionsareinmm (unlessotherwisespecified) Pin ConfigurationTable POSITION DESIGNATION B1 Source A1 Gate A2,B2 Drain

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0.50 0.50 A 1 2 B Ø 0.25 1.75□±0.10 Ø□0.50□±0.05 M0153-01 8.00 +0.30 –0.10 4.00□±0.10 4.00□±0.10 3.50□±0.05 5°□Max 0.78□±0.05 5°□Max 1.18□±0.05 1.18□±0.05 0.254□±0.02 CSD23201W10 www.ti.com SLPS209A –AUGUST 2009–REVISED MAY 2010 Land PatternRecommendation NOTE: Alldimensionsareinmm (unlessotherwisespecified) Tape and Reel Information NOTE: Alldimensionsareinmm (unlessotherwisespecified)

REVISION HISTORY

Changes from Original(August 2009)toRevisionA Page Copyright© 2009–2010,Texas InstrumentsIncorporated SubmitDocumentationFeedback 7 ProductFolderLink(s):CSD23201W10

www.ti.com 7-Jan-2016 Addendum-Page 1 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Qty Eco Plan (2) Lead/Ball Finish (6) MSL Peak Temp (3) Op Temp (°C) Device Marking (4/5) Samples CSD23201W10 OBSOLETE DSBGA YZB 4 TBD Call TI Call TI -55 to 150 HPA00788W10 OBSOLETE DSBGA YZB 4 TBD Call TI Call TI -55 to 150 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

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