CSD16327Q3 TI | Alldatasheet
Document overview
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Technical content
VGS - Gate-to-Source Voltage (V) R DS(on) - On-State Resistance (m:) 0 1 2 3 4 5 6 7 8 9 10 D007 TC = 25qC, ID = 24 A TC = 125qC, ID = 24 A Q g - Gate Charge (nC) VGS - Gate-to-Source Voltage (V) 0 2 4 6 8 10 12 D004 ID = 24 A VDS = 12.5 V 1 D 2 D 3 D D D5G P0095-01 Product Folder Sample & Buy T echnical Documents Tools & Software Support & Community An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. PRODUCTION DATA. CSD16327Q3 SLPS371A –DECEMBER 2011–REVISED SEPTEMBER 2016 CSD16327Q325-VN-ChannelNexFET™ PowerMOSFET
1 Features
1• Optimized for 5-V Gate Drive
- Ultra-Low Qg and Qgd
- Low Thermal Resistance
- Avalanche Rated
- Lead-Free Terminal Plating
- RoHS Compliant
- Halogen Free
- SON 3.3-mm × 3.3-mm Plastic Package
2 Applications
- Point-of-Load Synchronous Buck Converter for Applications in Networking, Telecom and Computing Systems
- Optimized for Control or Synchronous FET
Applications
3 Description
This 25-V, 3.4-mΩ, SON 3.3-mm × 3.3-mm NexFET™ power MOSFET has been designed to minimize losses in power conversion and optimized for 5-V gate drive applications. Top View Product Summary TA = 25°C TYPICAL VALUE UNIT VDS Drain-to-Source Voltage 25 V Qg Gate Charge Total (4.5 V) 6.2 nC Qgd Gate Charge Gate-to-Drain 1.1 nC RDS(on) Drain-to-Source On-Resistance VGS = 3 V 5 mΩVGS = 4.5 V 4 VGS = 8 V 3.4 VGS(th) Threshold Voltage 1.2 V Device Information(1) DEVICE MEDIA QTY PACKAGE SHIP CSD16327Q3 13-Inch Reel 2500 SON 3.30-mm × 3.30-mm Plastic Package Tape and ReelCSD16327Q3T 7-Inch Reel 250 (1) For all available packages, see the orderable addendum at the end of the data sheet. Absolute Maximum Ratings TA = 25°C VALUE UNIT VDS Drain-to-Source Voltage 25 V VGS Gate-to-Source Voltage +10 / –8 V ID Continuous Drain Current (Package Limited) 60 AContinuous Drain Current (Silicon Limited), TC = 25°C 112 Continuous Drain Current(1) 22 IDM Pulsed Drain Current(2) 240 A PD Power Dissipation(1) 2.8 W Power Dissipation, TC = 25°C 74 TJ, Tstg Operating Junction Temperature, Storage Temperature –55 to 150 °C EAS Avalanche Energy, Single Pulse ID = 50 A, L = 0.1 mH, RG = 25 Ω 125 mJ (1) Typical RθJA = 45°C/W on 1-in2 Cu (2 oz) on 0.06-in thick FR4 PCB. (2) Max RθJC = 1.7°C/W pulse width ≤100 μs, duty cycle ≤1%. RDS(on) vs VGS Gate Charge
SLPS371A –DECEMBER 2011–REVISED SEPTEMBER 2016 www.ti.com Product Folder Links: CSD16327Q3 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated Table of Contents
7 Mechanical, Packaging, and Orderable
4 Revision History
Changes from Original (December 2011) to Revision A Page
www.ti.com SLPS371A –DECEMBER 2011–REVISED SEPTEMBER 2016 Product Folder Links: CSD16327Q3 Submit Documentation FeedbackCopyright © 2011–2016, Texas Instruments Incorporated
5 Specifications
5.1 Electrical Characteristics
TA = 25°C (unless otherwise stated) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT STATIC CHARACTERISTICS BVDSS Drain-to-source voltage VGS = 0 V, ID = 250 μA 25 V IDSS Drain-to-source leakage current VGS = 0 V, VDS = 20 V 1 μA IGSS Gate-to-source leakage current VDS = 0 V, VGS = +10 / –8 V 100 nA VGS(th) Gate-to-source threshold voltage VDS = VGS, ID = 250 μA 0.9 1.2 1.4 V RDS(on) Drain-to-source on-resistance VGS = 3 V, ID = 24 A 5 6.5 mΩVGS = 4.5 V, ID = 24 A 4 4.8 VGS = 8 V, ID = 24 A 3.4 4.0 gfs Transconductance VDS = 12.5 V, ID = 24 A 96 S DYNAMIC CHARACTERISTICS CISS Input capacitance VGS = 0 V, VDS = 12.5 V, f = 1 MHz 1020 1300 pF COSS Output capacitance 740 960 pF CRSS Reverse transfer capacitance 50 65 pF Rg Series gate resistance 1.4 2.8 Ω Qg Gate charge total (4.5 V) VDS = 12.5 V, ID = 24 A 6.2 8.4 nC Qgd Gate charge gate-to-drain 1.1 nC Qgs Gate charge gate-to-source 1.8 nC Qg(th) Gate charge at Vth 1 nC QOSS Output charge VDS = 12.5 V, VGS = 0 V 14 nC td(on) Turnon delay time VDS = 12.5 V, VGS = 4.5 V ID = 24 A RG = 2 Ω 5.3 ns tr Rise time 15 ns td(off) Turnoff delay time 13 ns tf Fall time 6.3 ns DIODE CHARACTERISTICS VSD Diode forward voltage IS = 24 A, VGS = 0 V 0.85 1 V Qrr Reverse recovery charge VDD = 12.5 V, IF = 24 A, di/dt = 300 A/μs 21 nC trr Reverse recovery time VDD = 12.5 V, IF = 24 A, di/dt = 300 A/μs 16 ns cm), 0.06-in (1.52-mm) thick FR4 PCB. RθJC is specified by design, whereas RθJA is determined by the user’s board design. (2) Device mounted on FR4 material with 1-in2 (6.45-cm2), 2-oz (0.071-mm) thick Cu.
5.2 Thermal Information
TA = 25°C (unless otherwise stated) THERMAL METRIC MIN TYP MAX UNIT RθJC Junction-to-case thermal resistance(1) 1.7 °C/W RθJA Junction-to-ambient thermal resistance(1)(2) 55 °C/W
5.3 Typical MOSFET Characteristics
Figure 1. Transient Thermal Impedance
www.ti.com SLPS371A –DECEMBER 2011–REVISED SEPTEMBER 2016 Product Folder Links: CSD16327Q3 Submit Documentation FeedbackCopyright © 2011–2016, Texas Instruments Incorporated
6 Device and Documentation Support
6.1 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper right corner, click on Alert me to register and receive a weekly digest of any product information that has changed. For change details, review the revision history included in any revised document.
6.2 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of Use. TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help solve problems with fellow engineers. Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and contact information for technical support.
6.3 Trademarks
NexFET, E2E are trademarks of Texas Instruments. All other trademarks are the property of their respective owners.
6.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
6.5 Glossary
SLYZ022 — TI Glossary. This glossary lists and explains terms, acronyms, and definitions.
SLPS371A –DECEMBER 2011–REVISED SEPTEMBER 2016 www.ti.com Product Folder Links: CSD16327Q3 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated
7 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most current data available for the designated devices. This data is subject to change without notice and revision of this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
7.1 Q3 Package Dimensions
b1 0.310 NOM 0.012 NOM e 0.650 TYP 0.026 TYP K 0.650 TYP 0.026 TYP L1 0 — 0 0 — 0 θ 0 — 0 0 — 0
www.ti.com SLPS371A –DECEMBER 2011–REVISED SEPTEMBER 2016 Product Folder Links: CSD16327Q3 Submit Documentation FeedbackCopyright © 2011–2016, Texas Instruments Incorporated
7.2 Recommended PCB Pattern
For recommended circuit layout for PCB designs, see Reducing Ringing Through PCB Layout Techniques (SLPA005).
7.3 Recommended Stencil Opening
All dimensions are in mm, unless otherwise specified.
4.00 ±0.10 (See Note 1) 2.00 ±0.05 3.60 3.60 1.30 1.75 ±0.10 M0144-01 8.00 ±0.10 12.00 +0.30 –0.10 5.50 ±0.05 Ø 1.50 +0.10 –0.00 CSD16327Q3 SLPS371A –DECEMBER 2011–REVISED SEPTEMBER 2016 www.ti.com Product Folder Links: CSD16327Q3 Submit Documentation Feedback Copyright © 2011–2016, Texas Instruments Incorporated
7.4 Q3 Tape and Reel Information
Notes: 1. 10-sprocket hole pitch cumulative tolerance ±0.2. 2. Camber not to exceed 1 mm in 100 mm, noncumulative over 250 mm. 3. Material: black static dissipative polystyrene. 4. All dimensions are in mm (unless otherwise specified). 5. Thickness: 0.30 ±0.05 mm. 6. MSL1 260°C (IR and Convection) PbF-Reflow Compatible.
www.ti.com 23-May-2025 PACKAGING INFORMATION Orderable part number Status (1) Material type (2) Package | Pins Package qty | Carrier RoHS (3) Lead finish/ Ball material (4) MSL rating/ Peak reflow (5) Op temp (°C) Part marking (6) CSD16327Q3 Active Production VSON-CLIP (DQG) | 8 2500 | LARGE T&R ROHS Exempt SN Level-1-260C-UNLIM -55 to 150 CSD16327 CSD16327Q3.B Active Production VSON-CLIP (DQG) | 8 2500 | LARGE T&R ROHS Exempt SN Level-1-260C-UNLIM -55 to 150 CSD16327 CSD16327Q3T Active Production VSON-CLIP (DQG) | 8 250 | SMALL T&R ROHS Exempt SN Level-1-260C-UNLIM -55 to 150 CSD16327 CSD16327Q3T.B Active Production VSON-CLIP (DQG) | 8 250 | SMALL T&R ROHS Exempt SN Level-1-260C-UNLIM -55 to 150 CSD16327 (1) Status: For more details on status, see our product life cycle. (2) Material type: When designated, preproduction parts are prototypes/experimental devices, and are not yet approved or released for full production. Testing and final process, including without limitation quality assurance, reliability performance testing, and/or process qualification, may not yet be complete, and this item is subject to further changes or possible discontinuation. If available for ordering, purchases will be subject to an additional waiver at checkout, and are intended for early internal evaluation purposes only. These items are sold without warranties of any kind. (3) RoHS values: Yes, No, RoHS Exempt. See the TI RoHS Statement for additional information and value definition. (4) Lead finish/Ball material: Parts may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two lines if the finish value exceeds the maximum column width. (5) MSL rating/Peak reflow: The moisture sensitivity level ratings and peak solder (reflow) temperatures. In the event that a part has multiple moisture sensitivity ratings, only the lowest level per JEDEC standards is shown. Refer to the shipping label for the actual reflow temperature that will be used to mount the part to the printed circuit board. (6) Part marking: There may be an additional marking, which relates to the logo, the lot trace code information, or the environmental category of the part. Multiple part markings will be inside parentheses. Only one part marking contained in parentheses and separated by a "~" will appear on a part. If a line is indented then it is a continuation of the previous line and the two combined represent the entire part marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1
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