CSC2822P

NCP160 ONSEMI | Alldatasheet

Document overview

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• PDF pages: 20

Technical content

Features

• Operating Input V oltage Range: 1.9 V to 5.5 V
• Available in Fixed V oltage Option: 1.8 V to 5.14 V
• ±2% Accuracy Over Load/Temperature
• Ultra Low Quiescent Current Typ. 18 /C0109A
• Standby Current: Typ. 0.1 /C0109A
• Very Low Dropout: 80 mV at 250 mA
• Ultra High PSRR: Typ. 98 dB at 20 mA, f = 1 kHz
• Ultra Low Noise: 10 /C0109VRMS
• Stable with a 1 /C0109F Small Case Size Ceramic Capacitors
• Available in −WLCSP4 0.65 mm x 0.65 mm x 0.4 mm CASE 567KA −WLCSP4 0.65 mm x 0.65 mm x 0.33 mm CASE 567JZ −XDFN4 1 mm x 1 mm x 0.4 mm
• These Devices are Pb−Free, Halogen Free/BFR Free and are RoHS Compliant Typical Applications
• Battery−powered Equipment
• Wireless LAN Devices
• Smartphones, Tablets
• Cameras, DVRs, STB and Camcorders IN EN GND OUT OFF ON

Figure 1. Typical Application Schematics

ORDERING INFORMATION

(Top View) (Top View) WLCSP4 CASE 567JZ A1 X

1 XX M

Figure 2. Simplified Schematic Block Diagram A2 1 OUT Regulated output voltage. The output should be bypassed with small 1 /C0109F ceramic capacitor. B1 3 EN Chip enable: Applying VEN < 0.4 V disables the regulator, Pulling VEN > 1.2 V enables the LDO. should not be assumed, damage may occur and reliability may be affected.

1. Refer to ELECTRICAL CHARACTERISTIS and APPLICATION INFORMATION for Safe Operating Area.
2. This device series incorporates ESD protection and is tested by the following methods:

Latchup Current Maximum Rating tested per JEDEC standard: JESD78.

1. Measured according to JEDEC board specification. Detailed description of the board can be found in JESD51−7

www.onsemi.com ELECTRICAL CHARACTERISTICS −40°C ≤ TJ ≤ 125°C; VIN = VOUT(NOM) + 1 V; IOUT = 1 mA, CIN = COUT = 1 /C0109F, unless otherwise noted. VEN = 1.2 V. Typical values are at TJ = +25°C (Note 4). Parameter Test Conditions Symbol Min Typ Max Unit Operating Input Voltage VIN 1.9 5.5 V Output Voltage Accuracy VIN = VOUT(NOM) + 1 V 0 mA ≤ IOUT ≤ 250 mA VOUT −2 +2 % Line Regulation VOUT(NOM) + 1 V ≤ VIN ≤ 5.5 V LineReg 0.02 %/V Load Regulation IOUT = 1 mA to 250 mA LoadReg 0.001 %/mA Dropout Voltage (Note 5) IOUT = 250 mA VOUT(NOM) = 1.8 V VDO 180 250 mV VOUT(NOM) = 2.5 V 110 175 VOUT(NOM) = 2.8 V 95 160 VOUT(NOM) = 2.85 V 95 160 VOUT(NOM) = 3.0 V 90 155 VOUT(NOM) = 3.3 V 80 145 VOUT(NOM) = 3.5 V 75 140 VOUT(NOM) = 4.5 V 65 120 VOUT(NOM) = 5.0 V 75 105 VOUT(NOM) = 5.14 V 60 105 Output Current Limit VOUT = 90% VOUT(NOM) ICL 250 700 mA Short Circuit Current VOUT = 0 V ISC 690 Quiescent Current IOUT = 0 mA IQ 18 23 /C0109A Shutdown Current VEN ≤ 0.4 V, VIN = 4.8 V IDIS 0.01 1 /C0109A EN Pin Threshold Voltage EN Input Voltage “H” VENH 1.2 V EN Input Voltage “L” VENL 0.4 EN Pull Down Current VEN = 4.8 V IEN 0.2 0.5 /C0109A Turn−On Time COUT = 1 /C0109F, From assertion of VEN to VOUT = 95% VOUT(NOM) 120 /C0109s Power Supply Rejection Ratio IOUT = 20 mA f = 100 Hz f = 1 kHz f = 10 kHz f = 100 kHz PSRR dB Output Voltage Noise f = 10 Hz to 100 kHz IOUT = 1 mA IOUT = 250 mA VN /C0109VRMS Thermal Shutdown Threshold Temperature rising TSDH 160 °C Temperature falling TSDL 140 °C Active Output Discharge Resistance VEN < 0.4 V, Version A only RDIS 280 /C0087 Line Transient (Note 6) VIN = (VOUT(NOM) + 1 V) to (VOUT(NOM) +

1.6 V) in 30 /C0109s, IOUT = 1 mA

VIN = (VOUT(NOM) + 1.6 V) to (VOUT(NOM) +

1 V) in 30 /C0109s, IOUT = 1 mA +1

Load Transient (Note 6) IOUT = 1 mA to 200 mA in 10 /C0109s TranLOAD −40 mV IOUT = 200 mA to 1mA in 10 /C0109s +40 Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be indicated by the Electrical Characteristics if operated under different conditions. 4. Performance g uaranteed over the indicated operating temperature range by design and/or characterization. Production tested at T A = 25°C. Low duty cycle pulse techniques are used during the testing to maintain the junction temperature as close to ambient as possible. 5. Dropout voltage is characterized when V OUT falls 100 mV below VOUT(NOM). 6. Guaranteed by design.

Figure 30. Disable Current vs. Temperature Figure 31. Discharge Resistivity vs. Figure 32. Output Voltage Noise Spectral Density − VOUT = 1.8 V Figure 33. Output Voltage Noise Spectral Density − VOUT = 3.3 V

10 Hz − 100 kHz 100 Hz − 100 kHz

Figure 34. Power Supply Rejection Ratio, Figure 35. Power Supply Rejection Ratio, Figure 36. Power Supply Rejection Ratio, Figure 37. Stability vs. ESR Figure 38. Enable Turn−on Response − Figure 39. Enable Turn−on Response −

1 V/div

Figure 40. Line Transient Response − Figure 41. Line Transient Response − Figure 42. Line Transient Response − Figure 43. Turn−on/off − Slow Rising VIN Figure 44. Load Transient Response − Figure 45. Load Transient Response −

1 V/div100 mA/div50 mV/div

AC signals or noise modulated onto constant input voltage. during sudden load current changes. applied DC bias. Please refer Figure 52. Figure 52. Capacity vs DC Bias Voltage temperature, increasing at low temperature. and to deactivate/activate the active discharge function. the active discharge transistor is turned−off. limitation for the short circuit duration. used as a substitute for proper heat sinking.

www.onsemi.com Reverse Current The PMOS pass transistor has an inherent body diode which will be forward biased in the case that VOUT > VIN. Due to this fact in cases, where the extended reverse current condition can be anticipated the device may require additional external protection. Power Supply Rejection Ratio The NCP160 features very high Power Supply Rejection ratio. If desired the PSRR at higher frequencies in the range 100 kHz – 10 MHz can be tuned by the selection of C OUT capacitor and proper PCB layout. Turn−On Time The turn−on time is defined as the time period from EN assertion to the point in which VOUT will reach 98% of its nominal value. This time is dependent on various application conditions such as V OUT(NOM), COUT, TA. PCB Layout Recommendations To obtain good transient performance and good regulation characteristics place CIN and COUT capacitors close to the device pins and make the PCB traces wide. In order to minimize the solution size, use 0402 or 0201 capacitors with appropriate capacity. Larger copper area connected to the pins will also improve the device thermal resistance. The actual power dissipation can be calculated from the equation above (Equation 2). Expose pad can be tied to the GND pin for improvement power dissipation and lower device temperature.

www.onsemi.com Voltage Description Marking Rotation Package Shipping† NCP160AFCS180T2G 1.8 V 250 mA, Active Discharge A 0° WLCSP4 CASE 567KA (Pb-Free) 5000 / Tape & Reel NCP160AFCS250T2G 2.5 V D 0° NCP160AFCS280T2G 2.8 V E 0° NCP160AFCS285T2G 2.85 V F 0° NCP160AFCS300T2G 3.0 V J 0° NCP160AFCS320T2G 3.2 V V 0° NCP160AFCS330T2G 3.3 V K 0° NCP160AFCS350T2G 3.5 V L 0° NCP160AFCS450T2G 4.5 V P 0° NCP160AFCS500T2G 5.0 V R 0° NCP160AFCS514T2G 5.14 V Q 0° NCP160BFCS180T2G 1.8 V 250 mA, Non-Active Discharge A 90° WLCSP4 CASE 567KA (Pb-Free) 5000 / Tape & Reel NCP160BFCS250T2G 2.5 V D 90° NCP160BFCS280T2G 2.8 V E 90° NCP160BFCS285T2G 2.85 V F 90° NCP160BFCS300T2G 3.0 V J 90° NCP160BFCS330T2G 3.3 V K 90° NCP160BFCS350T2G 3.5 V L 90° NCP160BFCS450T2G 4.5 V P 90° NCP160BFCS500T2G 5.0 V R 90° NCP160BFCS514T2G 5.14 V Q 90° NCP160AFCT180T2G 1.8 V 250 mA, Active Discharge A 0° WLCSP4 CASE 567JZ (Pb-Free) 5000 / Tape & Reel NCP160AFCT250T2G 2.5 V D 0° NCP160AFCT280T2G 2.8 V E 0° NCP160AFCT285T2G 2.85 V F 0° NCP160AFCT300T2G 3.0 V J 0° NCP160AFCT330T2G 3.3 V K 0° NCP160AFCT350T2G 3.5 V L 0° NCP160AFCT450T2G 4.5 V P 0° NCP160AFCT500T2G 5.0 V R 0° NCP160AFCT514T2G 5.14 V Q 0° NCP160BFCT180T2G 1.8 V 250 mA, Non-Active Discharge A 90° WLCSP4 CASE 567JZ (Pb-Free) 5000 / Tape & Reel NCP160BFCT210T2G 2.1 V T 90° NCP160BFCT250T2G 2.5 V D 90° NCP160BFCT280T2G 2.8 V E 90° NCP160BFCT285T2G 2.85 V F 90° NCP160BFCT300T2G 3.0 V J 90° NCP160BFCT330T2G 3.3 V K 90° NCP160BFCT350T2G 3.5 V L 90° NCP160BFCT450T2G 4.5 V P 90° NCP160BFCT500T2G 5.0 V R 90° NCP160BFCT514T2G 5.14 V Q 90°

www.onsemi.com Device Nominal Output Voltage Description Marking Package Shipping NCP160AMX180TBG 1.8 V 250 mA, Active Discharge DF XDFN-4 (Pb-Free) 3000 / Tape & Reel (Available Soon) NCP160AMX250TBG 2.5 V DG NCP160AMX280TBG 2.8 V DH NCP160AMX285TBG 2.85 V DJ NCP160AMX300TBG 3.0 V DK NCP160AMX320TBG 3.2 V DY NCP160AMX330TBG 3.3 V DA NCP160AMX350TBG 3.5 V DL NCP160AMX450TBG 4.5 V DM NCP160AMX500TBG 5.0 V DW NCP160AMX514TBG 5.14 V DC NCP160BMX180TBG 1.8 V 250 mA, Non-Active Discharge EF XDFN-4 (Pb-Free) 3000 / Tape & Reel (Available Soon) NCP160BMX250TBG 2.5 V EG NCP160BMX280TBG 2.8 V EH NCP160BMX285TBG 2.85 V EJ NCP160BMX300TBG 3.0 V EK NCP160BMX330TBG 3.3 V EA NCP160BMX350TBG 3.5 V EL NCP160BMX450TBG 4.5 V EM NCP160BMX500TBG 5.0 V EW NCP160BMX514TBG 5.14 V EC †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.

www.onsemi.com PACKAGE DIMENSIONS È WLCSP4, 0.64x0.64 CASE 567KA ISSUE O SEATING PLANE 0.05 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. DIM A MIN MAX 0.35 MILLIMETERS D 0.64 BSC E b 0.185 0.215 e 0.35 BSC 0.45 D E A B PIN A1 REFERENCE e A0.05 BC 0.03 C 0.05 C 4X b B A 0.05 C A C 0.14 0.18

0.64 BSC

0.05 C2X TOP VIEW

e A2 0.25 REF PITCH 0.20 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* 0.35 0.35 RECOMMENDED A1 PACKAGE OUTLINE PITCH

www.onsemi.com PACKAGE DIMENSIONS XDFN4 1.0x1.0, 0.65P CASE 711AJ ISSUE O NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.15 AND 0.20 mm FROM THE TERMINAL TIPS. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. ÉÉ ÉÉ A B E D BOTTOM VIEW b e NOTE 3 2X 0.05 C PIN ONE REFERENCE TOP VIEW 2X 0.05 C A (A3) 0.05 C 0.05 C C SEATING PLANESIDE VIEW L4X 1 2 DIM MIN MAX MILLIMETERS A 0.33 0.43 A1 0.00 0.05 A3 0.10 REF b 0.15 0.25 D 1.00 BSC D2 0.43 0.53 E 1.00 BSC e 0.65 BSC L 0.20 0.30 *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. MOUNTING FOOTPRINT* 1.20 0.260.24 4X DIMENSIONS: MILLIMETERS 0.39 RECOMMENDED PACKAGE OUTLINE NOTE 4 e/2 45 /C0053 AM0.05 B C 4 3 0.65 PITCH DETAIL A b2 0.02 0.12 L2 0.07 0.17 0.52 0.114X L24X DETAIL A b24X

www.onsemi.com PACKAGE DIMENSIONS È WLCSP4, 0.64x0.64 CASE 567JZ ISSUE O SEATING PLANE 0.05 C NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. COPLANARITY APPLIES TO SPHERICAL CROWNS OF SOLDER BALLS. DIM A MIN MAX −−− MILLIMETERS D 0.64 BSC E b 0.195 0.225 e 0.35 BSC 0.33 D E A B PIN A1 REFERENCE e A0.03 BC 0.05 C 4X b B A 0.05 C A C 0.04 0.08 e A2 0.23 REF PITCH 0.20 DIMENSIONS: MILLIMETERS *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. SOLDERING FOOTPRINT* 0.35 0.35 RECOMMENDED A1 PACKAGE OUTLINE PITCH ON Semiconductor and the are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidia ries in the United States and/or other countries. SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5817−1050 NCP160/D LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative