CS98ULPA877AHLF-T

ICS98ULPA877A IDT | Alldatasheet

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Systems, Inc. ICS98ULPA877A Advance Information 1177C—05/23/07 1.8V Low-Power Wide-Range Frequency Clock Driver Pin Configuration 40-Pin MLF Recommended Application:  DDR2 Memory Modules / Zero Delay Board Fan Out  Provides complete DDR2 DIMM logic solution Product Description/Features:  Low skew, low jitter PLL clock driver  1 to 10 differential clock distribution (SSTL_18)  Feedback pins for input to output synchronization  Spread Spectrum tolerant inputs  Auto PD when input signal is at a certain logic state Switching Characteristics:  Period jitter: 40ps (DDR2-400/533) 30ps (DDR2-667/800)  Half-period jitter: 60ps (DDR2-400/533) 50ps (DDR2-667/800)  OUTPUT - OUTPUT skew: 40ps (DDR2-400/533) 30ps (DDR2-667/800)  CYCLE - CYCLE jitter 40ps 52-Ball BGA Top View Block Diagram ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners. FBOUTT FBOUTC FBIN_INT FBIN_INC PLL CLK_INT CLK_INC POWER DOWN AND TEST MODE LOGIC LD AVDD OE OS LD or OE LD, OS, or OE PLL BYPASS 10KΩ -1 0 0 KΩ CLKT0 CLKC0 CLKT1 CLKC1 CLKT2 CLKC2 CLKT3 CLKC3 CLKT4 CLKC4 CLKT5 CLKC5 CLKT6 CLKC6 CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 CLKC9 (1) NOTE: 1. The Logic Detect (LD) powers down the device when a logic LOW is applied to both CLK_INT and CLK_INC. B C D E F G H J K A 123456 V DDQ 40 39 38 37 36 35 34 33 32 31 V DDQ 11 12 13 14 15 16 17 18 19 20 V DDQ V DDQ VDDQ FB_INT FB_INC FBOUTC FBOUTT OE OS VDDQ GND VDDQ AGND AVDD CLK_INT CLK_INC VDDQ VDDQ CLKC2 CLKT2 CLKC7 CLKT7 CLKC3 CLKT3 CLKC4 CLKT4 CLKC9 CLKT9 CLKC8 CLKT8 CLKC1 CLKT1 CLKC0 CLKT0 CLKC5 CLKT5 CLKC6 CLKT6 12345 6 A CLKT1 CLKT0 CLKC0 CLKC5 CLKT5 CLKT6 B CLKC1 GND GND GND GND CLKC6 C CLKC2 GND NB NB GND CLKC7 D CLKT2 VDDQ VDDQ VDDQ OS CLKT7 E CLK_INT VDDQ NB NB VDDQ FB_INT F CLK_INC VDDQ NB NB OE FB_INC G AGND VDDQ VDDQ VDDQ VDDQ FB_OUTC H AVDD GND NB NB GND FB_OUTT J CLKT3 GND GND GND GND CLKT8 K CLKC3 CLKC4 CLKT4 CLKT9 CLKC9 CLKC8

1177C—05/23/07 Pin Descriptions lanimreT emaN noitpircseD lacirtcelE scitsiretcarahC DNGAd nuorGgolanA dnuorG VA DD rewopgolanA lanimonV8.1 TNI_KLCr otsisernwodllup)mhOK001-K01(ahtiwtupnikcolC tupnilaitnereffiD CNI_KLC rotsisernwodllup)mhOK001-K01(ahtiwtupnikcolcyratnelpmoC tupnilaitnereffiD TNI_BFt upnikcolckcabdeeF tupnilaitnereffiD CNI_BFt upnikcolckcabdeefyratnemelpmoC tupnilaitnereffiD TTUO_BFt uptuokcolckcabdeeF tuptuolaitnereffiD CTUO_BFt uptuokcolckcabdeefyratnemelpmoC tuptuolaitnereffiD EO) suonorhcnysA(elbanEtuptuO tupniSOMCVL SOV roDNGotdeit(tceleStuptuO QDD )t upniSOMCVL DNGd nuorG dnuorG V QDD rewoptuptuodnacigoL lanimonV8.1 ]9:0[TKLCs tuptuokcolC stuptuolaitnereffiD ]9:0[CKLCs tuptuokcolcyratnemelpmoC stuptuolaitnereffiD BNl laboN The PLL clock buffer, ICS98ULPA877A, is designed for a VDDQ of 1.8 V , a AVDD of 1.8 V and differential data input and output levels. Package options include a plastic 52-ball VFBGA and a 40-pin MLF . ICS98ULPA877A is a zero delay buffer that distributes a differential clock input pair (CLK_INT, CLK_INC) to ten differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock outputs (FB_OUTT, FBOUTC). The clock outputs are controlled by the input clocks (CLK_INT, CLK_INC), the feedback clocks (FB_INT, FB_INC), the LVCMOS program pins (OE, OS) and the Analog Power input (AVDD). When OE is low, the outputs (except FB_OUTT/FB_OUTC) are disabled while the internal PLL continues to maintain its locked-in frequency. OS (Output Select) is a program pin that must be tied to GND or V DDQ. When OS is high, OE will function as described above. When OS is low, OE has no effect on CLKT7/CLKC7 (they are free running in addition to FB_OUTT/FB_OUTC). When AVDD is grounded, the PLL is turned off and bypassed for test purposes. When both clock signals (CLK_INT, CLK_INC) are logic low, the device will enter a low power mode. An input logic detection circuit on the differential inputs, independent from the input buffers, will detect the logic low level and perform a low power state where all outputs, the feedback and the PLL are OFF . When the inputs transition from both being logic low to being differential signals, the PLL will be turned back on, the inputs and outputs will be enabled and the PLL will obtain phase lock between the feedback clock pair (FB_INT, FB_INC) and the input clock pair (CLK_INT, CLK_INC) within the specified stabilization time t STAB. The PLL in ICS98ULPA877A clock driver uses the input clocks (CLK_INT, CLK_INC) and the feedback clocks (FB_INT, FB_INC) to provide high-performance, low-skew, low-jitter output differential clocks (CLKT[0:9], CLKC[0:9]). ICS98ULPA877A is also able to track Spread Spectrum Clocking (SSC) for reduced EMI.

1177C—05/23/07 Function Table stupnIs tuptuO LLP DDVAE OS OT NI_KLCC NI_KLCT KLCC KLCT TUO_BFC TUO_BF DNGH X L H L H L H f fO/dessapyB DNGH X H L H L H L f fO/dessapyB DNGL H L H ) Z(L*) Z(L*L H f fO/dessapyB DNGL L H L ,)Z(L* 7TKLC evitca ,)Z(L* 7CKLC evitca H Lf fO/dessapyB )mon(V8.1L H L H ) Z(L*) Z(L*L H n O )mon(V8.1L L H L ,)Z(L* 7TKLC evitca ,)Z(L* 7CKLC evitca HL n O )mon(V8.1H X L H L H LH n O )mon(V8.1H X H L H L HL n O )mon(V8.1X X L L ) Z(L*) Z(L*) Z(L*) Z(L*f fO )mon(V8.1X X H H d evreseR *L(Z) means the outputs are disabled to a low stated meeting the IODL limit. ICS98ULPA877A is available in Commercial Temperature Range (0°C to 70°C) and Industrial Temperature Range (-40°C to +85°C). See Ordering Information for details

1177C—05/23/07 Absolute Maximum Ratings DDQ + 0.5V Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters Commercial: TA = 0°C - 70°C; Industrial: TA = -40°C - +85°C; Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input High Current (CLK_INT, CLK_INC) IIH VI = VDDQ or GND ±250 µA Input Low Current (OE, OS, FB_INT, FB_INC) IIL VI = VDDQ or GND ±10 µA Output Disabled Low Current IODL OE = L, VODL = 100mV 100 µA IDD1.8 CL = 0pf @ 410MHz 300 mA IDDLD CL = 0pf 500 µA Input Clamp Voltage VIK VDDQ = 1.7V Iin = -18mA -1.2 V IOH = -100 μA VDDQ - 0.2 V IOH = -9 mA 1.1 1.45 V IOL=100 μA 0.25 0.10 V IOL=9 mA 0.6 V Input Capacitance1 CIN VI = GND or VDDQ 23 p F Output Capacitance1 COUT VOUT = GND or VDDQ 23 p F 1Guaranteed by design, not 100% tested in production. Operating Supply Current High-level output voltage VOH Low-level output voltage VOL

1177C—05/23/07 Notes: 1. Unused inputs must be held high or low to prevent them from floating. 2. DC input signal voltage specifies the allowable DC execution of differential input. 3. Differential inputs signal voltages specifies the differential voltage [VTR-VCP] required for switching, where VTR is the true input level and VCP is the complementary input level. 4. Differential cross-point voltage is expected to track variations of V DDQ and is the voltage at which the differential signal must be crossing. Recommended Operating Condition (see note1) Commercial: TA = 0°C - 70°C; Industrial: TA = -40°C - +85°C; Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage V DDQ, AVDD 1.7 1.8 1.9 V CLK_INT, CLK_INC, FB_INC, FB_INT 0.35 x VDDQ V OE, OS 0.35 x V DDQ V CLK_INT, CLK_INC, FB_INC, FB_INT 0.65 x VDDQ V OE, OS 0.65 x V DDQ V DC input signal voltage (note 2) VIN -0.3 V DDQ + 0.3 V DC - CLK_INT, CLK_INC, FB_INC, FB_INT 0.3 V DDQ + 0.4 V AC - CLK_INT, CLK_INC, FB_INC, FB_INT 0.6 V DDQ + 0.4 V Output differential cross- voltage (note 4) VOX VDDQ/2 - 0.10 V DDQ/2 + 0.10 V Input differential cross- voltage (note 4) VIX VDDQ/2 - 0.15 V DD/2 V DDQ2 + 0.15 V High level output current I OH -9 mA Low level output current I OL 9m A Operating free-air temperature TA -40 85 °C Differential input signal voltage (note 3) VID Low level input voltage V IL High level input voltage V IH

1177C—05/23/07 NOTE: The PLL must be able to handle spread spectrum induced skew. NOTE: Operating clock frequency indicates a range over which the PLL must be able to lock, but in which it is not required to meet the other timing parameters. (Used for low speed system debug.) NOTE: Application clock frequency indicates a range over which the PLL must meet all timing parameters. NOTE: Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal, within the value specificied by the Static Phase Offset (t∅), after power-up. During normal operation, the stabilization time is also the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal when CK and CK# go to a logic low state, enter the power-down mode and later return to active operation. CK and CK# may be left floating after they have been driven low for one complete clock cycle. Timing Requirements Commercial: TA = 0°C - 70°C; Industrial: TA = -40°C - +85°C; Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Max clock frequency freq op 1.8V+0.1V @ 25°C 95 410 MHz Application Frequency Range freqApp 1.8V+0.1V @ 25°C 160 410 MHz Input clock duty cycle d tin 40 60 % CLK stabilization T STAB 15 µs

1177C—05/23/07 Notes: 1. Switching characteristics guaranteed for application frequency range. 2. Static phase offset shifted by design. Switching Characteristics1 Commercial: TA = 0°C - 70°C; Industrial: TA = -40°C - +85°C; Supply Voltage AVDDQ, VDDQ = 1.8 V +/- 0.1V (unless otherwise stated) PARAMETER SYMBOL CONDITION (MHz) MIN TYP MAX UNITS Output enable time ten OE to any output 4.73 8 ns Output disable time tdis OE to any output 5.82 8 ns 160 to 270 -40 40 ps 271 to 410 -30 30 ps 160 to 270 -60 60 ps 271 to 410 -50 50 ps Input Clock 1 2.5 4 v/ns Output Enable (OE), (OS) 0.5 v/ns Output clock slew rate SLr1(o) 1.5 2.5 3 v/ns tjit(cc+) 04 0 p s tjit(cc-) 0 -40 ps 160 to 270 -50 50 ps 271 to 410 -20 20 ps Static Phase Offset tSPO 2 271 to 410 -50 0 50 ps t jit (per) + t (Ø)dyn + t skew(o) ∑(su) 80 ps t(Ø)dyn + tskew(o) ∑t (h) 60 ps 160 to 270 40 ps 271 to 410 30 ps SSC modulation frequency 30.00 33 kHz SSC clock input frequency deviation 0.00 -0.50 % PLL Loop bandwidth (-3 dB from unity gain) 2.0 MHz 160 to 410 Period jitter tjit (per) Input slew rate SLr1(i) 160 to 410 Cycle-to-cycle period jitter t(Ø)dyn Half-period jitter tjit(hper) Output to Output Skew tskew Dynamic Phase Offset

Figure 11. AV DD Filtering *Place the 2200pF capacitors close to the PLL. trace to one GND via (farthest from PLL). *Recommended bead: Fair-rite P/N 2506036017Y0 or equivalent (0.8 Ω DC max., 600Ω at 100MHz).

1177C—05/23/07 D E T e HORIZ VERT TOTAL d h D1 E1 b c Min/Max Min/Max Min/Max * Source Ref.: JEDEC Publication 95, 10-0055 ALL DIMENSIONS IN MILLIMETERS REF. DIMENSIONS ----- BALL GRID ----- Max. Note: Ball grid total indicates maximum ball count for packa ge. Lesser quantity may be used. MO-205*, MO-225** SEATING PLANE 0.12 C C A B C D D E TOP VIEW T hT Y P dT Y P 4321 Numeric Designations for Horizontal Grid bR E F cR E F TYP-e- TYP-e- Alpha Designations for Vertical Grid (Letters I, O, Q, and S not used)

Ordering Information

Example: Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Temperature Grade Blank = 0°C to +70°C (Commercial) I = -40°C to +85°C (Industrial) Package Type H = BGA Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device ICS XXXX y H z LF- T

1177C—05/23/07 ALL DIMENSIONS IN MILLIMETERS N SYMBOL MIN. MAX. ND A 0.80 1.00 NE A1 0 0.05 D x E BASIC A3 D2 MIN. / MAX. b 0.18 0.30 E2 MIN. / MAX. e L MIN. / MAX. 10-0053 THERMALLY ENHANCED, VERY THIN, FINE PITCH QUAD FLAT / NO LEAD PLASTIC PACKAGE 0.30 / 0.50

0.25 Reference

0.50 BASIC

6.00 x 6.00 2.75 / 3.05 2.75 / 3.05 Source Reference: MLF2™ S C 0.08 C Seating Plane A Anvil Singulation or Sawn Singulation N Index Area E D Top View L E2/2 (ND -1 )x e (Ref.) ND &N E Even (Ref.) If ND &N E are Even (Typ.)e/2 b (NE -1 )x e (Ref.) Thermal Base ND &N E Odd (Ref.) e D2/2 Example: Designation for tape and reel packaging Lead Free, RoHS Compliant (Optional) Temperature Grade Blank = 0°C to +70°C (Commercial) I = -40°C to +85°C (Industrial) Package Type K = MLF Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device ICS XXXX y K z LF- T