CS86

CS86 FUJITSU | Alldatasheet

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DS06-20209-2EFUJITSU SEMICONDUCTOR DATA SHEET Semicustom CMOS Standard cell CS86 Series n DESCRIPTION The CS86 series of 0.18 mm standard cells is a line of CMOS ASICs based on higher integration implemented by introducing wiring pitch reduction technology and on I/O pad placement technology to the conventional CS81 series. The CS86 series has three types of cell sets (CS86MN, CS86MZ, and CS86ML), covering a variety of applications, from portable devices requiring low power consumption to image processors requiring large-scale circuitry and high speed.The three types of cell sets can be contained on one chip, allowing those system LSIs to be imple- mented which require low power consumption as well as high-speed operation for certain types of processing. n FEATURES

• T echnology : 0.18 mm silicon-gate CMOS, 4- to 6-layer wiring The same chip can therefore incorporate the standard transistor cell and the ultrahigh- speed or low-leakage process cell together.
• Supply voltage : +1.8 V – 0.15 V (normal) to +1.1 V – 0.1 V
• Junction temperature range : -40 °C to +125 °C
• Cell set CS86MN : Offers standard transistor characteristics. Designed as a library for products requiring higher throughputs. CS86MZ : Offers transistor characteristics for ultra high-speed operation. Designed as a library for products that require higher processing speeds than those provided by CS86MN. CS86ML : Offers transistor charactersistics with less leak current. Designed as a library for mobile devices and other products requiring lower power consumption.
• Cell Specifications : *1 : 2 input NAND cell (low-power type) , F/O = 2, normal load, Power supply voltage 1.8 V, T emperature = +25 °C *2 : 2 input NAND cell (low-power type) , F/O = 1, 4 Grid, Power supply voltage 1.8 V, T emperature = +25 °C *3 : 2 input NAND cell (low-power type) , F/O = 0, non load, Power supply voltage 1.8 V, T emperature = +25 °C (Continued) Cell set name CS86MZ CS86MN CS86ML Delay time*1 70 ps 88 ps 136 ps Power consumption*2 42.7 nW/MHz 40.1 nW/MHz 38.3 nW/MHz Leak power*3 3.922 nW 0.023 nW 0.0067 nW

(Continued)

• Output buffer cells with noise reduction circuits
• Input buffer cells and bidirectional buffer cells with on-chip input pull-up/pull-down resistors
• Buffer cells for crystal oscillation circuits
• Special interfaces : SSTL2, PCI, P-CML, T-LVTTL, USB 2.0, IEEE1394, and others.
• IP macros : CPU (ARM9, FR-V, and others) , DSP, PCI, IEEE1394, USB 2.0, IrDA, PLL, DAC, ADC, and others.
• Capable of incorporating compiled cells (RAM/ROM/Register file/Delay line)
• Configurable internal bus circuits
• Advanced hardware/software co-design environment
• Short-term development using Physical Synthesis tool
• Low power consumption using Low Power Synthesis tool
• Short-term development using a timing driven layout tool
• Hierarchical design environment for supporting large-scale circuits
• Support for Signal-Integrity
• Support for Memory (RAM, ROM) SCAN
• Support for Memory (RAM) BIST
• Support for Boundary SCAN
• Support for path delay test
• A variety of package options : QFP, TQFP, LQFP, HQFP, PBGA, FBGA, FLGA, EBGA

n MACRO LIBRARY (Including macros being prepared) 1. Logic cells 2. IP macro

• Adder • AND-OR
• AND-OR Inverter • Decoder
• Clock Buffer • NON-Scan Flip Flop
• Latch • Inverter
• NAND • Buffer
• AND • OR-AND Inverter
• NOR • OR
• OR-AND • Delay Buffer
• Scan Flip Flop • Selector
• ENOR • EOR
• Boundary Scan Register • Dummy Clock Buffer
• Bus Driver • Others CPU FR-V, ARM9, and others. DSP Communications DSP, DSP for Digital AV, and others. Peripheral Macro Interval timer, Interruption controller, DMA controller, RTC, Calender, UART, and others. Interface macro PCI, IEEE1394, USB 2.0, IrDA, and others. Multimedia processing macros JPEG, MPEG 4.0, and others. Mixed signal macros ADC, DAC, OPAMP, and others. Compiled macros RAM (1 port, 2 port) , ROM, Delay Line, Register file, and others. PLL Analog PLL I/O macro Compatible with various interface levels between 1.1 V and 5 V; SSTL2, PCI, P-CML, T-LVTTL, USB, IEEE1394, and others.

Compiled cells are macro cells which are automatically generated with the bit/word configuration specified. The CS86 series has the following types of compiled cells. (Note that each macro is different in word/bit range depending on the column type.) 1. Clock synchronous single-port RAM (1 address : 1 RW)

• High density type/High density partial write type
• Super high density type/Super high density partial write type
• Large scale partial write type
• Super high density large scale partial write type
• High speed type 2. Clock synchronous dual-port RAM (2 addresses : 1 RW, 1 R)
• High density type/Partial write type 3. Clock synchronous register file (3 addresses : 1 W, 2 R) 4. Clock synchronous register file (4 addresses : 2 W, 2 R) Column type Memory capacity Word range Bit range Unit 4 16 to 72 K 16 to 1 K 1 to 72 bit 16 64 to 72 K 64 to 4 K 1 to 18 bit Column type Memory capacity Word range Bit range Unit 4 64 to 144 K 32 to 2 K 2 to 72 bit Column type Memory capacity Word range Bit range Unit 16 24 to 1152 K 4K to 16 K 6 to 72 bit Column type Memory capacity Word range Bit range Unit 16 2 to 1152 K 512 to 16 K 4 to 72 bit Column type Memory capacity Word range Bit range Unit 8 256 to 144 K 64 to 2 K 4 to 72 bit Column type Memory capacity Word range Bit range Unit 4 16 to 72 K 16 to 1 K 1 to 72 bit 16 64 to 72 K 64 to 4 K 1 to 18 bit Column type Memory capacity Word range Bit range Unit 1 4 to 4608 4 to 64 1 to 72 bit Column type Memory capacity Word range Bit range Unit 1 4 to 4608 4 to 64 1 to 72 bit

1. Clock synchronous ROM (1 addresses : 1 R) 6. Clock synchronous delay line memory (2 addresses : 1 W, 1 R) Column type Memory capacity Word range Bit range Unit 16 256 to 1024 K 128 to 8 K 2 to 128 bit 64 1 to 1024 K 512 to 32 K 2 to 32 bit Column type Memory capacity Word range Bit range Unit 8 256 to 32 K 32 to 1 K 8 to 32 bit 16 384 to 32 K 64 to 2 K 6 to 16 bit 32 512 to 32 K 128 to 4 K 4 to 8 bit

n ABSOLUTE MAXIMUM RATINGS *1 : Internal gate part in case of single power supply or dual power supply *2 : I/O part in case 3.3 V I/F or 2.5 V I/F is used by dual power supply. *3 : DC current which continues more than 10 ms, or average DC current *4 : in case of I/O cell for clock input *5 : bps = bit per second

• Supply pin current value for one V DD /GND pin (mA) (a) Maximum current for one I/O*1 Tj = +125 °C*2 (VSS = 0 V) Parameter Symbol Rating Unit Min Max Supply voltage V DD - 0.5 2.5 *1 V 4.0 *2 Input voltage V I - 0.5 V Output voltage V O - 0.5 V Storage temperature Tst -55 +125 °C Junction temperature T j -40 +125 °C Output current*3 IO –10 (3.3 VCMOS, 2.5 VCMOS) mA – 7.5 (1.8 VCMOS) Input signal transmitting rate RI ¾ Clock input*4 : 200 Normal input : 100 Mbps*5 Output signal transmitting rate RO ¾ 100 Mbps* 5 Output load capacitance C O ¾ 3000/RO pF Supply pin current I D See “• Supply pin current for one VDD /GND pin (mA) “ mA Frame Source type Maximum current (at standard source) (mA) Number of layers YH VDDE 68 4 VDDE 59 5 VDDE 59 6 VDDI, VDD , VSS 68 4 VDDI, VDD , VSS 93 5 VDDI, VDD , VSS 118 6

(b) Current value that one I/O can provide to the core T j = +125°C*2 *1 : Maximum current for one I/O includes the supply current to the I/O part and the core part. *2 : The current values change according to the junction temperature. When the junction temperature is not +125°C, multiply the value by the following coefficients. Tj = + 90 °C : 2 . 8 Note : How to calculate the number of required supply pins In case of a frame with 6-layer wiring (2 power supplies)

• Maximum current for one V DD /GND pin VDDE = 59 mA/pin calucurated using the value in “(a) Maximum supply pin current for one I/O” VDDI = VSS = 59 mA/pin calucurated using the value in “(b) Current value that one I/O can provide to the core”
• Needed supply pin count (internal power supply/external power supply/VSS ) : Ni/Ne/Ns DC internal maximum power-supply current : Iimax, DC external maximum power-supply current : Iemax Ni = Iimax/59mA, Ne = Iemax/59mA, Ns = Iimax/59mA + Iemax/59mA WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Frame Source type Maximum current (at standard source) (mA) Number of layers YH VDDI, VDD , VSS 34 4 VDDI, VDD , VSS 34 5 VDDI, VDD , VSS 59 6

n RECOMMENDED OPERATING CONDITIONS

• Single power supply (VDD = 1.8 V – 0.15 V) * : VDDI = 1.1 V–0.1 V is being prepared. * : VDDI = 1.1 V–0.1 V is being prepared. (VSS = 0 V) Parameter Symbol Value Unit Min Typ Max Supply voltage V DD 1.65 1.8 1.95 V “H” level input voltage V IH VDD · 0.65 ¾ VDD + 0.3 V “L” level input voltage V IL -0.3 ¾ VDD · 0.35 V Junction temperature T j -40 ¾+ 125 °C (VSS = 0 V) Parameter Symbol Value Unit Min Typ Max Supply voltage VDDE 3.0 3.3 3.6 V VDDI 1.65 1.8 1.95 1.4 1.5 1.6 1.0 1.1 1.2 “H” level input voltage

1.8 V CMOS

VDDI · 0.65 ¾ VDDI + 0.3 V 3.3 V CMOS 2.0 ¾ VDDE + 0.3 “L” level input voltage -0.3 ¾ VDDI · 0.35 V 3.3 V CMOS -0.3 ¾ 0.8 Junction temperature T j -40 ¾+ 125 °C (VSS = 0 V) Parameter Symbol Value Unit Min Typ Max Supply voltage VDDE 2.3 2.5 2.7 V VDDI 1.65 1.8 1.95 1.4 1.5 1.6 1.0 1.1 1.2 “H” level input voltage VDDI · 0.65 ¾ VDDI + 0.3 V 2.5 V CMOS 1.7 ¾ VDDE + 0.3 “L” level input voltage -0.3 ¾ VDDI · 0.35 V 2.5 V CMOS -0.3 ¾ 0.7 Junction temperature T j -40 ¾+ 125 °C

WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.

n ELECTRICAL CHARACTERISTICS 1. DC characteristics

• Single power supply : VDD = 1.8 V standard * : Refer to “ (1) 1.8 V” in n V-I CHARACTERISTICS.
• Dual power supply : VDDE = 3.3 V, VDDI = 1.8 V/1.5 V/1.1 V *1 : Refer to “ (2) 3.3 V” in n V-I CHARACTERISTICS. *2 : Refer to “ (1) 1.8 V” in n V-I CHARACTERISTICS. (VDD = 1.8 V – 0.15 V, VSS = 0 V, Tj = -40 °C to +125 °C) Parameter Symbol Conditions Value Unit Min Typ Max “H” level output voltage VOH IOH = -100 mAV DD -0.2 ¾ VDD V “L” level output voltage VOL IOL = 100 mA0 ¾ 0.2 V “H” level output V-I characteristics ¾ 1.8 V VDD = 1.8 V–0.15 V * ¾ “L” level output V-I characteristics ¾ 1.8 V VDD = 1.8 V–0.15 V * ¾ Input leakage current I L ¾¾ ¾ – 5 mA Pull up/Pull down resistance R P Pull up VIL = 0, Pull down VIH = VDD 81 8 4 0 k W VSS = 0 V, Tj = -40 °C to +125 °C) Parameter Symbol Conditions Value Unit Min Typ Max “H” level output voltage VOH4 3.3 V Output IOH = -100 mAV DDE -0.2 ¾ VDDE V VOH2 1.8 V Output IOH = -100 mAV DDI-0.2 ¾ VDDI “L” level output voltage VOL4 3.3 V Output IOL = 100 mA0 ¾ 0.2 V VOL2 1.8 V Output IOL = 100 mA0 ¾ 0.2 “H” level output V-I characteristics ¾ 3.3 V VDDE = 3.3 V–0.3 V *1 1.8 V VDDI = 1.8 V–0.15 V *2 “L” level output V-I characteristics ¾ 3.3 V VDDE = 3.3 V–0.3 V *1 1.8 V VDDI = 1.8 V–0.15 V *2 Input leakage current I L ¾¾ ¾ – 5 mA Pull up/Pull down resistance R P 3.3 V Pull up VIL = 0, Pull down VIH = VDDI 10 33 80 kW 1.8 V Pull up VIL = 0, Pull down VIH = VDDI 81 8 4 0

• Dual power supply : VDDE = 2.5 V, VDDI = 1.8 V/1.5 V/1.1 V * : Refer to “ (1) 1.8 V” in n V-I CHARACTERISTICS. 2. AC CHARACTERISTICS VSS = 0 V, Tj = - 40 °C to +125 °C. (Standard specification) *1 : Delay time = propagation delay time, enable time, disable time. *2 : “typ” is calculated based on the cell specifications. *3 : Measurement conditions Note : AC characteristics are determined based on junction temperature, voltage conditions, and process variation. VSS = 0 V, Tj = -40 °C to +125 °C) Parameter Symbol Conditions Value Unit Min Typ Max “H” level output voltage VOH3 2.5 V Output IOH = -100 mAV DDE -0.2 ¾ VDDE V VOH2 1.8 V Output IOH = -100 mAV DDI-0.2 ¾ VDDI “L” level output voltage VOL3 2.5 V Output IOL = 100 mA0 ¾ 0.2 V VOL2 1.8 V Output IOL = 100 mA0 ¾ 0.2 “H” level output V-I characteristics ¾ 2.5 V VDDE = 2.5 V–0.2 V ¾ 1.8 V VDDI = 1.8 V–0.15 V * “L” level output V-I characteristics ¾ 2.5 V VDDE = 2.5 V–0.2 V ¾ 1.8 V VDDI = 1.8 V–0.15 V * Input leakage current I L ¾¾ ¾ – 5 mA Pull up/Pull down resistance R P 2.5 V Pull up VIL = 0, Pull down VIH = VDDE ¾ 25 ¾ kW 1.8 V Pull up VIL = 0, Pull down VIH = VDDI 81 8 4 0 Parameter Symbol Value Unit Min Typ Max Delay time t pd*1 typ*2 · tmin*3 typ*2 · ttyp*3 typ*2 · tmax*3 ns Measurement condition tmin ttyp tmax

(1) 1.8 V -10 IOH (mA) VOH -VDD (V) -2.0 -1.0 0.0 -20 -30 -40 Max Min Typ IOL (mA) VOL (V) 2.01.00.0 Max Min Typ -10 IOH (mA) VOH -VDD (V) -2.0 -1.0 0.0 -20 -30 -40 Max Min Typ -50 -60

10 IOL (mA)

VOL (V) 2.01.00.0 Min Typ Max50 Conditions Min : Process = Slow, Tj = +125 °C, VDD = 1.65 V Typ : Process = Typical, Tj = +25 °C, VDD = 1.80 V Max : Process = Fast, Tj = -40 °C, VDD = 1.95 V

1.8 V CMOS “H” level output

(L, M type)

1.8 V CMOS “L” level output

(L, M type) (H, V type) (H, V type)

(2) 3.3 V -20 IOH (mA) VOH -VDDE (V) -4.0 -1.0 0.0 -40 -60 -80 -2.0-3.0 Max Min Typ IOL (mA) VOL (V) 4.01.00.0 3.02.0 Max Min Typ -60 IOH (mA) VOH -VDDE (V) -2.0 -1.0 0.0 -20 -80 -40 -3.0-4.0 -100 -120 Max Min Typ IOL (mA) VOL (V) 4.01.00.0 100 120 Min Typ Max 2.0 3.0 Conditions Min : Process = Slow, Tj = +125 °C, VDDE = 3.0 V Typ : Process = Typical, Tj = +25 °C, VDDE = 3.3 V Max : Process = Fast, Tj = -40 °C, VDDE = 3.6 V

3.3 V CMOS “H” level output

(L, M type)

3.3 V CMOS “L” level output

(L, M type) (H, V type) (H, V type)

n INPUT/OUTPUT PIN CAPACITANCE (Tj = +25 °C, VDD = VI = 0 V, f = 1 MHz) Note : Capacitance varies according to the package and the location of the pin. n DESIGN METHOD The integrated standard-cell design environment, SCCAD2, provided for conventional models now supports the CS86 series. This allows you to design ASICs that operate at up to 500 MHz with up to 40 million gates and to halve the layout design period. The Fujitsu’s tool GLOSCAD also supports the satandard cell design for CS86 series.

• Physical Synthesis Physical Synthesis tool support is provided on a consulting business basis. A conventional style of ASIC devel- opment has a problem that iterations between logic synthesis and layout processing are caused by wiring congestion and the difference between actual and estimated wiring capacities. Supporting logic synthesis based on physical information reduces such iterations and contributes to convergence of ASIC design within the scheduled development period.
• Low Power Synthesis The Low Power Synthesis tool is supported, which enables the use of gated clock buffers of hard macro type incorporating sequential cells, such as latches. The use of gated clock buffers of hard macro type provides low power consumption by the clock line. It also provides reliable operation, reduction in script complexity, and shorter turnaround time (T A T) for processing.
• Timing Driven Layout Performing automatic placement and wiring based on chip-level timing constraints. This prevents post-layout timing problems from developing, which are prominent in particular in the field of deep submicron designs. In addition, all of remaining timing errors are automatically corrected by the Fujitsu’s automatic timing correction system. This shortens the development time from the end of creating a net list to the beginning of the prototyping stage.
• Hierarchical Design A top-down hierarchical design approach is taken consistently from logic design to physical design to support larger-scale circuit integration based on deep submicron designing. This enables multiple blocks to be designed logically and physically at the same time and timing convergence to be attained in a short period, providing a design environment capable of easily supporting ultra-large-scale integration of circuits.
• Support for Signal Integrity Automated power wiring enables layout satisfying the design specifications within a short period. The power width automatic adjustment function designed taking account of internal power consumption and clock frequencies can produce chips satisfying the current density and voltage drop restrictions without human intervention. Also, a verification system is prepared to check the signal noise or delay penalty owing to capacitive coupling between signal conductors and the voltage drop caused by simultaneous local switching. Parameter Symbol Requirements Unit Input pin ¾ CIN Max 16 pF Output pin L, M, H, V type COUT Max 16 pF I/O pin L, M, H, V type CI/O Max 16 pF

Note : Consult Fujitsu for the combination of each package and the time of availability. Package Pin count Material QFP 176, 208, 240 Plastic TQFP 100, 120 Plastic LQFP 144, 176, 208, 256 Plastic HQFP 208, 240, 256, 304 Plastic PBGA 256, 352, 420 Plastic FBGA 112, 144, 168, 176, 192, 224, 240, 272, 288, 304, 368 Plastic FLGA 144, 176, 208, 224, 288 Plastic EBGA 660 Plastic

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