ICS853014 IDT | Alldatasheet
Document overview
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Technical content
Features
- Five differential LVPECL/ECL outputs
- Two selectable differential LVPECL clock inputs
- PCLKx, PCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL
- Maximum output frequency: > 2GHz
- Output skew: 13ps (typical)
- Part-to-part skew: 60ps (typical)
- Propagation delay: 460ps (typical)
- LVPECL mode operating voltage supply range: VCC = 2.375V to 3.8V, VEE = 0V
- ECL mode operating voltage supply range: VCC = 0V, VEE = -3.8V to -2.375V
- -40°C to 85°C ambient operating temperature
- Available in both standard (RoHS 5) and lead-free (RoHS 6) packages HiPerClockS™ ICS ICS853014 20-Lead TSSOP 6.5mm x 4.4mm x 0.925mm package body G Package Top View Pin AssignmentBlock Diagram EN CLK_SEL PCLK0 PCLK0 D LE Q Pulldown Pulldown Pullup/Pulldown Pulldown VBB PCLK1 PCLK1 Pulldown Pullup/Pulldown VCC EN VCC PCLK1 PCLK1 VBB PCLK0 PCLK0 CLK_SEL VEE
Table 1. Pin Descriptions NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. Table 2. Pin Characteristics 1, 2 Q0, Q0 Output Differential output pair. LVPECL/ECL interface levels. 3, 4 Q1, Q1 Output Differential output pair. LVPECL/ECL interface levels. 5, 6 Q2, Q2 Output Differential output pair. LVPECL/ECL interface levels. 7, 8 Q3, Q3 Output Differential output pair. LVPECL/ECL interface levels. 9, 10 Q4, Q4 Output Differential output pair. LVPECL/ECL interface levels. 11 V EE Power Negative supply pin. selects PCLK0/PCLK0 inputs. LVTTL / LVCMOS interface levels. 13 PCLK0 Input Pulldown Non-inverting differential LVPECL clock input.
14 PCLK0 Input Pullup/
Pulldown Inverting differential LVPECL clock input. VCC/2 default when left floating. 15 V BB Output Bias voltage. 16 PCLK1 Input Pulldown Non-inverting differential LVPECL clock input.
17 PCLK1 Input Pullup/
Pulldown Inverting differential LVPECL clock input. VCC/2 default when left floating. 18, 20 V CC Power Positive supply pins.
19 EN Input Pulldown
Synchronizing clock enable. When LOW, clock outputs follow clock input. When HIGH, Qx outputs are forced low, Qx outputs are forced high. LVTTL/LVCMOS interface levels.
After EN switches, the clock outputs are disabled or enabled following a falling input clock edge as shown in Figure 1. In the active mode, the state of the outputs are a function of the PCLK0/PCLK0 and PCLK1/PCLK1 inputs as described in Table 3B. Figure 1. EN Timing Diagram
0 Biased; NOTE 1 LOW HIGH Single-Ended to Differential Non-Inverting
1 Biased; NOTE 1 HIGH LOW Single-Ended to Differential Non-Inverting
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 4 ICS853014BG REV. DNOVEMBER 12, 2007 Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Table 4A. Power Supply DC Characteristics, VCC = 2.375V to 3.8V; VEE = 0V, TA = -40°C to 85°C Item Rating Supply Voltage, VCC 4.6V (LVPECL mode, VEE = 0V) Negative Supply Voltage, VEE -4.6V (ECL mode, VCC = 0V) Inputs, VI (LVPECL mode) -0.5V to V CC + 0.5V Inputs, VI (ECL mode) 0.5V to V EE – 0.5V Outputs, IO Continuos Current Surge Current 50mA 100mA V BB Sink//Source, IBB ± 0.5mA Operating Temperature Range, TA -40°C to +85°C Package Thermal Impedance, θJA 73.2°C/W (0 lfpm) Storage Temperature, TSTG -65°C to 150°C Symbol Parameter Test Conditions Minimum Typical Maximum Units VCC Positive Supply Voltage 2.375 3.3 3.8 V IEE Power Supply Current 85 mA
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 5 ICS853014BG REV. DNOVEMBER 12, 2007 Table 4B. DC Characteristics, VCC = 3.3V; VEE = 0V, TA = -40°C to 85°C Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCC – 2V. NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLKx, PCLKx is VCC + 0.3V .Table 4C. LVPECL DC Characteristics, VCC = 2.5V; VEE = 0V, TA = -40°C to 85°C Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCC – 2V. NOTE 2: Common mode voltage is defined as VIH. NOTE 3: For single-ended applications, the maximum input voltage for PCLKx, PCLKx is VCC + 0.3V. Symbol Parameter -40°C 25°C 80°C UnitsMin Typ Max Min Typ Max Min Typ Max VBB Output Voltage Reference; VCMR Input High Voltage Common I IH Input High Current PCLK0, PCLK1 PCLK0 , PCLK1 150 150 150 µA IIL Input Low Current PCLK0, PCLK1 -10 -10 -10 µA PCLK0, PCLK1 -150 -150 -150 µA Symbol Parameter -40°C 25°C 80°C UnitsMin Typ Max Min Typ Max Min Typ Max VCMR Input High Voltage Common IIH Input High Current PCLK0, PCLK1 PCLK0 , PCLK1 150 150 150 µA IIL Input Low Current PCLK0, PCLK1 -10 -10 -10 µA PCLK0 , PCLK1 -150 -150 -150 µA
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 6 ICS853014BG REV. DNOVEMBER 12, 2007 Table 4D. ECL DC Characteristics, VCC = 0V; VEE = -3.8V to -2.375V, TA = -40°C to 85°C Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V. NOTE 1: Outputs terminated with 50Ω to VCC – 2V. NOTE 2: Single-ended input operation is limited. VCC ≥ 3V in LVPECL mode. NOTE 3: Common mode voltage is defined as VIH. NOTE 4: For single-ended applications, the maximum input voltage for PCLKx, PCLKx is VCC + 0.3V Symbol Parameter -40°C 25°C 80°C UnitsMin Typ Max Min Typ Max Min Typ Max VIH Input High Voltage VBB Output Voltage Reference; VCMR Input High Voltage Common Mode Range; NOTE 3, 4 VEE+1.2 0 V EE+1.2 0 V EE+1.2 0 V IIH Input High Current PCLK0, PCLK1 PCLK0 , PCLK1 150 150 150 µA IIL Input Low Current PCLK0, PCLK1 -10 -10 -10 µA PCLK0, PCLK1 -150 -150 -150 µA
All parameters are measured at f ≤ 1GHz, unless otherwise noted. NOTE 1: Measured from the differential input crossing point to the differential output crossing point. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: The VCMR and VPP levels should be such that input low voltage never goes below VEE. NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 8 ICS853014BG REV. DNOVEMBER 12, 2007 Parameter Measurement Information LVPECL Output Load AC Test Circuit Part-to-Part Skew Output Rise/Fall Time Differential Input Level Output Skew Propagation Delay SCOPE Qx nQx LVPECL VEE VCC -1.8V to -0.375V tsk(pp) Part 1 Part 2 Qx Qx Qy Qy Clock Outputs 20% 80% 80% 20% tR tF VSWING VCC VEE V CMR Cross Points V PP PCLKx PCLKx tsk(o) Qx Qx Qy Qy tPD Q0:Q4 Q0:Q4 PCLKx PCLKx
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 11 ICS853014BG REV. DNOVEMBER 12, 2007 Recommendations for Unused Output Pins Inputs: PCLK/PCLK INPUTS For applications not requiring the use of a differential input, both the PCLK and PCLK pins can be left floating. Though not required, but for additional protection, a 1kW resistor can be tied from PCLK to ground. For applications LVCMOS Control Pins All control pins have internal pull-ups or pull-downs; additional resistance is not required but can be added for additional protection. A 1kΩ resistor can be used. Outputs: LVPECL Outputs All unused LVPECL outputs can be left floating. We recommend that there is no trace attached. Both sides of the differential output pair should either be left floating or terminated. Termination for 3.3V LVPECL Outputs The clock layout topology shown below is a typical termination for LVPECL outputs. The two different layouts mentioned are recommended only as guidelines. FOUT and FOUT are low impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors (DC current path to ground) or current sources must be used for functionality. These outputs are designed to drive 50Ω transmission lines. Matched impedance techniques should be used to maximize operating frequency and minimize signal distortion. Figures 4A and 4B show two different layouts which are recommended only as guidelines. Other suitable clock layouts may exist and it would be recommended that the board designers simulate to guarantee compatibility across all printed circuit and clock component process variations. Figure 4A. 3.3V LVPECL Output Termination Figure 4B. 3.3V LVPECL Output Termination VCC - 2V 50Ω 50Ω RTT Zo = 50Ω Zo = 50Ω FOUT FIN RTT = Z o 1 ((VOH + VOL) / (VCC – 2)) – 2 3.3V 125Ω 125Ω 84Ω 84Ω Zo = 50Ω Zo = 50Ω FOUT FIN
Figure 6. ICS853014 Example LVPECL Clock Output Buffer Schematic
This section provides information on power dissipation and junction temperature for the ICS853014. Equations and example calculations are also provided. The total power dissipation for the ICS853014 is the sum of the core power plus the power dissipated in the load(s). The following is the power dissipation for VCC = 3.8V, which gives worst case results. NOTE: Please refer to Section 3 for details on calculating power dissipated in the load. Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the device. The maximum recommended junction temperature for HiPerClockS devices is 125°C. and a multi-layer board, the appropriate value is 66.6°C/W per Table 6 below. of board (single layer or multi-layer). Table 6. Thermal Resistance θJA for 20 Lead TSSOP, Forced Convection
- Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load. LVPECL output driver circuit and termination are shown in Figure 7. Figure 7. LVPECL Driver Circuit and Termination Pd_H is power dissipation when the output drives high. Pd_L is the power dissipation when the output drives low.
Table 7. θJA vs. Air Flow Table for a 20 Lead TSSOP Table 8. Package Dimensions
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 17 ICS853014BG REV. DNOVEMBER 12, 2007
Ordering Information
Table 8. Ordering Information NOTE: Parts that are ordered with an “LF” suffix to the part number are the Pb-Free configuration and are RoHS compliant. product for use in life support devices or critical medical instruments.
LOW SKEW, 1-TO-5, DIFFERENTIAL-TO-2.5V, 3.3V LVPECL/ECL FANOUT BUFFER IDT™ / ICS™ 2.5V, 3.3V LVPECL/ECL FANOUT BUFFER 18 ICS853014BG REV. DNOVEMBER 12, 2007 Revision History Sheet Rev Table Page Description of Change Date B T4B T4C T4D 3.3V LVPECL table - V OH values changed @ 85° to 2.22V min. and 3.3V LVPECL table - VOH values changed @ 85° to 2.22V min. and 3.3V LVPECL table - V OH values changed @ 85° to 2.22V min. and Revised LVPECL Output Termination drawings. Revised Figure 5D. 9/10/03 C T4B - T4D 4-5 LVPECL & ECL tables - deleted V PP row. AC Table - added VPP row and changed max. value from 1200mV to 1800mV. 3/18/04 C T9 Features Section - added Lead-Free bullet. Ordering Information Table - added Lead-Free part number. 5/13/05 D 4A 4 Power Supply DC Characteristics Table - changed I EE from 75mA max. to 85mA max. Updated format throughout the datasheet. 7/6/07 d 1 Corrected block diagram. 11/12/07
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