CS8413

CS8413 ETC | Alldatasheet

Document overview

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Technical content

Features

lSample Rates to >100 kHz lLow-Jitter, On-Chip Clock Recovery 256xFs Output clock Provided lSupports: AES/EBU, IEC 958, S/PDIF, & EIAJ CP340/1201 Professional and Consumer Formats lExtensive Error Reporting Repeat Last Sample on Error Option lOn-Chip RS422 Line Receiver lConfigurable Buffer Memory (CS8413) lPin Compatible with CS8411 and CS8412

Description

The CS8413 and CS8414 are monolithic CMOS devices which receive and decode audio data up to 96kHz ac- cording to the AES/EBU, IEC958, S/PDIF, and EIAJ CP340/1201 interface standards. The CS8413 and CS8414 receive data from a transmission line, recover the clock and synchronization signals, and de-multiplex the audio and digital data. Differential or single ended in- puts can be decoded. The CS8413 has a configurable internal buffer memory, read through a parallel port, which may be used to buffer channel status, auxiliary data, and/or user data. The CS8414 de-multiplexes the channel, user, and va- lidity data directly to serial output pins with dedicated output pins for the most important channel status bits.

ORDERING INFORMATION

CS8413-CS 0° to 70° C 28-pin Plastic SOIC CS8414-CS 0° to 70° C 28-pin Plastic SOIC I SCK12 FSYNC11 SDATA26 RXP 9 RXN 10 Audio Serial Port CS24 RD/WR23 A3-A04 D7-D08Configurable Buffer Memory MCK De-MUXRS422 Receiver CS8413 IEnable and Status ERF INT 25 14 Clock and Data Recovery AGND FILT VA+ DGND VD+ SCK12 FSYNC11 SDATA26 RXP 9 RXN 10 Audio Serial Port 28Registers MCK De-MUXRS422 Receiver CS8414 MUX 22 7 Clock and Data Recovery AGND FILT VA+ DGND VD+ 1 C U VERF MUX ERF CBL 154365 Ce/Cd/Cc/Cb/Ca/C0/ F2F1F0E2E1E0 SEL CS12/ FCK

13 A4/FCK

OCT ‘98 DS240F1

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Preliminary product information describes products which are in production, but for which full characterization data is not yet available. Advance product information describes products which are in development and subject to development changes. Cirrus Logic, Inc. has made best efforts to ensure that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided “AS IS” without warranty of any kind (express or implied). No responsibility is assumed by Cirrus Logic, Inc. for the use of this information, nor for infringements of patents or other rights of third parties. This document is the property of Cirrus Logic, Inc. and implies no license under patents, copyrights, trademarks, or trade secrets. No part of this publication may be copied, reproduced, stored in a retrieval sys- tem, or transmitted, in any form or by any means (electronic, mechanical, photographic, or otherwise). Furthermore, no part of this publication may be used as a basis for manufacture or sale of any items without the prior written consent of Cirrus Logic, Inc. The names of products of Cirrus Logic, Inc. or other vendors and suppliers appearing in this document may be trademarks or service marks of their respective owners

CHARACTERISTICS/SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS (GND = 0V, all voltages with respect to ground) Notes: 1. Transient currents of up to 100 mA will not cause SCR latch-up RECOMMENDED OPERATING CONDITIONS (GND = 0V, all voltages with respect to ground) Notes: 2. The ‘-CS’ parts are specified to operate over 0 to 70 °C but are tested at 25 °C only. DIGITAL CHARACTERISTICS (TA = 25 °C; VD+, VA+ = 5V ± 5%) Notes: 3. FS is defined as the incoming audio sample frequency per channel. Parameters Symbol Min Max Units Power Supply Voltage VD+, VA+ - 6.0 V Input Current, Any Pin Except Supply (Note 1) I in -± 1 0 m A Input Voltage, Any Pin Except RXP, RXN V IN -0.3 (VD+) + 0.3 V Input Voltage, RXP and RXN V IN -12 12 V Ambient Operating Temperature (power applied) T A -55 125 °C Storage Temperature T stg -65 150 °C Parameters Symbol Min Typ Max Units Power Supply Voltage VD+, VA+ 4.75 5.0 5.25 V Supply Current VA+ VD+ I A ID mA mA Ambient Operating Temperature: (Note 2) T A 02 5 7 0° C Power Consumption P D - 175 315 mW Parameters Symbol Min Typ Max Units High-Level Input Voltage except RXP, RXN V IH 2.0 - - V Low-Level Input Voltage except RXP, RXN V IL -- + 0 . 4 V High-Level Output Voltage (I O = 200 µA) V OH (VD+) - 1.0 -- V Low-Level Output Voltage (I O = -3.2 mA) V OL -- 0 . 5 V Input Leakage Current I in -1 . 0 1 0µ A Input Sample Frequency: (Note 3) F S 28.4 - 100 kHz Master Clock Frequency (Note 3) MCK 7.28 256xF S 25.6 MHz MCK Clock Jitter t j - 200 - psRMS MCK Duty Cycle (high time/cycle time) - 50 - %

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DIGITAL CHARACTERISTICS - RS422 RECEIVERS (RXP, RXN pins only; VD+, VA+ = 5V ± 5%) Notes: 4. VCM - Input Common Mode Range 5. When the receiver inputs are configured for single ended operation (e.g. consumer configuration) the signal amplitude must exceed 400 mVp-p for the differential voltage on RXP to RXN to exceed 200 mV. This represents twice the minimum signal level of 200 mVp-p specified in CP340/1201 and IEC-958 (which are not RS-422 compliant). SWITCHING CHARACTERISTICS - CS8413 PARALLEL PORT (TA = 25 °C;VD+, VA+ = 5V ± 5%; Inputs: Logic 0 = DGND, Logic 1 = VD+; CL = 20 pF) Parameters Symbol Min Typ Max Units Input Resistance (-7V < V CM < 7V) (Note 4) Z IN -1 0- k W Differential Input Voltage, (-7V < VCM < 7V) (Notes 4 and 5) RXP to RXN VTH 200 - - mV Input Hysteresis V HYST -5 0-m V Parameters Symbol Min Typ Max Units ADDRESS valid to CS low t adcss 13.5 - - ns CS high to ADDRESS invalid t csadh 0--n s RD/WR valid to CS low t rwcss 10 - - ns CS low to RD/WR invalid t csrwi 35 - - ns CS low t csl 35 - - ns DATA valid to CS rising RD/WR low (writing) tdcssw 32 - - ns CS high to DATA invalid RD/WR low (writing) tcsdhw 0--n s CS falling to DATA valid RD/WR high (reading) tcsddr -- 3 5 n s CS rising to DATA Hi-Z RD/WR high (reading) tcsdhr 5--n s A4 - A0 D7 - D0 RD/WR Writing Reading adcsst csddrt cslt dcsswt csdhwt csdhrt csadht CS D7 - D0 RD/WR csrwitrwcsst CS8413 Parallel Port timing

SWITCHING CHARACTERISTICS - SERIAL PORTS (TA = 25 °C; VD+, VA+ = 5V ± 5%; Inputs: Logic 0 = DGND, Logic 1 = VD+; CL = 20 pF) Notes: 6. The output word rate, OWR, refers to the frequency at which an audio sample is output from the part. (A stereo pair is two audio samples.) Therefore, in Master mode, there are always 32 SCK periods in one audio sample. In Slave mode, exactly 32 SCK periods per audio sample must be provided in most serial port formats. Therefor, if SCK is 128 x Fs, then SCK must be gated to provide exactly 32 periods per audio sample. 7. In Master mode, SCK and FSYNC are outputs. In Slave mode, they are inputs. In the CS8413, control reg. 2 bit 1, MSTR, selects master. In the CS8414, formats 1, 3 and 9 are slaves. 8. The table above assumes data is output on the falling edge and latched on the rising edge. With the CS8413 the edge is selectable. The table is defined for the CS8413 with control reg. 2 bit 0, SCED, set to one, and for the CS8414 in formats 2, 3, 5, 6 and 7. For the other formats, the table and figure edges must be reversed (i.e. “rising” to “falling” and vice versa.) Parameters Symbol Min Typ Max Units SCK Frequency Master Mode (Notes 6 and 7) Slave Mode (Note 7) f sck - OWRx32 OWRx32 128 x FS Hz Hz SCK falling to FSYNC delay Master Mode (Notes 7 and 8) t sfdm -20 - 20 ns SCK Pulse Width Low Slave Mode (Note 7) t sckl 40 - - ns SCK Pulse Width High Slave Mode (Note 7) t sckh 40 - - ns SCK rising to FSYNC edge delay Slave Mode (Notes 7 and 8) tsfds 20 - - ns FSYNC edge to SCK rising setup Slave Mode (Notes 7 and 8) tfss 20 - - ns SCK falling (rising) to SDATA valid (Note 8) t ssv - - 20 ns C, U, CBL valid to FSYNC edge CS8414 (Note 8) t cuvf -1 / f sck -s MCK to FSYNC edge delay FSYNC from RXN/RXP t mfd -1 5- n s sfdst ssvt SDATA SCK FSYNC fsst MSB sckht ssvt scklt SDATA SCK FSYNC MSB (Mode 1) (Mode 3) sfdmt ssvt cuvft SDATA SCK FSYNC C, U Serial Output Timing - Slave Mode Serial Output Timing - Master Mode & C, U Port FSYNC Generated From Received Data FSYNC mfdt MCK fsstsfdst sckhtscklt SCK (Modes 2,3,5,6, 7,10,12, and 13) (Modes 0,1,4, 8,9, and 11)

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Figure 1. CS8413 Typical Connection Diagram

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Figure 2. CS8414 Typical Connection Diagram

The CS8413/14 are monolithic CMOS circuits that receive and decode audio and digital data accord- ing to the AES/EBU, IEC 958, S/PDIF, and EIAJ CP340/1201 interface standards. Both chips con- tain RS422 line receivers and Phase-Locked Loops (PLL) that recover the clock and synchronization signals, and de-multiplex the audio and digital data. The CS8413 contains a configurable internal buffer memory, read via a parallel port, which can buffer channel status, user, and optionally auxiliary data. The CS8414 de-multiplexes the channel status, us- er, and validity information directly to serial output pins with dedicated pins for the most important channel status bits. Both chips also contain exten- sive error reporting as well as incoming sample fre- quency indication for auto-set applications. The CS8413/14 are pin-compatible with the CS8411/12 digital audio receiver parts. The func- tionality of the CS8413/14 is the same as the CS8411/12 with two exceptions: first, the operat- ing frequency (sample rate) of the CS8413/14 is ex- tended to include 96 kHz, and second, the frequency reporting bits are modified to delete the ±400 ppm ranges, and include 88.2 kHz and 96 kHz ranges. Familiarity with the AES/EBU and IEC 958 speci- fications are assumed throughout this document. The App Note, Overview of Digital Audio Inter- face Data Structures, contains information on digi- tal audio specifications; however, it is not meant to be a complete reference. To guarantee compliance, the proper standards documents should be ob- tained. The AES/EBU standard, AES3-1985, should be obtained from the Audio Engineering Society or ANSI (ANSI document # ANSI S4.40- 1985); the IEC 958 standard from the International Electrotechnical Commission; and the EIAJ CP340/1201 standard from the Japanese Electron- ics Bureau. Line Receiver The RS422 line receiver can decode differential as well as single ended inputs. The receiver consists of a differential input Schmitt trigger with 50mV of hysteresis. The hysteresis prevents noisy signals from corrupting the phase detector. Appendix A contains more information on how to configure the line receivers for differential and single ended sig- nals. Clocks and Jitter Attenuation The primary function of these chips is to recover audio data and low jitter clocks from a digital audio transmission line. The clocks that can be generated are MCK (256xF S), SCK (64xFS), and FSYNC (FS or 2xFS). MCK is the output of the voltage con- trolled oscillator which is a component of the PLL. The PLL consists of phase and frequency detectors, a second-order loop filter, and a voltage controlled oscillator. All components of the PLL are on chip with the exception of a resistor and capacitor used in the loop filter. This filter is connected between the FILT pin and AGND. The typical closed-loop transfer function, which specifies the PLL’s jitter attenuation characteristics, is shown in Figure 3. Most jitter introduced by the transmission line is high in frequency and will be strongly attenuated. Multiple frequency detectors are used to minimize the time it takes the PLL to lock to the incoming data stream and to prevent false lock conditions. When the PLL is not locked to the incoming data stream, the frequency detectors pull the VCO fre- quency within the lock range of the PLL. When no digital audio data is present, the VCO frequency is pulled to its minimum value. As a master, SCK is always MCK divided by four, producing a frequency of 64xF S. In the CS8413, FSYNC can be programmed to be a divided version of MCK or it can be generated directly from the in- coming data stream. In the CS8414, FSYNC is al- ways generated from the incoming data stream. When FSYNC is generated from the data, its edges

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MCK instead of from the incoming data. a microprocessor or DSP is not available. Characteristics - Parallel Port table. modes selectable by two bits in control register 1. found in the Control Registers section. Figure 3. Typical Jitter Attenuation Characteristics

to make the IEnable registers visible. FLAG2 causes an interrupt on the rising edge only. can be found in the Buffer Memory section.

2 X 8

28 X 8

4 X 8

Figure 4. CS8413 Block Diagram

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mode (FSYNC and SCK are inputs to the CS8413). indicates that a CRC error occurred in that channel.

20 Bytes

Figure 5. CS8413 Buffer Memory Map CRC2: CRC Error - sub-frame 2. Buffer mode 2 only. CRC1: CRC Error - sub-frame 1. Buffer mode 2 only. ERF: Error Flag. ORing of all errors in SR2. FLAG1: Memory mode dependent - See Figure 11. FLAG0: High for last two bytes of user data. IER1: Enables the corresponding bit in SR1. A “1” enables the interrupt. A “0” masks the interrupt. Figure 6. Status/IEnable Register 1 CRC2: CRC Error - sub-frame 2. Buffer mode 2 only. CRC1: CRC Error - sub-frame 1. Buffer mode 2 only. ERF: Error Flag. ORing of all errors in SR2. FLAG1: Memory mode dependent - See Figure 11. FLAG0: High for last two bytes of user data. IER1: Enables the corresponding bit in SR1. A “1” enables the interrupt. A “0” masks the interrupt.

rupt once if SR1 is not read. Table 1. Incoming Sample Frequency Bits 3, configures the audio serial port. SR2: FREQ2: The 3 FREQ bits indicate incoming sample frequency. IER2: TEST1,0: (0 on power-up) Must stay at “0”. INT. ENABLES: Enables the corresponding bit in SR2. A “1” enables the interrupt. A “0” masks the interrupt. Figure 7. Status/IEnable Register 2

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must be connected to the FCK pin as a reference. consists of three pins: SCK, SDATA, and FSYNC. other, and the polarity of SCK can be controlled. between FSYNC edges will vary.

011 A u x i l i a r y D a t a

113 R e s e r v e d

Table 2. Buffer Memory Modes FCEN: enables freq. comparator (FCK must be 6.144 MHz). : [X:00,01] 0 - status, 1 - interrupt enable registers. CS2/CS1 : ch. status to buffer; 0 - sub-frame 1, 1 - sub-frame 2. B1: with B0, selects the buffer memory mode. B0: with B1, selects the buffer memory mode. : Resets internal counters. Set to “1” for normal operation. Figure 8. Control Register 1 SDF2: with SDF0 & SDF1, select serial data format. SDF1: with SDF0 & SDF2, select serial data format. SDF0: with SDF1 & SDF2, select serial data format. FSF1: with FSF0, select FSYNC format. FSF0: with FSF1, select FSYNC format. SCED: When set, falling edge of SCK outputs data. When clear, rising edge of SCK outputs data. Figure 9. Control Register 2

modes selectable by SDF2-SDF0 and FSF1-FSF0.

16 Clocks 16 Clocks

32 Clocks

32 Clocks 32 Clocks

000 MSB First - 32

20 Bits

16 Bits

18 Bits

32 Bits 32 Bits

16 Bits16 Bits

210 MSTR Name

100 Async SCK0

Figure 10. CS8413 Serial Port SDATA and FSYNC Timing

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The audio serial port outputs the audio data portion from the received data and consists of three pins: SCK, SDATA, and FSYNC. SCK clocks the data out on the SDATA line. The edge that SCK uses to output data is programmable from CR2. FSYNC delineates the audio samples and may indicate the particular channel, left or right. Figure 10 illus- trates the multitude of formats that SDATA and FSYNC can take. Normal Modes SCK and FSYNC can be inputs (MSTR = 0) or out- puts (MSTR = 1), and are usually programmed as outputs. As outputs, SCK contains 32 periods for each sample and FSYNC has four formats. The first two output formats of FSYNC (shown in Fig- ure 10) delineate each word and the identification of the particular channel must be kept track of ex- ternally. This may be done using the rising edge of FLAG2 to indicate the next data word is left chan- nel data. The last two output formats of FSYNC also delineate each channel with the polarity of FSYNC indicating the particular channel. The last format has FSYNC change one SCK cycle before the frame containing the data and may be used to generate an I 2S compatible interface. When SCK is programmed as an input, 32 SCK cy- cles per sample must be provided. (There are two formats in the Special Modes section where SCK can have 16 or 24 clocks per sample.) The four modes where FSYNC is an input are similar to the FSYNC output modes. The first two require a tran- sition of FSYNC to start the sample frame, whereas the last two are identical to the corresponding FSYNC output modes. If the circuit generating SCK and FSYNC is not locked to the master clock of the CS8413, the serial port will eventually be re- read or a sample will be missed. When this occurs, the SLIP bit in SR1 will be set. SDATA can take on five formats in the normal se- rial port modes. The first format (see Figure 10), MSB First, has the MSB aligned with the start of a sample frame. Twenty-four audio bits are output including the auxiliary bits. This mode is compati- ble with many DSPs. If the auxiliary bits are used for something other than audio data, they must be masked off. The second format, MSB Last, outputs data LSB first with the MSB aligned to the end of the sample frame. This format is conducive to seri- al arithmetic. Both of the above formats output all audio bits from the received data. The last three for- mats are LSB Last formats that output the most sig- nificant 16, 18, and 20 bits respectively, with the LSB aligned to the end of the sample frame. These formats are used by many interpolation filters. Special Modes Five special modes are included for unique applica- tions. In these modes, the master bit, MSTR, must be defined as shown in Figure 10. In the first mode, Asynchronous SCK, FSYNC (which is an output in this mode) is aligned to the incoming SCK. This mode is useful when the SCK is locked to an exter- nal event and cannot be derived from MCK. Since SCK is asynchronous, the number of SCK cycles per sample frame will vary. The data output will be MSB first, 24 bits, and aligned to the beginning of a sample frame. The second and third special modes are unique in that they contain 24 and 16 SCK cycles respectively per sample frame, where- as all normal modes contain 32 SCK cycles. In these two modes, the data is MSB first and fills the entire frame. The fourth special mode outputs NRZ data including the V, U, C, and P bits and the pre- amble replaced with zeros. SCK is an output with 32 SCK cycles per sample frame. The fifth mode outputs the biphase data recovered from the trans- mission line with 64 SCK cycles output per sample frame, with data changing on the rising edge. Normally, data recovered by the CS8413 is delayed by two frames in propagating through the part, but

in the fourth and fifth special modes, the data is de- layed only a few bit periods before being output. However, error codes, and the C, U and V bits fol- low the normal pathway with a two frame delay (so that the error code would be output with the offend- ing data in the other modes). As a result, in special modes four and five, the error codes are nearly two frames behind the data output on SDATA. Buffer Memory In all buffer modes, the status, mask, and control registers are located at addresses 0-3, and the user data is buffered at locations 4 through 7. The paral- lel port can access any location in the user data buffer at any time; however, care should be taken not to read a location when that location is being updated internally. This internal writing is done through a second port of the buffer and is done in a cyclic manner. As data is received, the bits are as- sembled in an internal 8-bit shift register which, when full, is loaded into the buffer memory. The first bit received is stored in D0 and, after D7 is re- ceived, the byte is written into the proper buffer memory location. The user data is received one bit per sub-frame. At the channel status block boundary, the internal pointer for writing user data is initialized to 04H (Hex). After receiving eight user bits, the byte is written to the address indicated by the user pointer which is then incremented to point to the next ad- dress. After receiving all four bytes of user data, 32 audio samples, the user pointer is set to 04H again and the cycle repeats. FLAG0, in SR1 can be used to monitor the user data buffer. When the last byte of the user buffer, location 07H, is written, FLAG0 is set low and when the second byte, location 05H, is written, FLAG0 is set high. If the corresponding bit in the interrupt enable register (IER1, bit 0) is set, a transition of FLAG0 will generate a low pulse on the interrupt pin. The level of FLAG0 indicates which two bytes the part will write next, thereby in- dicating which two bytes are free to be read. FLAG1 is buffer mode dependent and is discussed in the individual buffer mode sections. A transition of FLAG1 will generate an interrupt if the appro- priate interrupt enable bit is set. FLAG2 is set high after channel status byte 23, the last byte of the block, is written and set low after channel status byte 3 is written to the buffer mem- ory. FLAG2 is unique in that only the rising edge can cause an interrupt if the appropriate interrupt enable bit in IER1 is set. Figure 11 illustrates the flag timing for an entire channel status block which includes 24 bytes of channel status data per channel and 384 audio sam- ples. The lower portion of Figure 11 expands the first byte of channel status showing eight pairs of data, with a pair defined as a frame. This is further expanded showing the first sub-frame (A0) to con- tain 32 bits defined as per the digital audio stan- dards. When receiving stereo, channel A is left and channel B is right. For all three buffer modes, the three most signifi- cant bits in SR1, shown in Figure 6, can be used to monitor the channel status data. In buffer mode 2, bits 7 and 6 change definition and are described in that section. Channel status data, as described in the standards, is independent for each channel. Each channel contains its own block of channel status data, and in most systems, both channels will con- tain the same channel status data. Buffer modes 0 and 1 operate on one block of channel status with the particular block selected by the CS2/CS1 bit in CR1. CSDIF, bit 7 in SR1, indicates when the channel status data for each channel is not the same even though only one channel is being buffered. CRCE, bit 6 in SR1, indicates a CRC error oc- curred in the buffered channel. CCHG, bit 5 in SR1, is set when any bit in the buffered channel sta- tus bytes 0 to 3, change from one block to the next.

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channel status data is independent for each channel. tus data for each channel would be identical. Figure 11. CS8413 Status Register Flag Timing

expanded portion of the figure for clarity. not used (except for byte 23, CRC). allowing FLAG0 to be used to monitor both. Figure 12. CS8413 Buffer Memory Write Sequence - MODE 0

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scribed in the BUFFER MODE 1 section. Figure 13. CS8413 Buffer Memory Write Sequence - MODE 1 Figure 14. CS8413 Buffer Memory Write Sequence - MODE 2

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indicating that the audio output may not be valid. CS8414 is illustrated in Figure 16. CS8413 sections in the beginning of this data sheet. Figure 16. CS8414 Block Diagram

Table 3. Normal Audio Port Modes (M3 = 0) may be useful when writing data to storage. Table 4. Special Audio Port Modes (M3 = 1)

1. However, the C, U, V bits and error codes fol-

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18 Bits18 Bits

16 Bits 16 Bits

Figure 17. CS8414 Audio Serial Port Formats

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channel status information, selectable by SEL. the last clearing will be selected. Table 5. Error Decoding PLL is not locked onto the incoming data stream. two thirds of a block for the ‘F’ pins to be accurate. Table 6. Sample Frequency Decoding

000 N o E r r o r

101 P a r i t y E r r o r

mation reported is shown in Table 7. Table 7. Channel Status Pins coded versions of channel status bits 2, 3, and 4. indicate not to update the display. Table 8. Emphasis Encoding data has had pre-emphasis added.

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tection asserted) and the L bit to 1 (original). To support this feature, Ce, in the consumer mode, is defined as IGCAT (ignorant category) which is low for the “general” (0000000) and “A/D converter without copyright information” (01100xx) catego- ries.

PIN DESCRIPTIONS: CS8413 Power Supply Connections VD+ - Positive Digital Power, PIN 7. Positive supply for the digital section. Nominally +5 volts. V A+ - Positive Analog Power, PIN 22. Positive supply for the analog section. Nominally +5 volts. This supply should be as quiet as possible since noise on this pin will directly affect the jitter performance of the recovered clock. DGND - Digital Ground, PIN 8. Ground for the digital section. DGND should be connected to same ground as AGND. AGND - Analog Ground, PIN 21. Ground for the analog section. AGND should be connected to same ground as DGND. D2 D1DATA BUS BIT 2 DATA BUS BIT 1 D3 D0DATA BUS BIT 3 DATA BUS BIT 0 D4 SDATADATA BUS BIT 4 SERIAL OUTPUT DATA D5 ERFDATA BUS BIT 5 ERROR FLAG D6 CSDATA BUS BIT 6 CHIP SELECT D7 RD/WRDATA BUS BIT 7 READ/WRITE SELECT VD+ VA+DIGITAL POWER ANALOG POWER DGND AGNDDIGITAL GROUND ANALOG GROUND RXP FILTRECEIVE POSITIVE FILTER RXN MCKRECEIVE NEGATIVE MASTER CLOCK FSYNC A0FRAME SYNC ADDRESS BUS BIT 0 SCK A1SERIAL DATA CLOCK ADDRESS BUS BIT 1 A4/FCK A2ADDRESS BUS BIT 4/FCLOCK ADDRESS BUS BIT 2 INT A3INTERRUPT ADDRESS BUS BIT 3 CS8413

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SCK - Serial Clock, PIN 12. Serial clock for SDATA pin which can be configured (via control register 2) as an input or output, and can sample data on the rising or falling edge. As an input, SCK must contain 32 clocks for every audio sample in all normal audio serial port formats. FSYNC - Frame Sync, PIN 11. Delineates the serial data and may indicate the particular channel, left or right. Also, FSYNC may be configured as an input or output. The format is based on bits in control register 2. SDATA - Serial Data, PIN 26. Audio data serial output pin. ERF - Error Flag, PIN 25. Signals that an error has occurred while receiving the audio sample currently being read from the serial port. The errors that cause ERF to go high are enumerated in status register 2 and enabled by setting the corresponding bit in IEnable register 2. A4/FCK - Address Bus Bit 4/Frequency Clock, PIN 13. This pin has a dual function and is controlled by the FCEN bit in control register 1. A4 is the address bus pin as defined below. When used as FCK, an internal frequency comparator compares a 6.144 MHz clock input on this pin to the received clock frequency and stores the value in status register 1 as three FREQ bits. These bits indicate the incoming frequency. When defined as FCK, A4 is internally set to 0. Parallel Interface CS - Chip Select, PIN 24. This input is active low and allows access to the 32 bytes of internal memory. The address bus and RD/WR must be valid while CS is low. RD/WR - Read/Write, PIN 23. If RD/WR is low when CS goes active (low), the data on the data bus is written to internal memory. If RD/WR is high when CS goes active, the data in the internal memory is placed on the data bus. A4-A0 - Address Bus, PINS 13, 15-18. Parallel port address bus that selects the internal memory location to be read from or written to. Note that A4 is the dual function pin A4/FCK as described above. D0-D7 - Data Bus, PINS 27-28, 1-6. Parallel port data bus used to check status, read or write control words, or read internal buffer memory.

INT - Interrupt, PIN 14. Open drain output that can signal the state of the internal buffer memory as well as error information. A 5kW resistor to VD+ is typically used to support logic gates. All bits affecting INT are maskable to allow total control over the interrupt mechanism. Receiver Interface RXP, RXN - Differential Line Receivers, PINS 9, 10. RS422 compatible line receivers. Described in detail in Appendix A. Phase Locked Loop MCK - Master Clock, PIN 19. Low jitter clock output of 256 times the received sample frequency. FILT - Filter, PIN 20. An external 470W resistor and 0.068µF capacitor are required from the FILT pin to analog ground.

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PIN DESCRIPTIONS: CS8414 Power Supply Connections VD+ - Positive Digital Power, PIN 7. Positive supply for the digital section. Nominally +5 volts. V A+ - Positive Analog Power, PIN 22. Positive supply for the analog section. Nominally +5 volts. DGND - Digital Ground, PIN 8. Ground for the digital section. DGND should be connected to same ground as AGND. AGND - Analog Ground, PIN 21. Ground for the analog section. AGND should be connected to same ground as DGND. CV E R FCHANNEL STATUS OUTPUT VALIDITY + ERROR FLAG Cd/F1 Ce/F2CS d/FREQ REPORT 1 CS e/FREQ REPORT 2 Cc/F0 SDATACS c/FREQ REPORT 0 SERIAL OUTPUT DATA Cb/E2 ERFCS b/ERROR CONDITION 2 ERROR FLAG Ca/E1 M1CS a/ERROR CONDITION 1 SERIAL PORT MODE SELECT 1 C0/E0 M0CS 0/ERROR CONDITION 0 SERIAL PORT MODE SELECT 0 VD+ VA+DIGITAL POWER ANALOG POWER DGND AGNDDIGITAL GROUND ANALOG GROUND RXP FILTRECEIVE POSITIVE FILTER RXN MCKRECEIVE NEGATIVE MASTER CLOCK FSYNC M2FRAME SYNC SERIAL PORT MODE SELECT 2 SCK M3SERIAL DATA CLOCK SERIAL PORT MODE SELECT 3 CS12/FCK SELCHANNEL SELECT/FCLOCK FREQ/CS SELECT U CBLUSER DATA OUTPUT CS BLOCK START CS8414

SCK - Serial Clock, PIN 12. Serial clock for SDATA pin which can be configured (via the M0, M1, M2, and M3 pins) as an input or output, and can sample data on the rising or falling edge. As an output, SCK will generate 32 clocks for every audio sample. As an input, 32 SCK periods per audio sample must be provided in all normal modes. FSYNC - Frame Sync, PIN 11. Delineates the serial data and may indicate the particular channel, left or right, and may be an input or output. The format is based on M0, M1, M2, and M3 pins. SDATA - Serial Data, PIN 26. Audio data serial output pin. M0, M1, M2, M3 - Serial Port Mode Select, PINS 23, 24, 18, 17. Selects the format of FSYNC and the sample edge of SCK with respect to SDATA. M3 selects between eight normal modes (M3 = 0), and six special modes (M3 = 1). Control Pins VERF - Validity + Error Flag, PIN 28. A logical OR’ing of the validity bit from the received data and the error flag. May be used by interpolation filters to interpolate through errors. U - User Bit, PIN 14. Received user bit serial output port. FSYNC may be used to latch this bit externally. (Except in I2S modes when this pin is updated on the active edge of FSYNC.) C - Channel Status Output, PIN 1. Received channel status bit serial output port. FSYNC may be used to latch this bit externally. (Except in I2S modes when this pin is updated on the active edge of FSYNC.) CBL - Channel Status Block Start, PIN 15. The channel status block output is high for the first four bytes of channel status and low for the last 20 bytes. SEL - Select, PIN 16. Control pin that selects either channel status information (SEL = 1) or error and frequency information (SEL = 0) to be displayed on six of the following pins.

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C0 , Ca, Cb, Cc, Cd, Ce - Channel Status Output Bits, PINS 2-6, 27. These pins are dual function with the ‘C’ bits selected when SEL is high. Channel status information is displayed for the channel selected by CS12. C0, which is channel status bit 0, defines professional (C0 = 0) or consumer (C0 = 1) mode and further controls the definition of the Ca-Ce pins. These pins are updated with the rising edge of CBL. CS12 - Channel Select, PIN 13. This pin is also dual function and is selected by bringing SEL high. CS12 selects sub-frame 1 (when low) or sub-frame 2 (when high) to be displayed by channel status pins C0 and Ca through Ce. FCK - Frequency Clock, PIN 13. Frequency Clock input that is enabled by bringing SEL low. FCK is compared to the received clock frequency with the value displayed on F2 through F0. Nominal input value is 6.144 MHz. E0, E1, E2 - Error Condition, PINS 4-6. Encoded error information that is enabled by bringing SEL low. The error codes are prioritized and latched so that the error code displayed is the highest level of error since the last clearing of the error pins. Clearing is accomplished by bring SEL high for more than 8 MCK cycles. F0, F1, F2 - Frequency Reporting Bits, PINS 2-3, 27. Encoded sample frequency information that is enabled by bringing SEL low. A proper clock on FCK must be input for at least two thirds of a channel status block for these pins to be valid. They are updated three times per block, starting at the block boundary. These pins are invalid when the PLL is out of lock. ERF - Error Flag, PIN 25. Signals that an error has occurred while receiving the audio sample currently being read from the serial port. Three errors cause ERF to go high: a parity or biphase coding violation during the current sample, or an out of lock PLL receiver. Receiver Interface RXP, RXN - Differential Line Receivers, PINS 9, 10. RS422 compatible line receivers. Phase Locked Loop MCK - Master Clock, PIN 19. Low jitter clock output of 256 times the received sample frequency. FILT - Filter, PIN 20. An external 470W resistor and 0.068µF capacitor is required from FILT pin to analog ground.

28L SOIC (300 MIL BODY) PACKAGE DRAWING D HE b A c L µSEATING PLANE e INCHES MILLIMETERS DIM MIN MAX MIN MAX A 0.093 0.104 2.35 2.65 A1 0.004 0.012 0.10 0.30 B 0.013 0.020 0.33 0.51 C 0.009 0.013 0.23 0.32 D 0.697 0.713 17.70 18.10 E 0.291 0.299 7.40 7.60 e 0.040 0.060 1.02 1.52 H 0.394 0.419 10.00 10.65 L 0.016 0.050 0.40 1.27 µ 0° 8° 0° 8°

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Grounding the shield of the cable is a tricky issue. with different ground potentials are connected. pended upon to make that electrical connection. Figure 20. RS422 Receiver Internal Circuit Figure 21. Professional Input Circuit Figure 22. Transformerless Professional Circuit

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Figure 25. CS8414 Reset Circuit

• Notes •