CS8402A

CS8401 ETC | Alldatasheet

Document overview

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Technical content

Features

• • Monolithic Digital Audio Interface Transmitter
• • Supports: AES/EBU, IEC 958, S/PDIF, & EIAJ CP-340 Professional and Consumer Formats
• • Host Mode and Stand Alone Modes
• • Generates CRC Codes and Parity Bits
• • On-Chip RS422 Line Driver
• • Configurable Buffer Memory (CS8401A)
• • Transparent Mode Allows Direct Connection of CS8402A and CS8412 or CS8401A and CS8411A General Description The CS8401/2A are monolithic CMOS devices which encode and transmit audio data according to the AES/EBU, IEC 958, S/PDIF, & EIAJ CP-340 interface standards. The CS8401/2A accept audio and digital data, which is then multiplexed, encoded and driven onto a cable. The audio serial port is double buffered and capable of supporting a wide variety of formats. The CS8401A has a configurable internal buffer mem- ory, loaded via a parallel port, which may be used to buffer channel status, auxiliary data, and/or user data. The CS8402A multiplexes the channel, user, and valid- ity data directly from serial input pins with dedicated input pins for the most important channel status bits. ORDERING INFORMATION: page 30 TABLE OF CONTENTS: page 31 NOV ’93 DS60F1 Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 (512) 445-7222 FAX: (512) 445-7581 Digital Audio Interface Transmitter Semiconductor Corporation Serial Port MUX RS422 Driver FSYNC SCK SDATA A4 - A0 D7- D0 TXP TXN CS8401A CS8402A MCK INT Memory Buffer Configurable Audio RD/WR CS Prescaler MUX RS422 Driver Serial Port MCK RSTM0M1M2 FSYNC SCK SDATA C U V 212223 5 16 Dedicated Channel TXP TXN CBL Audio Registers Status Bits 15 24 TRNPT CS8401A CS8402A

Specifications are subject to change without notice. ABSOLUTE MAXIMUM RATINGS (GND = 0V, all voltages with respect to ground.) Parameter Symbol Min Max Units DC Power Supply VD+ 6.0 V Input Current, Any Pin Except Supply Note 1 I in - ±10 mA Digital Input Voltage V IND -0.3 VD+ V Ambient Operating Temperature (power applied) T A -55 125 °C Storage Temperature T stg -65 150 °C Notes: 1. Transient currents of up to 100 mA will not cause SCR latch-up. WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. RECOMMENDED OPERATING CONDITIONS (GND = 0V; all voltages with respect to ground) Parameter Symbol Min Typ Max Units DC Voltage VD+ 4.5 5.0 5.5 V Supply Current Note 2 I DD 1.5 5 mA Ambient Operating Temperature: CS8401/2A-CP or -CS Note 3 TA 02 5 7 0 °C CS8401/2A-IP or -IS -40 85 °C Power Consumption Note 2 P D 7.5 25 mW Notes: 2. Drivers open (unloaded). The majority of power is used in the load connected to the drivers. 3. The ’-CP’ and ’-CS’ parts are specified to operate over 0 to 70 °C but are tested at 25 °C only. The ’-IP’ and ’-IS’ parts are tested over the full -40 to 85 °C temperature range. DIGITAL CHARACTERISTICS (TA = 25 °C for suffixes ’CP’ & ’CS’, TA = -40 to 85 °C for ’IP’ & ’IS’; VD+ = 5V ± 10%) Parameter Symbol Min Typ Max Units High-Level Input Voltage V IH 2.0 V DD +0.3 V Low-Level Input Voltage V IL -0.3 +0.8 V High-Level Output Voltage (I O = 200µA) V OH VDD -1.0 V Low-Level Output Voltage (I O = 3.2mA) V OL 0.4 V Input Leakage Current I in 1.0 10 µA Master Clock Frequency: CS8401A Note 4 MCK 22 MHz CS8402A Note 4 7.1 MHz Master Clock Duty Cycle CS8401/2A 40 60 % Notes: 4. MCK for the CS8401 must be 128, 192, 256, or 384× the input word rate based on M0 and M1 in control register 2. MCK for the CS8402A must be 128 × the input word rate, except in Transparent Mode where MCK is 256x the input word rate. CS8401A CS8402A

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SWITCHING CHARACTERISTICS - CS8401A PARALLEL PORT (TA = 25 °C for suffixes ’-CP’ and ’-CS’; TA = -40 to 85 °C for suffixes ’-IP’ and ’-IS’) Parameter Symbol Min Typ Max Units ADDRESS valid to CS low t adcss 13.5 ns CS high to ADDRESS invalid t csadh 0n s RD/WR valid to CS low t rwcss 10 ns CS low to RD/WR invalid t csrwi 35 ns CS low t csl 35 ns DATA valid to CS rising RD/ WR low (writing) t dcssw 32 ns CS high to DATA invalid RD/ WR low (writing) t csdhw 0n s CS falling to DATA valid RD/ WR high (reading) t csddr 35 ns CS rising to DATA Hi-Z RD/ WR high (reading) t csdhr 5n s A4 - A0 D7 - D0 RD/WR Writing Reading adcsst csddrt cslt dcsswt csdhwt csdhrt csadht CS D7 - D0 RD/WR csrwitrwcsst CS8401A Parallel Port Timing DIGITAL CHARACTERISTICS - RS422 DRIVERS (TXP, TXN pins only; VD+ = 5V ±10%) Parameter Symbol Min Typ Max Units Output High Voltage I OH = -30 mA V OH VD+- 0.7 VD+ - 0.4 V Output Low Voltage I OL = 30 mA V OL 0.4 0.7 V CS8401A CS8402A DS60F1 3

SWITCHING CHARACTERISTICS - SERIAL PORTS (TA = 25 °C for suffixes ’-CP’ and ’-CS’; TA = -40 to 85 °C for suffixes ’-IP’ and ’-IS’; Inputs: Logic 0 = GND, logic 1 = VD+; CL = 20 pF) Parameter Symbol Min Typ Max Units SCK Frequency Master Mode Notes 5,6 t sckf IWR ×64 Hz Slave Mode Note 6 12.5 MHz SCK Pulse Width Low Slave Mode Note 6 t sckl 25 ns SCK Pulse Width High Slave Mode Note 6 t sckh 25 ns SCK rising to FSYNC edge delay Notes 6,7 t sfds 20 ns SCK rising to FSYNC edge setup Notes 6,7 t sfs 20 ns SDATA valid to SCK rising setup Note 7 t sss 20 ns SCK rising to SDATA hold time Note 7 t ssh 20 ns C, U, V valid to SCK rising setup CS8402A non-CD Mode Notes, 7,8 t css 0n s SCK rising to C, U, V hold time CS8402A non-CD mode Notes 7, 8 t scs 50 ns U valid to SBC rising setup CS8402A, CD mode Note 8 t uss 0n s SBC rising to U hold time CS8402A, CD mode Note 8 t suh 80 ns RST Pulse Width CS8402A 150 ns Notes: 5. The input word rate, IWR, refers to the frequency at which stereo audio input samples are input to the part. (A stereo pair is two audio samples.) Therefore, in Master mode, there are always 32 SCK periods in one audio sample. 6. Master mode is defined as SCK and FSYNC being outputs. In Slave mode they are inputs. In the CS8401A, control reg. 3 bit 1, MSTR, selects master. In the CS8402A, only format 0 is master. 7. The table above assumes data is output on the falling edge and latched on the rising edge. In both parts the edge is selectable. The table is defined for the CS8401A with control reg. 3 bit 0, SCED, set to one, and for the CS8402A in formats 4 through 7. For the other formats, the table and figure edges must be reversed (ie. "rising" to "falling" and vice versa). 8. The diagrams show SBC rising coincident with the first rising edge of SCK after FSYNC transitions. This is true for all modes except FSF0 & 1 both equal 1 in the CS8401A, and format 4 in the CS8402A. In these modes SBC is delayed one full SCK period. sckht sfst sfdst ssst ssht scklt SDATA SCK FSYNC Serial Input Timing - Slave Mode CS8401A CS8402A

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7 FSYNC

16 RD/WR

15 INT

Figure 1. CS8401A Typical Connection Diagram

15 CBL

Figure 2. CS8402A Professional & Consumer Modes Typical Connection Diagram

10 SBF

Figure 3. Consumer CD Submode Typical Connection Diagram

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The CS8401A/2A are monolithic CMOS circuits that encode and transmit audio and digital data according to the AES/EBU, IEC 958 (S/PDIF), and EIAJ CP-340 interface standards. Both chips accept audio and control data separately; multi- plex and biphase-mark encode the data internally; and drive it, directly or through a transformer, to a transmission line. The CS8401A is fully software programmable through a paral- lel port and contains buffer memory for control data, while the CS8402A has dedicated pins for the most important control bits and a serial input port for the C, U, and V bits. Familiarity with the AES/EBU and IEC 958 specifications are assumed throughout this data sheet. Many terms such as channel status, user data, auxiliary data, professional mode, etc. are not defined. The Application Note, Overview of AES/EBU Digital Audio Interface Data Struc- tures, provides an overview of the AES/EBU and IEC 958 specifications and is included for clar- ity; however, it is not meant to be a complete reference, and the complete standards should be obtained from the Audio Engineering Society or ANSI for the AES/EBU document, and the Inter- national Electrotechnical Commission for the IEC document. Line Drivers The RS422 line drivers for both the CS8401A and CS8402A are low skew, low impedance, dif- ferential outputs capable of driving 110 Ω transmission lines with a 4 volt peak-to-peak sig- nal when configured as shown in Appendix A. To prevent possible short circuits, both drivers are set to ground when no master clock (MCK) is provided. They can also be disabled by reset- ting the device (RST = low). Appendix A contains more information on the line drivers. A 0.1 µF capacitor, with short leads, should be placed as close as possible to the VD+ and GND pins. CS8401A DESCRIPTION The CS8401A accepts 16- to 24-bit audio samples through a configurable serial port, and channel status, user, and auxiliary data through an 8-bit parallel port. The parallel port allows access to 32 bytes of internal memory which is used to store control information and buffer channel status, user, and auxiliary data. This data is multiplexed with the audio data from the serial port, the parity bit is generated, and the bit stream is biphase-mark encoded and driven through an RS422 line driver. A block diagram of the CS8401A is shown in Figure 4. In accordance with the professional definition of channel status, the CRCC code (C.S. byte 23) can be internally gener- ated. Parallel Port The parallel port accesses one status register, three control registers, and 28 bytes of dual port buffer memory. The address bus, and RD/WR line must be valid when CS goes low. If RD/WR is low, the value on the data bus will be written into the buffer mem- ory at the specified address. If RD/WR is high, the value in the buffer memory, at the specified address, is placed on the data bus. The detailed timing for reading and writing the CS8401A can be found in the Digital Switching Characteristics table. The memory space is allocated as shown in Figure 5. There are three defined buffer memory modes select- able by two bits in control register 2. Status and Control Registers Upon power up the CS8401A control registers contain all zeros. Therefore, the part is initially in reset and is muted. One’s must be written to control register 2, bits RST and MUTE, before the part will transmit data. The remaining regis- ters are not initialized on power-up and may contain random data. The first register, shown in Figure 6, is the status register in which only three bits are valid. The lower three bits contain flags indicating the position of the transmit pointer in the buffer memory. These flags CS8401A CS8402A DS60F1 7

Figure 4. CS8401A Block Diagram

4 X 8

28 X 8

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audio signal is suitable for conversion to analog. in Figure 5 and the bit combinations in Table 2. B1: with B0, selects the buffer memory mode. V: Validity bit of current sample. B0: with B1, selects the buffer memory mode. M1: with M0, selects MCK frequency. M0: with M1, selects MCK frequency. CRCE: Channel status CRC Enable. Professional mode only. MUTE: When clear, transmitted audio data is set to zero. RST: When clear, drivers are disabled, frame counters cleared. Figure 8. Control Register 2 MASK1: Interrupt mask for FLAG1. MASK2: Interrupt mask for FLAG2. A "1" enables the interrupt. MASK0: Interrupt mask for FLAG0. BKST: Causes realignment of data block when set to "1". Figure 7. Control Register 1 FLAG0: High for last two bytes of user data. Figure 6. Status Register

20 Bytes

Figure 5. CS8401A Buffer Memory Modes Table 1. MCLK Frequencies Table 2. Buffer Memory Modes

RST and MUTE are set to zero upon power up. two formats also indicate the specific channel. are inputs, MSTR low, or outputs, MSTR high. chips, and standard serial data formats. fine the particular channel, left or right. of SDA TA and is also described in Figure 10. When clear, falling edge of SCK latches data. FSF1: with FSF0, select FSYNC format. SDF0: with SDF1 & SDF2, select serial data format. FSF0: with FSF1, select FSYNC format. SDF2: with SDF0 & SDF1, select serial data format. SDF1: with SDF0 & SDF2, select serial data format. MSTR: When set, SCK and FSYNC are outputs. SCED: When set, rising edge of SCK latches data. Figure 9. Control Register 3

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riods are output per sample. relationship of FSYNC and MCK. of the buffer and is done in a cyclic manner. byte of user data is loaded into the shift register.

16 Bits

18 Bits

20 Bits

16 Clocks 16 Clocks

32 Clocks

32 Clocks 32 Clocks

Figure 10. CS8401A Serial Port SDATA and FSYNC Timing

individual buffer mode sections. Figure 11. CS8401A Status Register Flag Timing

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bytes of channel status data. and flag 2 can be used to monitor this buffer. large, flag 0 can be used to monitor both. trates the buffer read sequence for mode 2. Figure 13. CS8401A Buffer Memory Read Sequence - MODE 1

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VD+ - Positive Digital Power, PIN 19. Positive supply for the digital section. Nominally +5 volts. GND - Ground, PIN 18. Ground for the digital section. Audio Input Interface SCK - Serial Clock, PIN 6. Serial clock for SDA TA pin which can be configured (via control register 3) as an input or output, and can sample data on the rising or falling edge. As an output, SCK will contain 32 clocks for every audio sample. As an input, it does not need to be continuous and can be up to 15 MHz. FSYNC - Frame Sync, PIN 7. Delineates the serial data and may indicate the particular channel, left or right. Also, FSYNC may be configured as an input or output. The format is based on bits in control register 3. SDATA - Serial Data, PIN 8. Audio data serial input pin. Parallel Interface CS - Chip Select, PIN 14. This input is active low and allows access to the 32 bytes of internal memory. The address bus and RD/WR must be valid while CS is low. CS8401A DATA BUS BIT 4 D4 D3 DATA BUS BIT 3 DATA BUS BIT 5 D5 D2 DATA BUS BIT 2 DATA BUS BIT 6 D6 D1 DATA BUS BIT 1 DATA BUS BIT 7 D7 D0 DATA BUS BIT 0 MASTER CLOCK MCK TXP TRANSMIT POSITIVE SERIAL DATA CLOCK SCK VD+ POWER FRAME SYNC FSYNC GND GROUND SERIAL INPUT DATA SDATA TXN TRANSMIT NEGATIVE ADDRESS BUS BIT 4 A4 RD /WR READ/WRITE SELECT ADDRESS BUS BIT 3 A3 INT INTERRUPT ADDRESS BUS BIT 2 A2 CS CHIP SELECT ADDRESS BUS BIT 1 A1 A0 ADDRESS BUS BIT 0 12 13 CS8401A

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RD/ WR - Read/Write, PIN 16. If RD/WR is low when CS goes active (low), the data on the data bus is written to internal memory. If RD/WR is high when CS goes active, the data in the internal memory is placed on the data bus. A4-A0 - Address Bus, PINS 9-13. Parallel port address bus that selects the internal memory location to be read from or written to. D0-D7 - Data Bus, PINS 21-24, 1-4. Parallel port data bus used to check status, write control words, or write internal buffer memory. INT - Interrupt, PIN 15. Open drain output that can signal the state of the internal buffer memory. A 5kΩ resistor to VD+ is typically used to support logic gates. All bits affecting INT are maskable allowing total control over the interrupt mechanism. Transmitter Interface MCK - Master Clock, PIN 5. Clock input which defines the transmit timing. It can be configured, via control register 2, for 128, 192, 256, or 384 times the sample rate. TXP, TXN - Differential Line Drivers, PINS 20, 17. RS422 compatible line drivers. Drivers are pulled low when part is in reset state. CS8401A DS60F1 17

coded and driven through an RS422 line driver. to the professional standard, and the CRC code (C.S. byte 23) can be internally generated. the consumer mode is compact disk, CD, mode. MCK input must be 128 times that or 5.6448 MHz. and 1 are designed to interface with Crystal ADCs. Table 3. CS8402A Audio Port Modes

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16 Bits 16 Bits

18 Bits18 Bits

Figure 16. CS8402A Audio Serial Port Formats

is right as per the digital audio interface specs. Figure 17. CBL and Transmitter Timing

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the transparent mode MCK must be 256 Fs. channel status bits are input at the C pin. 9, 15, 24, and 25 are controlled via dedicated pins.

16 RST

Figure 19. CS8402A Block Diagram - Professional Mode

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generation status of the transmitted material (i.e.. first generation, second generation). category code is forced to CD. Figure 20. CS8402A Block Diagram - Consumer Mode Table 5. Sample Frequency Encoding Table 4. Emphasis Encoding

16 RST9V

Figure 21. CS8402A Block Diagram - Consumer Mode, CD Submode Figure 22. CD Subcode Port Timing

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VD+ - Positive Digital Power, PIN 19. Positive supply for the digital section. Nominally +5 volts. GND - Ground, PIN 18. Ground for the digital section. Audio Input Interface SCK - Serial Clock, PIN 6. Serial clock for SDA TA pin which can be configured (via the M0, M1, and M2 pins) as an input or output, and can sample data on the rising or falling edge. As an output, SCK will contain 32 clocks for every audio sample. As an input, it does not need to be continuous and can be up to 15 MHz. FSYNC - Frame Sync, PIN 7. Delineates the serial data and may indicate the particular channel, left or right, and may be an input or output. The format is based on M0, M1, and M2 pins. SDATA - Serial Data, PIN 8. Audio data serial input pin. M0, M1, M2 - Serial Port Mode Select, PINS 21, 22, 23. Selects the format of FSYNC and the sample edge of SCK with respect to SDATA. Control Pins RST - Master Reset, PIN 16. When low, all internal counters are reset and the line drivers are disabled, pulling low. CS8402A CS BIT 7 / CS BIT 3 C7 /C3 TRNPT/FC1 TRANSPARENT / FREQ. CTRL 1 PROFESSIONAL MODE PRO M2 SERIAL PORT MODE SELECT 2 CS BIT 1 / FREQ. CTRL. 0 C1 /FC0 M1 SERIAL PORT MODE SELECT 1 CS BIT 6 / CS BIT 2 C6 /C2 M0 SERIAL PORT MODE SELECT 0 MASTER CLOCK MCK TXP TRANSMIT POSITIVE SERIAL DATA CLOCK SCK VD+ POWER FRAME SYNC FSYNC GND GROUND SERIAL INPUT DATA SDATA TXN TRANSMIT NEGATIVE VALIDITY INPUT V RST MASTER RESET CS SERIAL IN / SC FRAME CLOCK C/SBF CBL/SBC CS BLOCK OUT / SC BIT CLOCK USER DATA INPUT UE M 0 /C9 EMPHASIS 0 / CS BIT 9 CS BIT 9 / CS BIT 15C9 /C15 EM1 /C8 EMPHASIS 1 / CS BIT 8 12 13 CS8402A DS60F1 25

V - Validity, PIN 9. V alidity bit serial input port. This bit is defined according to the digital audio standards wherein V = 0 signifies the audio signal is suitable for conversion to analog. V = 1 signifies the audio signal is not suitable for conversion to analog, i.e. invalid. V is sampled once per subframe U - User Bit, PIN 11. User bit serial input port is sampled once per subframe. PRO - Professional/Consumer Select, PIN 2. Selects between professional mode (PRO low) and consumer mode ( PRO high). This pin defines the functionality of the next seven pins. PRO must be low for Transparent Mode, but will have no effect on the channel status bits. C9/C15 - Channel Status Bit 9 / Channel Status Bit 15, PIN 12. In professional mode, C9 is the inverse of channel status bit 9 (bit 1 of byte 1). In consumer mode, C15 is the inverse of channel status bit 15 (bit 7 of byte 1). C9/C15 are ignored in Transparent Mode. EM0/ C9 - Emphasis 0 / Channel Status Bit 9, PIN 14. In professional mode, EM0 and EM1 encode channel status bits 2, 3, and 4. In consumer mode, C9 is the inverse of channel status bit 9 (bit 1 or byte 1). EMO/C9 are ignored in Transparent Mode. EM1/ C8 - Emphasis 1 / Channel Status Bit 8, PIN 13. In professional mode, EM0 and EM1 encode channel status bits 2, 3, and 4. In consumer mode, C8 is the inverse of channel status bit 8 (bit 0 of byte 1). EM1/C8 are ignored in Transparent Mode. C7/C3 - Channel Status Bit 7 / Channel Status Bit 3, PIN 1. In professional mode, C7 is the inverse of channel status bit 7. In consumer mode, C3 is the inverse of channel status bit 3. C7/C3 are ignored in Transparent Mode. C6/C2 - Channel Status Bit 6 / Channel Status Bit 2, PIN 4. In professional mode, C6 is the inverse of channel status bit 6. In consumer mode, C2 is the inverse of channel status bit 2. C6/C2 are ignored in Transparent Mode. C1/FC0 - Channel Status Bit 1 / Frequency Control 0, PIN 3. In professional mode, C1 is the inverse of channel status bit 1. In consumer mode, FC0 and FC1 are encoded versions of channel status bits 24 and 25 (bits 0 and 1 of byte 3). When FC0 and FC1 are both high, CD mode is selected. C1/FC0 are ignored in Transparent Mode. CS8402A

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TRNPT/FC1 - Transparent Mode / Frequency Control 1, PIN 24. In professional mode, setting TRNPT low selects normal operation & CBL is an output. Setting TRNPT high, allows the CS8402A to be connected directly to a CS8412. In transparent mode, CBL is an input & MCK must be at 256 Fs. In consumer mode, FC0 and FC1 are encoded versions of channel status bits 24 and 25. When FC0 and FC1 are both high, CD mode is selected. C/SBF - Channel Status Serial Input / Subcode Frame Clock, PIN 10. In professional and consumer modes this pin is the channel status serial input port. In CD mode this pin inputs the CD subcode frame clock. CBL/SBC - Channel Status Block Output / Subcode Bit Clock, PIN 15. In professional and consumer modes, the channel status block output is high for the first 16 bytes of channel status. In CD mode, this pin outputs the subcode bit clock. Transmitter Interface MCK - Master Clock, PIN 5. Clock input at 128× Fs the sample frequency which defines the transmit timing. In transparent mode, MCK must be 256× Fs. TXP, TXN - Differential Line Drivers, PINS 20, 17. RS422 compatible line drivers. Drivers are pulled to low when part is in reset state. CS8402A DS60F1 27

Appendix A: RS422 Driver Information The RS422 drivers on the CS8401A and CS8402A are designed to drive both the professional and con- sumer interfaces. The AES/EBU specification for professional/broadcast use calls for a 110Ω source impedance and a balanced drive capability. Since the transmitter impedance is very low, a 110Ω resistor should be placed in series with one of the transmit pins. (A 110Ω resistor in parallel with the trans- former would, with the receiver impedance of 110Ω , provide a 55Ω load to the part which is too low.) The specifications call for a balanced output drive of 2-7 volts peak-to-peak into a 110Ω load with no ca- ble attached. Using the circuit in Figure A1, the output of the transformer is short-circuit protected, has the proper source impedance, and provides a 5 volt peak-to-peak signal into a 110Ω load. Lastly, the two output pins should be attached to an XLR connector with male pins and a female shell, and with pin 1 of the connector grounded. In the case of consumer use, the specifications call for an unbalanced drive circuit with an out- put impedance of 75Ω and a output drive level of 0.5 volts peak-to-peak ±20% when measured across a 75Ω load using no cable. The circuit shown in Figure A2 only uses the TXP pin and provides the proper output impedance and drive level using standard 1% resistors. The connector for consumer would be an RCA phono socket. This circuit is also short circuit protected. The TXP pin may be used to drive TTL or CMOS gates as shown in Figure A3. This circuit may be used for optical connectors for digital audio since they are usually TTL compatible. This circuit is also useful when driving multiple digital audio outputs since RS422 line drivers have TTL interfaces. The transformer should be capable of operating from 1.5 to 7 MHz, which is the audio data rate of 25 kHz to 55 kHz after biphase-mark encod- ing. Transformers provide isolation from ground loops, 60 Hz noise, and common mode noise and interference. One of the important considera- tions when choosing transformers is minimizing shunt capacitance between primary and secon- dary windings. The higher the shunt capacitance, the lower the isolation between primary and sec- ondary, and the more coupling of high frequency energy. This energy appears in the form of com- mon mode noise on the receive side ground and has the potential to degrade analog performance. Therefore, for best performance, shielded trans- formers optimized for minimum shunt capacitance should be used. The following are a few typical transformers: Pulse Engineering Telecom Products Group 7250 Convoy Ct. San Diego, CA 92111 CS8401/2A TXN TXP 110 XLR CS8401/2A TXN TXP 374

90.9 RCA

Figure A1. Professional Output Circuit Figure A2. Consumer Output Circuit CS8401/2A TXN TXP TTL or CMOS Gate Figure A3. TTL/CMOS Output Circuit CS8401A CS8402A

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(619) 268-2400 Part Number: PE65612 Schott Corporation 1000 Parkers Lane Rd. Wayzata, MN 55391 (612) 475-1173 FAX (612) 475-1786 Part Number: 67125450 - compatible with Pulse 67128990 - lower cost 67129000 - surface mount 67129600 - single shield Scientific Conversions Inc.

42 Truman Drive

Novato, CA. 94947 (415) 8922323 Part Number: SC916-01 - single shield SC916-02 - surface mount Appendix B: MCK and FSYNC Relationship FSYNC should be derived either directly or indi- rectly from MCK. The indirect case could be a DSP , providing FSYNC through its serial port, using the same master oscillator that generates MCK. In either case, FSYNC’s relationship to MCK is fixed and does not move. Since this ap- pendix provides information on what would happen if FSYNC did move with respect to MCK, it does not apply to the majority of users. All internal timing is derived from MCK. On the CS8402A, MCK is always 128 ×Fs. On the CS8401A, the external MCK is programmable and is initially divided to 128×Fs before being used by the part. The internal clock IMCK used in the following discussion is always 128×Fs re- gardless of the external MCK pin. After RST, the CS8401A and CS8402A syn- chronize the internal timing to the audio data port, more specifically FSYNC, to guarantee that channel A is left channel data and channel B is right channel data as per the AES/EBU specifica- tion. If FSYNC moves with respect to IMCK, the transmitter could lose synchronization, which causes an internal reset. Figure B1 shows the structure of the serial port input, to the transmitter output. The audio data is serially shifted into R1. PLD is an internal signal that parallel loads R1 into the R2 buffer, and, at the same time, the C, U, and V bits are latched. On the CS8401A, the C, U, and V bits are held in RAM, whereas on the CS8402A, they are latched from external pins. The PLD signal rises on the first SCK edge that can latch data. This is coincident with the latching of the MSB of audio data in MSB-first, left-justified modes. PLD stays high for one SCK period. In the CS8402A section, the arrows on SCK in Figure 16 indicate when PLD goes high. Also, SBC in the CS8402A CD submode is an external version of PLD gated by the SBF input. P C U V Preamble Dri- verMux Biphase Encode TXP TXN R3 - Shift (out) Register R2 - Audio Buffer R1 - Shift (in) RegisterSDATA SCK internally generated CS8402A C,U,V Port CS8401A Internal Memory PLD (load signal) LDS (load signal) IMCK D Q Internal Reset Figure B1. Serial Port-to-Transmitter Block Diagram CS8401A CS8402A DS60F1 29

When the part is finished transmitting the pream- ble of a sub-frame, the internal signal LDS rises to parallel-load R2 into R3 for transmission. Af- ter RST, the part synchronizes the audio port to IMCK as shown in Figure B2. Since PLD is based on FSYNC and LDS is based on IMCK, if FSYNC mo v es with res pect to IMCK until PLD and LDS occur at the same time, the data would not be properly loaded into R3. If LDS and PLD overlap, an internal reset is initiated causing the timing to return to the initial state shown in Fig- ure B2. Figure B2. Serial Ports-to-Transmitter Timing (slave mode) Preamb. Left 0VUCP Right 0 CUV0L 191R CUV191R Left 0 Preamb. Right 191VUCP 191L Left 191 9.5 8.5 IMCK PLD CS8402A C,U, V SDATA FSYNC SCK CS8402A CBL CS8401A Flags TXN TXP LDS Ordering Guide Model Temperature Range Package CS8401A-CP 0 to 70 °C* 24-Pin Plastic .3" DIP CS8401A-IP -40 to 85 °C 24-Pin Plastic .3" DIP CS8401A-CS 0 to 70 °C* 24-Pin Plastic SOIC CS8401A-IS -40 to 85 °C 24-Pin Plastic SOIC CS8402A-CP 0 to 70 °C* 24-Pin Plastic .3" DIP CS8402A-IP -40 to 85 °C 24-Pin Plastic .3" DIP CS8402A-CS 0 to 70 °C* 24-Pin Plastic SOIC CS8402A-IS -40 to 85 °C 24-Pin Plastic SOIC * Although the ’-CP’ and ’-CS’ suffixed parts are guaranteed to operate over 0 to 70 °C, they are tested at 25 °C only. If testing over temperature is desired, the ’-IP’ and ’-IS’ suffixed parts are tested over their specified temperature range. CS8401A CS8402A

30 DS60F1

D B A L C 6.10 31.37 1.02 0.36 0.51 3.94 3.18 0.20 2.41 7.62 6.60 32.13 1.65 0.56 1.02 4.57 3.81 0.38 15° 0.240 1.235 0.095 0.040 0.014 0.020 0.155 0.125 0.300 0.008 0.260 0.065 0.022 0.040 0.180 0.150 0.015 15° 24 pin Plastic Skinny DIP 1.265 8.25 0.325 24 13 E11 12 D B1 e1 B A1 L ASEATING PLANE C eA 2.67 0.105 NOTES: 1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN 0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH. NOM 6.35 31.75 1.27 0.46 0.76 4.32 0.25 2.54 NOM 0.250 1.250 0.100 0.050 0.018 0.030 0.170 0.010 eA

A A A A A A A A A AA AA A A AA AA AA AAA A A A AAA AA AA AA AAA A A A A A A AA AA AA AAA A A A AAA AA AA AA AAA A A A A A A AAA A A A A A A AA A A A A AAA A A A AAA AA A A AA SOIC MILLIMETERS INCHES MIN MAX MAXMIN 0.095 0.1052.41 2.67 0.008 0.0150.203 0.381 0.398 0.42010.11 10.67 0.0200.0130.510.33 0.016 0.0350.41 0.89 8°0°0° 8° MILLIMETERS INCHES MIN MAX MAX MINpins 0.4100.3909.91 10.4116 0.5100.49012.45 12.9520 0.6100.59014.99 15.5024 0.7100.69017.53 18.0328 0.0120.0050.127 0.300 1.14 0.040 DIM E E b L D e A A c 0.292 0.2987.42 7.57 D EE1 e A Ab 1 A 2 c L µ µ 1.40 0.055 A 2 see table above NOM 2.54 0.280 10.41 0.46 NOM 10.16 12.70 15.24 17.78 7.49 1.27 2.29 2.542.41 NOM 0.100 0.011 0.410 0.018 NOM 0.400 0.500 0.600 0.700 0.295 0.050 0.1000.090 0.095

• Notes •

Smart AnalogTM is a Trademark of Crystal Semiconductor Corporation