82C52 INTERSIL | Alldatasheet
Document overview
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Technical content
Features
- Single Chip UART/BRG
- DC to 16MHz (1M Baud) Operation
- Crystal or External Clock Input
- On-Chip Baud Rate Generator - 72 Selectable Baud Rates
- Interrupt Mode with Mask Capability
- Microprocessor Bus Oriented Interface
- 80C86 Compatible
- Single +5V Power Supply
- Modem Interface
- Line Break Generation and Detection
- Operating Temperature Range:
- Pb-Free Plus Anneal Available (RoHS Compliant)
Ordering Information
RANGE (°C) PACKAGE PKG. DWG. # CP82C52 CP82C52 0 to +70 PDIP E28.6 CP82C52Z (Note) CP82C52Z 0 to +70 PDIP (Pb-Free)** E28.6 IP82C52 IP82C52 -40 to +85 PDIP E28.6 CS82C5296 CS82C52 0 to +70 PLCC (Tape & Reel) N28.45 CS82C52Z* (Note) CS82C52Z 0to +70 PLCC (Pb-Free) N28.45 IS82C52 IS82C52 -40 to +85 PLCC N28.45 IS82C52Z* (Note) IS82C52Z -40 to +85 PLCC (Pb-Free) N28.45 ID82C52 ID82C52 -40 to +85 CERDIP F28.6 MD82C52/B MD82C52/B -55 to +125 F28.6 8501501XA 8501501XA SMD# F28.6 MR82C52/B -55 to +125 CLCC J28.A 85015013A 85015013A SMD# J28.A *Add "96" suffix for tape and reel. **Pb-free PDIPs can be used for through hole wave solder processing only. They are not intended for use in Reflow solder processing applications. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Data Sheet FN2950.3 April 26, 2006 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 1997, 2002, 2006. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
2 FN2950.3 April 26, 2006 Pinouts Block Diagram 82C52 (PDIP, CERDIP) TOP VIEW 82C52 (PLCC, CLCC) TOP VIEW RD WR IX OX CSO DR SDI INTR RST CO DTR DSR CTS GND SDO VCC TBRE RTS 1911 3 2 14 14 15 16 17 1812 13 28 27 26 SDI INTR RST TBRE CO RTS DTR IX OX SDO GND DSR CTS WR RD CSO DR VCC READ/WRITE CONTROL LOGIC DATA BUS BUFFER PROGRAM- MABLE BOUD RATE CONTROL LOGIC 3 - 10 RD WR 28CSO OX CO RST INTR 13IX GENERATOR INTERNAL DATA BUS TRANSMITTER BUFFER REGISTER UART CONTROL AND STATUS RECEIVER BUFFER REGISTER MODEM CONTROL AND REGISTERS STATUS REGISTERS
18 DSR
17 CTS
19 DTR
20 RTS
P RECEIVER REGISTER P S SDO SDI TBRE DR S D0-D7 82C5282C52
3 FN2950.3 April 26, 2006 Pin Description SYMBOL PIN NO. TYPE ACTIVE LEVEL DESCRIPTION RD 1 I Low READ: The RD input causes the 82C52 to output data to the data bus (D0-D7). The data output depends upon the state of the address inputs (A0-A1). CS0 enables the RD input. WR 2 I Low WRITE: The WR input causes data from the data bus (D0-D7) to be input to the 82C52. Addressing and chip select action is the same as for read operations. D0-D7 3-10 I/O High DATA BITS 0-7: The Data Bus provides ei ght, three-state input/output lines for the transfer of data, control and status information between the 82C52 and the CPU. For character formats of less than 8 bits, the corresponding D7, D6 and D5 are consider ed “don't cares” for data WRITE operations and are 0 for data READ operations. These lines are normally in a high impedance state except during read operations. D0 is the Least Significant Bit (LSB) and is the first serial data bit to be received or transmitted. A0, A1 11, 12 I High ADDRESS INPUTS: The address lines sele ct the various internal registers during CPU bus operations. IX, OX 13, 14 I/O CRYSTAL/CLOCK: Crystal connections for the internal Baud Rate Generator. IX can also be used as an external clock input in which case OX should be left open. SDO 15 O High SERIAL DATA OUTPUT: Serial data output from t he 82C52 transmitter circuitry. A Mark (1) is a logic one (high) and Space (0) is logic zero (low). SD0 is held in the Mark condition when CTS is false, when RST is true, when the Transmitter Register is empty, or when in the Loop Mode. GND 16 Low GROUND: Power supply ground connection. CTS 17 I Low CLEAR TO SEND: The logical state of the CTS line is reflected in the CTS bit of the Modem Status Register. Any change of state in CTS causes INTR to be set true when INTEN and MIEN are true. A false level on CTS will inhibit transmission of data on the SD0 output and will hold SD0 in the Mark (high) state. If CTS goes false during transmission, the curr ent character being transmitted will be completed. CTS does not affect Loop Mode operation. DSR 18 I Low DATA SET READY: The logical state of the DSR line is reflected in the Modem Status Register. Any change of state of DSR will cause INTR to be set if INTEN and MIEN are true. The state of this signal does not affect any other circuitry within the 82C52. DTR 19 O Low DATA TERMINAL READY: The DTR signal can be set (low) by writing a logic 1 to the appropriate bit in the Modem Control Register (MCR). This signal is cleared (high) by writing a logic 0 in the DTR bit in the MCR or whenever a reset (RST = high) is applied to the 82C52. RTS 20 O Low REQUEST TO SEND: The RTS signal can be set (low) by writing a logic 1 to the appropriate bit in the MCR. This signal is cleared (high) by writing a logic 0 to the RTS bit in the MCR or whenever a reset (RST = high) is applied to the 82C52. CO 21 O CLOCK OUT: This output is user programmable to provide either a buffered IX output or a buffered Baud Rate Generator (16X) clock output. The buffered IX (Crystal or external clock source) output is provided when the Baud Rate Select Register (BRSR) bit 7 is set to a zero. Writing a logic one to BRSR bit 7 causes the CO output to provide a buffered version of the internal Baud Rate Generator clock which operates at sixteen times the programmed baud rate. On reset D7 (CO select) is reset to TBRE 22 O High TRANSMITTER BUFFER REGISTER EMPTY: The TBRE output is set (high) whenever the Transmitter Buffer Register (TBR) has transferred its data to the Transmit Register. Application of a reset (RST) to the 82C52 will also set the TBRE output. TBRE is cleared (low) whenever data is written to the TBR. RST 23 I High RESET: The RST input forces the 82C52 into an “Idle” mode in which all serial data activities are suspended. The Modem Control Register (MCR) along with its associated outputs are cleared. The UART Status Register (USR) is cleared except for the TBRE and TC bits, which are set. The 82C52 remains in an “Idle” state until programmed to re sume serial data activities. The RST input is a Schmitt triggered input. INTR 24 O High INTERRUPT REQUEST: The INTR output is enabled by the INTEN bit in the Modem Control Register (MCR). The MIEN bit selectively enables modem status changes to provide an input to the INTR logic. Figure 9 in Design Information shows th e overall relationship of these interrupt control signals. 82C5282C52
4 FN2950.3 April 26, 2006 SDI 25 I High SERIAL DATA INPUT: Serial data input to the 82C52 receiver circuits. A Mark (1) is high, and a Space (0) is low. Data inputs on SDI are disabled when operating in the loop mode or when RST is true. DR 26 O High DATA READY: A true level indicates that a c haracter has been received, transferred to the RBR, and is ready for transfer to the CPU. DR is reset on a data READ of the Receiver Buffer Register (RBR) or when RST is true. V CC 27 High V CC: +5V positive power supply pin. A 0.1 µF decoupling capacitor from V CC (Pin 27) to GND (Pin 16) is recommended. CS0 28 I Low CHIP SELECT: The chip select input acts as an enable signal for the RD and WR input signals. Pin Description (Continued) SYMBOL PIN NO. TYPE ACTIVE LEVEL DESCRIPTION 82C5282C52
- Resets the internal Baud Rate Generator (BRG) circuit clock counters and bit counters. The Baud Rate Select Register (BRSR) is not affected (except for bit 7 which is reset to 0).
- Clears the UART Status Register (USR) except for Transmission Complete (TC) and Transmit Buffer Register Empty (TBRE) which are set. The Modem Control Register (MCR) is also cleared. All of the discrete lines, memory elements and miscellaneous logic associated with these register bits are also cleared or turned off. Note that the UART Control Register (UCR) is not affected. Following removal of the reset condition (RST = low), the 82C52 remains in the idle mode until programmed to its desired system configuration. Programming The 82C52 The complete functional definition of the 82C52 is programmed by the systems software. A set of control words (UCR, BRSR and MCR) must be sent out by the CPU to initialize the 82C52 to support the desired communication format. These control words will program the character length, number of stop bits, even/odd/no parity, baud rate, etc. Once programmed, the 82C52 is ready to perform its communication functions. The control registers can be written to in any order. However, the MCR should be written to last because it controls the interrupt enables, modem control outputs and the receiver enable bit. Once the 82C52 is programmed and operational, these registers can be updated any time the 82C52 is not immediately transmitting or receiving data.
Table 1. Shows the control signals required to access 82C52 insure software compatibility with future product upgrades. programmed with different or no parity. See Figure 1.
00001 D a t a B u s → Transmitter Buffer
00010 R e c e i v e r B u f f e r R e g i s t e r
00101 D a t a B u s → UART Control
00110 U A R T S t a t u s R e g i s t e r
01001 D a t a B u s → Modem Control
01010 M C R → Data Bus
01101 D a t a B u s → Bit Rate Select
01110 M o d e m S t a t u s R e g i s t e r
FIGURE 1. UCR
the Transmitter and Receiver circuits. “external” is selected and the Prescaler is set to ÷3 or ÷5. frequency/ Prescale divisor combinations. directly controlled by their associated bits in this register. FIGURE 2. BRSR
11 FN2950.3 April 26, 2006 Absolute Maximum Ratings Thermal Information Operating Conditions Operating Temperature Range Thermal Resistance (Typical, Note 1) θJA (°C/W) θJC (°C/W) Maximum Junction Temperature (Lead Tips Only For Surface Mount Packages) Die Characteristics CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. θJA is measured with the component mounted on an evaluation PC board in free air. TA = -55°C to +125°C (M82C52) SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS VIH Logical One Input Voltage 2.0 - V I82C52, C82C52 2.2 - V M82C52 VIL Logical Zero Input Voltage - 0.8 V VTH Schmitt Trigger Logic One Input Voltage V CC -0.5 - V Reset Input VTL Schmitt Trigger Logic Zero Input Voltage - GND +0.5 V Reset Input VIH (CLK) Logical One Clock Input Voltage V CC -0.5 - V External Clock VlL (CLK) Logical Zero Clock Input Voltage - GND +0.5 V External Clock VOH Output High Voltage 3.0 - V I OH = -2.5mA, Except OX VCC -0.4 - V I OH = -100µA, For OX - IOH = -1.0mA VOL Output Low Voltage - 0.4 V l OL = +2.5mA II Input Leakage Current -1.0 +1.0 µAV IN = GND or VCC, DIP Pins 1, 2, 11, 12, 17, 18, 23, 25, 28 IO Input/Output Leakage Current -10.0 +10.0 µAV O = GND or VCC, DIP Pins 3-10 ICCOP Operating Power Supply Current (Note 1) - 4 mA External Clock F = 2.4576MHz, VCC = 5.5V, VIN = VCC or GND, Outputs Open ICCSB Standby Supply Current - 100 µAV CC = 5.5V, VIN = VCC or GND, Outputs Open NOTE: 1. Guaranteed and sampled, but not 100% tested. ICCOP is typically ≤ 1.5mA/MHz. Capacitance TA = 25°C SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS CIN Input Capacitance 12 pF FREQ = 1MHz, all measurements are referenced to device GNDCOUT Output Capacitance 15 pF CI/O I/O Capacitance 15 pF 82C5282C52
FIGURE 12. PROPAGATION DELAY FIG URE 13. ENABLE/DISABLE DELAY AC TESTING: All input signals (except IX and RST) must switch between V IL -0.4V and VIH +0.4V. Input rise and fall times are driven at 1ns/V.
FIGURE 14. BUS OPERATION
2 Disable Delay V CC 5K 5K 50pF
14 FN2950.3 April 26, 2006 UART Timing Characterization All parameters listed in this table were laboratory bench characterized at room temperature on a small sample of parts. No guarantee is implied. The main intent here is to clarify functional operation of the 82C52. 82C52 UART Timing Characterized with IX = External Clock SYMBOL PARAMETER MIN MAX UNITS TEST CONDITIONS (15) TS1 CO(IX) Delay from IX - 30 ns BRSR Bit D7 = 0 (IX Output) (16) TS2 CO (BRG) Delay from IX - 80 ns BRSR Bit D7 = 1 (BRG Output) (17) TCY CO (BRG) Clock Cycle Time 62.5 - ns BRSR Bit D7 = 1 (BRG Output), Note 1 (18) TDTX SDO Delay from CO(BRG) Low - 30 ns Note 2 (19) TWLTL WR Low to TBRE Low - 50 ns Note 3 (20) TCLTH CO (BRG) Low to TBRE HIgh - 50 ns Notes 3, 4 (21) TIHF INTR High on Flag - 50 ns Note 5A, 5B (22) TIHM INTR High on MS - 50 ns Note 5 (23) TRLIL RD Low to INTR Low - 60 ns (24) TCTHX CTS High to Disable Transmit 4TCY + 10 - ns TBR Full, Note 6 (25) TDRH CO (BRG) Low to DR High - 40 ns Note 7 (26) TRLDL RD Low to DR Low - 50 ns Note 7 (27) TWHO WR High to RTS/DTR Active - 50 ns NOTES: 1. Prescaler rate of divide by 1, Divisor Select rate of “external” (divide by 1). The Baud Rate Clock (CO-BRG) operates at 16 times the user programmed bit rate. For example, at 1200 baud: TCY = 1/(16 x 1200) = 52.1µs. 2. A. With TR (Transmitter Register) initially empty, TD TX occurs from the 5th falling edge of CO(BRG) after WR goes high. B. With TR initially full, TDTX occurs from the trailing edge of the 16th CO(BRG) in the last Stop bit provided WR went high by the trailing edge of the 12th CO(BRG) in the last Stop bit. C. With CTS high (disable transmit) and TBR full, TDTX occurs from the 5th falling edge of CO(BRG) after CTS goes low. 3. TBRE bit D6 in USR is updated each time TBRE changes state. 4. A. With TR initially empty, TCLTH(TBRE) occurs from the 4th falling edge of CO(BRG) after WR goes high. B. With TR initially full, TCLTH(TBRE) occurs from the tr ailing edge of the 15th CO(BRG) in the last Stop bit provided WR went high by the trailing edge of the 12th CO(BRG) in the last Stop bit. C. With CTS high (disable transmit) and TBR full, TCLTH(TBRE) occurs from the 4th falling edge of CO(BRG) after CTS goes low. 5. A. INT on TC : INTEN enabled; USR bit D5(TC) is updated at this time regardless of interrupt configuration. - INT on TC occurs from the trailing edge of the 11th CO(BRG) in the last Stop bit if TBR empty at that time. B. INTR on receive flags OE, FE, PE, and RBRK: INTEN enabled; Respective USR bits updated at this time regardless of interrupt configura- tion. - INT on OE, FE, PE, RBRK occurs from the trailing edge of the 11th CO(BRG) in the last Stop bit. To avoid OE, RD(RBR) must go low by the trailing edge of the 8th CO(BRG) in the last Stop bit. C. INTR on MS: INTEN and MIEN enabled; USR bit D4(MS) is updated at this time regardless of INTEN/MIEN. - INTR on MS occurs whenever CTS or DSR input changes state. 6. TCTHX is time before end of last Stop bit by which CTS must be inactive (high) to prevent transmission of the character waiting in TBR. 7. DR bit D7 in USR is updated each time DR changes state. T DRH always from trailing edge of 11th CO(BRG) in last Stop bit. 82C5282C52
FIGURE 15. CLOCK (IX) AND CO TIMING FIGURE 16. TRANSMITTER DATA FIGURE 17. RECEIVER DATA
16 CO(BRG) PERIODS
8 CO(BRG) PERIODS
FIGURE 18. TRANSMIT TIMING
- TBRE bit D6 in USR is updated each time TBRE changes state.
- A. With TR initially empty, TCLTH(TBRE) occurs from the 4th falling edge of CO(BRG) after WR
trailing edge of the 12th CO(BRG) in the last Stop bit.
- A. With TR (Transmitter Register) initially empty, TD TX occurs from the 5th falling edge of CO(BRG) after WR goes high.
of the 12th CO(BRG) in the last Stop bit.
- TCTHX is time before end of last Stop bit by which CTS must be inactive (high) to prevent transmission of the character waiting in TBR.
- With CTS high (disable transmit) and TBR full, TCLTH(TBRE) occurs from the 4th falling edge of CO(BRG) after CTS goes low.
- With CTS high (disable transmit) and TBR full, TDTX occurs from the 5th falling edge of CO(BRG) after CTS goes low.
FIGURE 19. RECEIVE TIMING
FIGURE 20. OTHER TIMING
- DR bit D7 in USR is updated each time DR changes state. T DRH always from trailing edge of 11th CO(BRG) in last Stop bit.
- INTR on receive flags OE, FE, PE, and RBRK : INTEN enabled; Respective USR bits updated at this time regardless of interrupt configuration.
trailing edge of the 8th CO(BRG) in the last Stop bit.
- INTR on MS : INTEN and MIEN enabled; USR bit D4(MS) is updated at this time regardless of INTEN/MIEN.
- INTR on MS occurs whenever CTS or DSR input changes state.
19 FN2950.3 April 26, 2006 Burn-In Circuits MD82C52 CERDIP MR82C52 CLCC NOTES: 1. V CC = 5.5V ±0.5V GND = 0V VIL = -0.2V to +0.4V 3. Component Values: C1 = 1.0µF nominal C2 = 0.01µF minimum F0 = 100KHz ±10%, F1 = F0/2, F2 = F1/2 . . . F12 = F11/2 GND VCC/2 VCC VCC/2 A VCC/2 VCC/2 VCC GND GND VCC/2 VCC VCC/2 VCC/2 VCC GND VCC/2 VCC A 1911 3 2 14 14 15 16 17 1812 13 28 27 26 VCC A R1 VCC/2 R1 VCC/2 R1 VCC/2 R1 VCC/2 R1 VCC/2 R1 VCC R2Q5 A R2Q6 R2Q7 R2Q8 R2Q7 R2Q8 R2Q1 VCCGND R1R1 VCC/2 VCCGND R1R2 VCC GND Q4 Q3 82C52
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnishe d by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN2950.3 April 26, 2006 Die Characteristics DIE DIMENSIONS: 178.7 x 187.0 x 19 ±1mils METALLIZATION: Type: Silicon - Aluminum Thickness: 11k Å ±2kÅ GLASSIVATION: Type: Nitrox Thickness: 10k Å WORST CASE CURRENT DENSITY: 2.07 x 104 A/cm2 Metallization Mask Layout 82C52 SD1 INTR TBRE CO CTSGNDIX WR RD CSO VCC DR RST RTS DTR DSR SDOOX 82C52