CS8140

CS8140 CHERRY | Alldatasheet

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Technical content

Features

& Bias Short Circuit Watchdog Undervoltage Regulation RESET Control Logic ENABLE RESET Delay Sense *NOTE: shorted together on 7 Lead TO-220* n 5V ± 4%, 500mA Output Voltage n µP Compatible Control Functions Watchdog ENABLE n Low Dropout Voltage (1.25V @ 500mA) n Low Quiescent Current (7mA @ 500mA) n Low Noise, Low Drift n Low Current SLEEP Mode (IQ = 250µA) n Fault Protection Thermal Shutdown Short Circuit 60V Peak Transient Voltage RESET Package Options

7 Lead TO-220

Tab (Gnd)

14 Lead PDIP

24 Lead SOIC Wide

5V , 500mA Linear Regulator with ENABLE, , and WatchdogRESET Delay VOUT Sense WDI NC NC NC NC NC VIN ENABLE RESET Gnd NC NC NC Gnd NC NC NC NC NC NC NC CS8140/1

Description

V IN ENABLE RESET NC 1V IN

2 ENABLE

4 Gnd

5 Delay

6 WDI

A Company ¨ Rev. 2/23/99 Cherry Semiconductor Corporation

2000 South County Trail, East Greenwich, RI 02818

Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com

Electrical Characteristics: 7V ² VIN ² 26V, 5mA ² IOUT ² 500mA, -40ûC ² TJ ² +150ûC, -40ûC ² TA ² 125ûC unless otherwise specified PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Absolute Maximum Ratings Input Voltage Electrostatic Discharge Lead Temperature Soldering CS8140/1 n Output Stage (VOUT) Output Voltage, VOUT 7V ² VIN ² 26V 4.8 5.0 5.2 V 5mA < IOUT < 500mA Dropout Voltage (VIN - VOUT)I OUT = 500mA 1.25 1.50 V Line Regulation I OUT = 50mA, 5 25 mV 7V ² VIN ² 26V Load Regulation V IN = 14V, 5 80 mV 50mA ² IOUT ² 500mA Output Impedance, ROUT 500mA DC and 10mA AC , 200 m½ 100Hz ² f ² 10kHz Quiescent Current, (IQ) Active Mode 0 ² I OUT ² 500mA, 7V ² VIN ² 26V 7.00 15.00 mA Sleep Mode I OUT = 0mA, VIN = 13V, ENABLE = 0V 0.25 0.50 mA Ripple Rejection 7 ² V IN ² 17V, IOUT = 250mA, 60 75 dB f = 120Hz Current Limit 700 1200 2000 mA Thermal Shutdown 150 180 ¡C Overvoltage Shutdown V OUT < 1V 30 34 38 V n ENABLE Threshold HIGH V OUT ³ 0.5V, (VOUT(ON)) 4.05 4.50 V LOW V OUT < 0.5V, (VOUT(OFF)) 3.50 3.95 V Threshold Hysteresis (HIGH - LOW) 100 mV

Package Lead # Lead Symbol Function Electrical Characteristics: continued PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CS8140/1 n Threshold HIGH VR(HI) VOUT increasing 4.65 4.90 V OUT - 0.05 V LOW VR(LOW) VOUT decreasing 4.50 4.70 4.90 V Threshold Hysteresis(VRH) (HIGH - LOW) 150 200 250 mV Reset Output Leakage V OUT ³V R(HI) 25 µA = HIGH Output Voltage Low(VL(LOW) ) 1V ² V OUT ²V R(LOW) 0.1 0.4 V Rp = 2.7k½* Low (VRpeak )V OUT, Power up, Power down 0.6 1.0 V Delay Times C DELAY = 0.1µF tPOR 30.0 47.5 65.0 ms tWDI( ) 0.5 1.0 1.5 ms n Watchdog Input Voltage HIGH 2.0 V LOW 0.8 V Input Current WDI ² V OUT 01 0 µ A Threshold Frequency C DELAY = 0.1µF fWDILOWER 64 77 96 Hz fWDI(UPPER)** 218 262 326 Hz * RP is connected to and V OUT. ** CS8140 only To observe safe operating junction temperature, low duty cycle pulse testing is used on tests where applicable. RESET RESET RESET RESET

7 Lead 24 Lead * 14 Lead

12 1 1 2 V IN Supply voltage to IC, usually direct from the battery. 2 23 13 ENABLE CMOS compatible logical input. V OUT is disabled when ENABLE is LOW and WDI is beyond its preset limits. 3 24 14 CMOS compatible output lead. goes low whenever VOUT drops below 4.5% of its typical value for more than 2µs or WDI signal falls outside itÕs window limits. 4 12, 20 11 Gnd Ground connection. 5 2 1 Delay Timing capacitor for Watchdog and functions. 6 3 2 WDI CMOS compatible input lead. The Watchdog function mon- itors the falling edge of the incoming digital pulse train. The signal is usually generated by the system microprocessor. 74 3 V OUT Regulated output voltage, 5V (typ). N/A 5 4 Sense Kelvin connection which allows remote sensing of output voltage for improved regulation. 1,6-11,13-19,22 5-10 NC No connection. * The CS8141 uses a fused lead package. Leads 6-8 and 17-19 are fused together through the lead frame. These leads are electrically connected to IC ground and should be connected to system ground for a good thermal connection. RESET RESETRESET

Typical Performance Characteristics CS8140/1 0123456789 1 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Rload = NO LOAD VOUT (V) VIN (V) VENABLE = VIN Rload = 6.67W Rload = 10W VOUT vs. VIN over RLOAD; T = 25ûC 0123456789 1 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 VOUT (V) VIN (V) TEMP = 25°C TEMP = 125°C TEMP = -40 °C VENABLE = VIN VOUT vs. VIN over Temperature; RLOAD = 25½ 0 100 200 300 400 500 600 700 800 400 600 800 1200 1400 1600 1800 200 1000 -40°C 125°C 25°C IOUT (mA) Dropout Voltage (mV) Dropout Voltage vs. Output Current over Temperature 0 100 200 300 400 500 600 700 800 -35.0 -31.5 -28.0 -24.5 -21.0 -17.5 -14.0 -10.5 -7.0 -3.5 3.5 -40°C 25°C 125°C VIN = 14V IOUT (mA) LOAD REGULATION (mV) Load Regulation vs. Output Current over Temperature 0 100 200 300 400 500 600 700 800 -40°C 25°C 125°C VIN = 14V IOUT (mA) LINE REGULATION (mV) Line Regulation vs. Output Current over Temperature 0 100 200 300 400 500 600 700 800 -40°C 125°C 25°C IOUT (mA) IQ (mA) VIN = 14V Quiescent Current vs. Output Current over Temperature

Typical Performance Characteristics: continued CS8140/1 0123456789 1 0 VIN (V) IQ (mA)

6 Rload = NO LOAD

Rload = 6.67 Rload = 25 VENABLE = VIN Quiescent Current vs. VIN over RLOAD; T = 25¡C 0123456789 1 0 TEMP = 125°C TEMP = 25°C TEMP =- 40°C VIN (V) IQ (mA) VENABLE = VIN Quiescent Current vs. VIN over Temperature; RLOAD = 25½ -40 -30 -10 10 20 40 60 70 90 110 120 100 120 140 160 180 200 220 240 260 280 -20 0 30 50 80 100 130 140 150 300 TJ (°C) FREQUENCY (Hz) Lower Threshold C DELAY = 0.1mF Upper Threshold Watchdog Frequency Thresholds vs. Temperature 105 104 103 102 101 100 101 102 103 104 105 106 CAPACITANCE (pF) WDI THRESHOLD 106 Lower Threshold 107 107 Upper Threshold Watchdog Frequency Threshold vs CDELAY REJECTION (dB) FREQUENCY (Hz) CO = 10mF, ESR=10W CO = 10mF,ESR=1W CO = 10mF, ESR=1&0.1mF, ESR=0 IO =250mA 100 101 102 103 104 105 106 107 108 Ripple Rejection vs Frequency 2000 1800 1600 1400 1200 1000 800 600 400 200 1 5 10 15 20 25 30 35 40 VIN = 5V RESET OUTPUT CURRENT (mA) RESET OUTPUT VOLTAGE (mV) RESET Output Voltage vs Output Current

POR Normal Operation WDI held High Figure 3: Timing Diagrams for Watchdog and ENABLE Functions 3a: VOUT when Watchdog is held high and ENABLE = HIGH. Battery BatteryVIN WDI RESET VOUT 0V POR Normal Operation WDI held Low ENABLE 3b: VOUT when Watchdog is held low and ENABLE = HIGH. Battery BatteryVIN WDI RESET VOUT 0V POR Normal Operation Slow WDI signal ENABLE 3c: VOUT when Watchdog is too slow and ENABLE = HIGH. Battery BatteryVIN WDI RESET VOUT 0V POR Normal Operation Fast WDI signal ENABLE 3d: VOUT when Watchdog is too fast and ENABLE = HIGH. Battery BatteryVIN WDI RESET VOUT 0V POR Normal Operation Sleep ModeWDI high POR Normal Operation ENABLE 3e: WDI held high after a normal period of operation; ENABLE = LOW. Battery BatteryVIN WDI RESET VOUT 0V POR Normal Operation Sleep ModeWDI low POR Normal Operation ENABLE 3f: WDI held low or is too slow after a normal period of operation; ENABLE = LOW. Battery BatteryVIN WDI RESET VOUT 0V POR Normal Operation Sleep Mode POR Normal Operation ENABLE 3g: WDI frequency rises above the upper frequency threshold after a normal period of operation; ENABLE = LOW (for the CS8140 only). CS8140/1

As long as ENABLE is high or ENABLE is low and the Watchdog signal is normal, VOUT will be at 5V (typ). If ENABLE is low and the Watchdog signal moves outside programmable limits, the output transistor turns off and the IC goes into SLEEP mode. Only the ENABLE circuitry in the IC remains powered up, drawing a quiescent cur- rent of 250µA. The Watchdog monitors the frequency of an incoming WDI signal. If the signal falls outside of the WDI window, a frequency programmable pulse train is generated at the lead (Figure 3) until the correct Watchdog input signal reappears at the lead (ENABLE = HIGH). The lower and upper window threshold limits of the watchdog function are set by the value of C DELAY. The lim- its are determined according to the following equations for the CS8140: (a) t WDILOWER = (1.3 x 105)CDELAY or fWDI(LOWER) = (7.69 x 10-6)CDELAY-1 (b) tWDI(UPPER) = (3.82 x 10-4)CDELAY or fWDI(UPPER) = (2.62 x 10-5)CDELAY-1 For the CS8141 the lower limit is determined by the equa- tions in (a) above. The capacitor CDELAY also determines the frequency of the signal and the POWER-ON- (POR) delay period. Function The function is activated when the Watchdog sig- nal is outside of its preset window (Figure 3), when the regulator is in its power up state (Figure 4a) or when V OUT drops below VOUT -4.5% for more than 2µs (Figure 4b.) If the Watchdog signal falls outside of the preset voltage and frequency window, a frequency programmable pulse train is generated at the lead (Figure 3) until the correct Watchdog input signal reappears at the lead. The duration of the pulse is determined by C DELAY according to the following equation: tWDI( ) = (1 x104)CDELAY 4a: Power and Power Down 4b: Undervoltage Triggered If an undervoltage condition exists, the voltage on the lead goes low and the delay capacitor, CDELAY, is discharged. remains low until output is in regula- tion, the voltage on C DELAY exceeds the upper switching threshold and the Watchdog input signal is within its set window limits (Figure 4). The delay after the output is in regulation is: t POR(typ) = (4.75 x 105) CDELAY The delay circuit is also programmed with the external cap CDELAY. The output of the reset circuit is an open collector NPN. is operational down to VOUT = 1V. Both and its delay are governed by comparators with hysteresis to avoid undesirable oscillations. RESETRESET RESET RESET RESET RESET VOUT VOUT -4.5% <2mS RESET tPOR ³2ms RESET VOUT VRHI VRLO VRLO tPOR RESET VRPEAK RESET Circuit Waveforms with Delays Indicated RESET RESET RESET RESET RESET RESETRESET RESET Circuit Description: continued Application Notes The CS8140 with its unique integration of linear regulator and control features: , ENABLE and WATCHDOG, provides a single IC solution for a microprocessor power supply. The reset delay, reset duration and watchdog fre- quency limits are all determined by a single capacitor. For a particular microprocessor the overriding requirement is usually the reset delay (also known as power on reset). The capacitor is chosen to meet this requirement and the reset duration and watchdog frequency follow. The reset delay is given by: t POR(typ) = (4.75 x 105)CDELAY Assume that the reset delay must be 200ms minimum. From the CS8140 data sheet the reset delay has a ±37% tol- erance due to the regulator. Assume the capacitor tolerance is ±10%. tPOR (min) = (4.75 x 105 x 0.63) x CDELAY x 0.9 CDELAY (min) = CDELAY = (min) = 0.743 µF Closest standard value is 0.82µF. Minimum and maximum delays using 0.82µF are 220ms and 586ms. t POR (min) 2.69 x 105 RESET CS8140 Design Example

Application Notes: continued Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage condi- tions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capacitor will usually cost less and occupy less board space. If the output oscillates within the range of expected operating conditions, repeat steps 3 and 4 with the next larger stan- dard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Remove the unit from the environmental chamber and heat the IC with a heat gun. Vary the load current as instructed in step 5 to test for any oscillations. Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regula- tor performance. Most good quality aluminum electrolytic capacitors have a tolerance of +/- 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above. The maximum power dissipation for a single output regu- lator (Figure 9) is: P D(max) = {VIN(max) - VOUT(min)}IOUT(max) + VIN(max)IQ (1) where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the applica- tion, and IQ is the quiescent current the regulator consumes at IOUT(max). Figure 9: Single output regulator with key performance parameters labeled. Once the value of PD(max) is known, the maximum permis- sible value of RQJA can be calculated: RQJA = (2) The value of RQJA can then be compared with those in the package section of the data sheet. Those packages with R QJA's less than the calculated value in equation 2 will keep the die temperature below 150¡C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. A heatsink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of R QJA: RQJA = RQJC + RQCS + RQSA (3) where: RQJC = the junctionÐtoÐcase thermal resistance, RQCS = the caseÐtoÐheatsink thermal resistance, and RQSA = the heatsinkÐtoÐambient thermal resistance. RQJC appears in the package section of the data sheet. Like RQJA, it too is a function of package type. RQCS and RQSA are functions of the package type, heatsink and the inter- face between them. These values appear in heatsink data sheets of heatsink manufacturers. Heatsinks 150¡C - TA PD VIN Smart Regulator VOUT IOUT IIN IQ Control Calculating Power Dissipation in a Single Output Linear Regulator CS8140/1

D Lead Count Metric English Max Min Max Min 24 Lead SOIC Wide 15.60 15.20 .614 .598 14 Lead PDIP 19.69 18.67 .775 .735 Package Specification PACKAGE DIMENSIONS IN mm (INCHES)

Ordering Information

Thermal 7 L 24L 24L (Fused) 14 L Data TO-220 CS8140 CS8141 PDIP RQJC typ 1.6 16 9 48 ûC/W RQJA typ 50 80 55 85 ûC/W Rev. 2/23/99 CS8140/1 Part Number Description CS8140YT7 7L TO-220 Straight CS8140YTVA7 7L TO-220 Vertical CS8140YTHA7 7L TO-220 Horizontal CS8140YDW24 24L SO CS8140YDWR24 24L SO (tape & reel) CS8140YN14 14L PDIP CS8141YT7 7L TO-220 Straight CS8141YTVA7 7L TO-220 Vertical CS8141YTHA7 7L TO-220 Horizontal CS8141YDWF24 24L SO (internally fused leads) CS8141YDWFR24 24L SO (internally fused leads) (tape & reel) CS8141YN14 14L PDIP © 1999 Cherry Semiconductor Corporation Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. Surface Mount Wide Body (DW); 300 mil wide 1.27 (.050) BSC 7.60 (.299) 7.40 (.291) 10.65 (.419) 10.00 (.394) D 0.32 (.013) 0.23 (.009) 1.27 (.050) 0.40 (.016) REF: JEDEC MS-013 2.49 (.098) 2.24 (.088) 0.51 (.020) 0.33 (.013) 2.65 (.104) 0.10 (.004) Plastic DIP (N); 300 mil wide 0.39 (.015) MIN. 1.14 (.045) D Some 8 and 16 lead packages may have 1/2 lead at the end of the package. All specs are the same. .203 (.008) .356 (.014) REF: JEDEC MS-001 3.68 (.145) 2.92 (.115) 8.26 (.325) 7.62 (.300) 7.11 (.280) 6.10 (.240) .356 (.014) .558 (.022)

7 Lead TO-220 (T) Straight

2.87 (.113) 2.62 (.103) 9.78 (.385) 10.54 (.415) 1.40 (.055) 1.14 (.045) 0.64 (.025) 0.38 (.015) 0.56 (.022) 0.36 (.014) 1.40 (.055) 1.14 (.045) 4.83 (.190) 4.06 (.160) 14.22 (.560) 13.72 (.540) 0.94 (.037) 0.58 (.023) 7.75 (.305) 7.49 (.295) 2.92 (.115) 2.29 (.090) 3.71 (.146) 14.22 (.560) 6.55 (.258) 5.94 (.234)

7 Lead TO-220 (TVA) Vertical

10.54 (.415) 9.78 (.385) 2.03 (.080) 7.52 (.296) 4.34 (.171) 1.40 (.055) 1.14 (.045) 14.99 (.590) 14.22 (.560) 11.86 (.467) 4.83 (.190) 4.06 (.160) 8.26 (.325) 7.62 (.300) 0.81 (.030) 1.27 (.050) TYP 0.56 (.022) 0.36 (.014) 2.92 (.115) 2.29 (.090) 2.87 (.113) 2.62 (.103) 6.55 (.258) 5.94 (.234) 2.92 (.115) 3.96 (.156) 3.71 (.146)