CS8129 ONSEMI | Alldatasheet
Document overview
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Technical content
Features
- 5.0 V ±3.0% Regulated Output
- Low Dropout V oltage (0.6 V @ 0.5 A)
- 750 mA Output Current Capability
- Reduced RESET Threshold for Use with 4.0 V Microprocessors
- Externally Programmed RESET Delay
- Fault Protection − Reverse Battery − 60 V , −50 V Peak Transient V oltage − Short Circuit − Thermal Shutdown
- Pb−Free Packages are Available* *For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. TO−220 FIVE LEAD T SUFFIX CASE 314D 1 5 TO−220 FIVE LEAD TVA SUFFIX CASE 314K TO−220 FIVE LEAD THA SUFFIX CASE 314A1 See general marking information in the device marking section on page 8 of this data sheet. DEVICE MARKING INFORMATION SO−16WB DW SUFFIX CASE 751G http://onsemi.com See detailed ordering and shipping information in the package dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
Figure 1. Block Diagram
- 60 seconds max above 183 °C.
http://onsemi.com ELECTRICAL CHARACTERISTICS (−40°C ≤ TA ≤ 125°C, −40 ≤ TJ ≤ 150°C, 6.0 ≤ VIN ≤ 26 V, 5.0 mA ≤ IOUT ≤ 500 mA, RRESET = 4.7 k/C0087 to VOUT unless otherwise noted.) (Note 3) Characteristic Test Conditions Min Typ Max Unit OUTPUT STAGE (VOUT) Output Voltage − 4.85 5.0 5.15 V Dropout Voltage IOUT = 500 mA − 0.35 0.60 V Supply Current IOUT = 10 mA IOUT = 100 mA IOUT = 500 mA 2.0 6.0 7.0 100 mA mA mA Line Regulation 6.0 V ≤ VIN ≤ 26 V, IOUT = 50 mA − 5.0 50 mV Load Regulation 50 mA ≤ IOUT ≤ 500 mA, VIN = 14 V − 10 50 mV Ripple Rejection f = 120 Hz, VIN = 7.0 to 17 V, IOUT = 250 mA 54 75 − dB Current Limit − 0.75 1.20 − A Overvoltage Shutdown − 32 − 40 V Reverse Polarity Input Voltage DC VOUT ≥ −0.6 V, 10 /C0087 Load −15 −30 − V Thermal Shutdown Guaranteed by Design 150 180 210 °C RESET AND DELAY FUNCTIONS Delay Charge Current VDELAY = 2.0 V 5.0 10 15 /C0109A RESET Threshold VOUT Increasing, VRT(ON) VOUT Decreasing, VRT(OFF) 4.05 4.00 4.35 4.20 4.50 4.45 V V RESET Hysteresis VRH = VRT(ON) − VRT(OFF) 50 150 250 mV Delay Threshold Charge, VDC(HI) Discharge, VDC(LO) 3.25 2.85 3.50 3.10 3.75 3.35 V V Delay Hysteresis − 200 400 800 mV RESET Output Voltage Low 1.0 V < VOUT < VRT(L), 3.0 k/C0087 to VOUT − 0.1 0.4 V RESET Output Leakage VOUT > VRT(H) Current − 0 10 /C0109A Delay Capacitor Discharge Voltage Discharge Latched “ON”, VOUT > VRT − 0.2 0.5 V Delay Time CDELAY = 0.1 /C0109F, (Note 4) 16 32 48 ms 3. To observe safe operating junction temperatures, low duty cycle pulse testing is used in tests where applicable. 4. Assuming ideal capacitor. Delay Time /C0043CDelay /C0032VDelay Threshold Charge ICharge /C0043CDelay /C00323.5 /C0032105 (typ) PACKAGE LEAD DESCRIPTION PACKAGE LEAD # SO−16WB TO−220
5 LEAD LEAD SYMBOL FUNCTION
1 1 VIN Unregulated supply voltage to IC. 16 5 VOUT Regulated 5.0 V output. 4, 5, 11, 12, 13 3 GND Ground Connection. 8 4 Delay Timing capacitor for RESET function. 6 2 RESET CMOS/TTL compatible output lead. RESET goes low whenever VOUT drops below 6.0% of it’s regulated value. 14 N/A VOUT(SENSE) Remote sensing of output voltage.
Figure 2. Quiescent Current vs. Input Voltage Figure 3. Quiescent Current vs. Input Figure 4. Output Voltage vs. Input Voltage Figure 5. VOUT vs. VIN Over RLOAD Figure 6. Line Regulation vs. Output Current Figure 7. Load Regulation vs. Output Current
100 VIN = 6−26 V
discharge circuit, and operates down to 1.0 V . (see Block Diagram on page 2). allowed by the RESET Delay circuit. current to ground (used to discharge the delay capacitor). Figure 13. Test & Application Circuit *CIN is required if regulator is far from the power source filter. **COUT is required for stability. into account to calculate the total variation in the delay time. delay, load transient response and loop stability. manufacturers data sheet usually provides this information. necessarily the optimized solution. design under steady state conditions. conditions for the regulator at low temperature.
http://onsemi.com Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Raise the temperature to the highest specified operating temperature. Vary the load current as instructed in step 5 to test for any oscillations. Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regulator performance. Most good quality aluminum electrolytic capacitors have a tolerance of ± 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above. CALCULATING POWER DISSIPATION IN A SINGLE OUTPUT LINEAR REGULATOR The maximum power dissipation for a single output regulator (Figure 14) is: PD(max) /C0043/C0458VIN(max) /C0042VOUT(min)/C0459IOUT(max) /C0041VIN(max)IQ (1) where: VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the application, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of P D(max) is known, the maximum permissible value of R/C0113JA can be calculated: R/C0113JA /C0043150°C /C0042TA PD (2) The value of R/C0113JA can then be compared with those in the package section of the data sheet. Those packages with R /C0113JA’s less than the calculated value in equation 2 will keep the die temperature below 150°C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. Figure 14. Single Output Regulator With Key A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of R/C0113JA. R/C0113JA /C0043R/C0113JC /C0041R/C0113CS /C0041R/C0113SA (3) where: R/C0113JC = the junction−to−case thermal resistance, R/C0113CS = the case−to−heatsink thermal resistance, and R/C0113SA = the heatsink−to−ambient thermal resistance. R/C0113JC appears in the package section of the data sheet. Like R/C0113JA, it too is a function of package type. R/C0113CS and R/C0113SA are functions of the package type, heatsink and the interface between them. These values appear in heat sink data sheets of heat sink manufacturers.
http://onsemi.com MARKING DIAGRAMS A = Assembly Location WL = Wafer Lot YY, Y = Year WW = Work Week G = Pb−Free Package TO−220 5−LEAD CS8129 AWLYYWWG SO−16 WB CS 8129 AWLYWWG CS8129 AWLYWWG CS 8129 AWLYWWG Device Package Shipping† CS8129YT5 TO−220* STRAIGHT
50 Units / Rail
CS8129YT5G TO−220* STRAIGHT (Pb−Free) CS8129YTHA5 TO−220* HORIZONTAL CS8129YTHA5G TO−220* HORIZONTAL (Pb−Free) CS8129YTVA5 TO−220* VERTICAL CS8129YTVA5G TO−220* VERTICAL (Pb−Free) CS8129YDW16 SO−16WB
47 Units / RailCS8129YDW16G SO−16WB
(Pb−Free) CS8129YDWR16 SO−16WB 1000 / Tape & ReelCS8129YDWR16G SO−16WB (Pb−Free) †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
http://onsemi.com PACKAGE DIMENSIONS TO−220 CASE 314D−04 ISSUE F −Q− 12345 U K D G A 5 PL J H L E C MQM0.356 (0.014) T SEATING PLANE−T− DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.572 0.613 14.529 15.570 B 0.390 0.415 9.906 10.541 C 0.170 0.180 4.318 4.572 D 0.025 0.038 0.635 0.965 E 0.048 0.055 1.219 1.397 G 0.067 BSC 1.702 BSC H 0.087 0.112 2.210 2.845 J 0.015 0.025 0.381 0.635 K 0.977 1.045 24.810 26.543 L 0.320 0.365 8.128 9.271 Q 0.140 0.153 3.556 3.886 U 0.105 0.117 2.667 2.972 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. B1 0.375 0.415 9.525 10.541 B DETAIL A−A B DETAIL A−A
http://onsemi.com PACKAGE DIMENSIONS TO−220 TVA SUFFIX CASE 314K−01 ISSUE O NOTES: /Em/figure1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. /Em/figure2. CONTROLLING DIMENSION: INCH. /Em/figure3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 10.92 (0.043) MAXIMUM. DIM MIN MAX MIN MAX MILLIMETERSINCHES A 0.560 0.590 14.22 14.99 B 0.385 0.415 9.78 10.54 C 0.160 0.190 4.06 4.83 D 0.027 0.037 0.69 0.94 E 0.045 0.055 1.14 1.40 F 0.530 0.545 13.46 13.84 G 0.067 BSC 1.70 BSC J 0.014 0.022 0.36 0.56 K 0.785 0.800 19.94 20.32 L 0.321 0.337 8.15 8.56 M 0.063 0.078 1.60 1.98 Q 0.146 0.156 3.71 3.96 S 0.146 0.196 3.71 4.98 U 0.460 0.475 11.68 12.07 W 55°° R 0.271 0.321 6.88 8.15 A U D G B TM0.356 (0.014) MQ 5 PL −Q− K F J C E −T− S L 12345 SEATING PLANE R M W TO−220 THA SUFFIX CASE 314A−03 ISSUE E NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION D DOES NOT INCLUDE INTERCONNECT BAR (DAMBAR) PROTRUSION. DIMENSION D INCLUDING PROTRUSION SHALL NOT EXCEED 0.043 (1.092) MAXIMUM. DIM A MIN MAX MIN MAX MILLIMETERS 0.572 0.613 14.529 15.570 INCHES B 0.390 0.415 9.906 10.541 C 0.170 0.180 4.318 4.572 D 0.025 0.038 0.635 0.965 E 0.048 0.055 1.219 1.397 F 0.570 0.585 14.478 14.859 G 0.067 BSC 1.702 BSC J 0.015 0.025 0.381 0.635 K 0.730 0.745 18.542 18.923 L 0.320 0.365 8.128 9.271 Q 0.140 0.153 3.556 3.886 S 0.210 0.260 5.334 6.604 U 0.468 0.505 11.888 12.827 −T− SEATING PLANE L S E C F K J OPTIONAL CHAMFER D5X MPM0.014 (0.356) T G AU B Q −P−
http://onsemi.com PACKAGE DIMENSIONS SO−16 WB CASE 751G−03 ISSUE C D 14X B16X SEATING PLANE SAM0.25 B ST 16 9 h X 45/C0095 MBM0.25 H8X E B A e T A L C /C0113 NOTES: 1. DIMENSIONS ARE IN MILLIMETERS. 2. INTERPRET DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 3. DIMENSIONS D AND E DO NOT INLCUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 5. DIMENSION B DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 TOTAL IN EXCESS OF THE B DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM MIN MAX MILLIMETERS A 2.35 2.65 A1 0.10 0.25 B 0.35 0.49 C 0.23 0.32 D 10.15 10.45 E 7.40 7.60 e 1.27 BSC H 10.05 10.55 h 0.25 0.75 L 0.50 0.90 q 0 7 /C0095/C0095 PACKAGE THERMAL DATA Parameter TO−220 FIVE LEAD SO−16WB Unit R/C0113JC Typical 2.1 23 °C/W R/C0113JA Typical 50 105 °C/W ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION N. American Technical Support: 800−282−9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81−3−5773−3850 CS8129/D SMART REGULATOR is a registered trademark of Semiconductor Components Industries, LLC (SCILLC). LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada Fax: 303−675−2176 or 800−344−3867 Toll Free USA/Canada Email: orderlit@onsemi.com ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative