CS8129

CS8129 CHERRY | Alldatasheet

Document overview

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Technical content

Features

n 5V +/- 3% Regulated Output n Low Dropout Voltage (0.6V @ 0.5A) n 750mA Output Current Capability n Reduced Threshold for use with 4V Micro- processors n Externally Programmed Delay n Fault Protection Reverse Battery 60V , -50V Peak Transient Voltage Short Circuit Thermal Shutdown RESET RESET Package Options

5 Lead TO-220

VOUT(SENSE) Gnd Gnd Gnd NC NC

Description

The CS8129 is a precision 5V linear reg- ulator capable of sourcing 750mA. The threshold voltage has been lowered to 4.2V so that the regulator can be used with 4V microprocessors. The lower threshold also per- mits operation under low battery condi- tions (5.5V plus a diode). The Õs delay time is externally programmed using a discrete RC network. During power up, or when the output goes out of regulation, remains in the low state for the duration of the delay. This function is independent of the input voltage and will function correct- ly as long as the output voltage remains at or above 1V. Hysteresis is included in the Delay and the comparators to improve noise immunity. A latching discharge circuit is used to discharge the delay capacitor when it is triggered by a brief fault condition. The regulator is protected against a variety of fault conditions: i.e. reverse battery, overvoltage, short circuit and thermal runaway conditions. The regu- lator is protected against voltage tran- sients ranging from -50V to +40V. Short circuit current is limited to 1.2A (typ). The CS8129 is packaged in a 5 lead TOÐ220 and a 16 lead surface mount package. RESET RESET RESET RESET RESET Block Diagram VOUT VIN Over Voltage Shutdown Pre- Regulator Regulated Supply for Circuit Bias Bandgap Reference Anti-Saturation and Current Limit Q R S Delay Gnd VOUTSENSE Error Amplifier Delay Comparator Latching Discharge Charge Current Generator RESET Thermal Shutdown VDISCHARGE CS8129 1V IN

3 Gnd

4 Delay

16 Lead SOIC Wide

A Company ¨ Rev. 3/31/99 Cherry Semiconductor Corporation

2000 South County Trail, East Greenwich, RI 02818

Tel: (401)885-3600 Fax: (401)885-5786 Email: info@cherry-semi.com Web Site: www.cherry-semi.com

• To observe safe operating junction temperatures, low duty cycle pulse testing is used in tests where applicable. Delay Time = = C Delay x 3.5 x 105 (typ) Note 1: assuming ideal capacitor CDelay x VDelay Threshold Charge I Charge Electrical Characteristics: -40ûC ² TA ² + 125ûC, -40ûC ² TJ ² +150ûC, 6V ² VIN ² 26V, 5mA ² IOUT ² 500mA, R = 4.7k½ to V OUT unless otherwise noted* RESET PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Absolute Maximum Ratings Lead Temperature Soldering CS8129 n Output Stage (VOUT) Output Voltage 4.85 5.00 5.15 V Dropout Voltage I OUT = 500mA 0.35 0.60 V Supply Current I OUT ² 10mA 2 7 mA IOUT ² 100mA 6 12 IOUT ² 500mA 55 100 Line Regulation 6V ² V IN ² 26V, IOUT = 50mA 5 50 mV Load Regulation 50mA ² I OUT ² 500mA, VIN = 14V 10 50 mV Ripple Rejection f = 120Hz, V IN = 7 to 17V, 54 75 dB IOUT = 250mA Current Limit 0.75 1.20 A Overvoltage Shutdown 32 40 V Reverse Polarity Input V OUT ³ -0.6V, 10½ Load -15 -30 V Voltage DC Thermal Shutdown Guaranteed by Design 150 180 210 ¡C n and Delay Functions Delay Charge Current V DELAY = 2V 5 10 15 µA Threshold V OUT Increasing, VRT(ON) 4.05 4.35 4.50 V VOUT Decreasing, VRT(OFF) 4.00 4.20 4.45 V Hysteresis V RH=VRT(ON) - VRT(OFF) 50 150 250 mV Delay Threshold Charge, V DC(HI) 3.25 3.50 3.75 V Discharge, VDC(LO) 2.85 3.10 3.35 V Delay Hysteresis 200 400 800 mV Output Voltage Low1V < VOUT < VRT(L) , 3k½ to VOUT 0.1 0.4 V Output Leakage V OUT > VRT(H) 01 0 µ A Current Delay Capacitor Discharge Latched ÒONÓ, 0.2 0.5 V Discharge Voltage V OUT > VRT Delay Time C DELAY = 0.1µF (Note 1) 16 32 48 ms RESET RESET RESET RESET RESET

Typical Performance Characteristics 0.0 0.0 ICQ (mA) VIN (V) 5.0 10.0 15.0 20.0 25.0 30.0 35.0 40.0 45.0 50.0 55.0 125ûC 25ûC -40ûC Rload = 25W 0.0 0.0 ICQ (mA) VIN (V) 20.0 40.0 60.0 80.0 100.0 120.0 Rload = 6.67W Rload = 10W Rload = 25W Rload = NO LOAD Room Temp. 0.0 0.0 VOUT (V) VIN (V) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Rload = 25W 125ûC 25ûC -40ûC Output Voltage vs Input Voltage over Temperature Quiescent Current vs Input Voltage over Load ResistanceQuiescent Current vs Input Voltage over Temperature 0.0 0.0 VOUT (V) VIN (V) 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 Rload = NO LOAD Rload = 6.67W Rload = 10W Room Temp. VOUT vs. VIN over RLOAD Package Lead Description PACKAGE LEAD # LEAD SYMBOL FUNCTION CS8129 -100 LINE REGULATION (mV) OUTPUT CURRENT (mA) -80 -60 -40 -20 100 100 200 300 400 500 600 700 800 VIN 6-26V TEMP = 25ûC TEMP = -40ûC TEMP = 125ûC -14 LOAD REGULATION (mV) OUTPUT CURRENT (mA) -12 -10 100 200 300 400 500 600 700 800 TEMP = 25ûC TEMP = 125ûC VIN = 14V TEMP = -40ûC Load Regulation vs. Output CurrentLine Regulation vs. Output Current Rload=25½ 16L SOIC Wide 5L TO-220 11 V IN Unregulated supply voltage to IC. 16 5 V OUT Regulated 5V output. 4, 5, 11, 12, 13 3 Gnd Ground connection. 8 4 Delay Timing capacitor for function. 6 2 CMOS/TTL compatible output lead. goes low whenev- er V OUT drops below 6% of it's regulated value. 14 N/A V OUT(SENSE) Remote sensing of output voltage. RESETRESET RESET

Test & Application Circuit CIN* 100nF VIN Delay Gnd RESET VOUT CS8129 COUT** 10mF to 100mF RRST 4.7kW Delay 0.1mF DROPOUT VOLTAGE (mV) OUTPUT CURRENT (mA) 100 200 300 400 500 600 700 800 100 200 300 400 500 600 700 800 900 25ûC -40ûC 125ûC QUIESCENT CURRENT (mA) OUTPUT CURRENT (mA) 100 100 200 300 400 500 600 700 800 VIN = 14V 125ûC 25ûC -40ûC 100 REJECTION (dB) FREQUENCY (Hz) 101 102 103 104 105 106 107 108 IOUT= 250mA COUT= 10mF, ESR = 10W COUT= 10mF, ESR = 1W COUT= 10mF, ESR = 1 & 0.1mF, ESR = 0 Ripple Rejection Quiescent Current vs. Output CurrentDropout Voltage vs. Output Current Typical Performance Characteristics Continued 100 ESR (ohms) Output Current (mA) 101 102 103 101 102 103 10-4 100 10-1 10-2 10-3 COUT= 68mF COUT= 47mF COUT= 47/68mF Stable Region Output Capacitor ESR *CIN required if regulator is far from the power source filter. **COUT required for stability.

The CS8129 function has hysteresis on both the reset and delay comparators, a latching Delay capacitor discharge circuit, and operates down to 1V. The circuit output is an open collector type with ON and OFF parameters as specified. The output NPN transistor is controlled by the two circuits described (see Block Diagram). This circuit monitors output voltage, and when output voltage is below the specified minimum causes the output transistor to be in the ON (saturation) state. When the output voltage is above the specified level, this circuit permits the output transistor to go into the OFF state if allowed by the Delay circuit. This circuit provides a programmable (by external capaci- tor) delay on the output lead. The Delay lead pro- vides source current to the external delay capacitor only when the "Low Voltage Inhibit" circuit indicates that out- put voltage is above V RT(ON). Otherwise, the Delay lead sinks current to ground (used to discharge the delay capacitor). The discharge current is latched ON when the output voltage is below V RT(OFF). The Delay capacitor is fully discharged anytime the output voltage falls out of regulation, even for a short period of time. This feature ensures a controlled pulse is generated following detection of an error condition. The circuit allows the output transistor to go to the OFF (open) state only when the voltage on the Delay lead is higher than V DC(HI). The Delay time for the function is calculated from the formula: Delay time = Delay time = CDelay(µF) x 3.2 x 10 5 If CDelay=0.1µF, Delay time (ms)=32ms ± 50%: i.e. 16ms to 48ms. The tolerance of the capacitor must be taken into account to calculate the total variation in the delay time. C Delay x VDelay Threshold ICharge RESET RESET RESET RESET Reset Delay Circuit RESET RESET RESET Low Voltage Inhibit Circuit RESET RESET RESET (1) (2)(3) (2) Delay VOUT VRT(ON) VRT(OFF) VRH VDC(HI) VDC(LO) VDH tDelay VDIS VRL RESET (1) = No Delay Capacitor (2) = With Delay Capacitor (3) = Max: Voltage (1.0V) RESET Circuit WaveformRESET Circuit Functional DescriptionRESET CS8129

The output or compensation capacitor helps determine three main characteristics of a linear regulator: start-up delay, load transient response and loop stability. The capacitor value and type should be based on cost, availability, size and temperature constraints. A tantalum or aluminum electrolytic capacitor is best, since a film or ceramic capacitor with almost zero ESR can cause instabil- ity. The aluminum electrolytic capacitor is the least expen- sive solution, but, if the circuit operates at low tempera- tures (-25¡C to -40¡C), both the value and ESR of the least expensive will vary considerably. The capacitor manufac- turers data sheet usually provides this information. The value for the output capacitor C OUT shown in the test and applications circuit should work for most applica- tions, however it is not necessarily the optimized solution. To determine an acceptable value for C OUT for a particular application, start with a tantalum capacitor of the recom- mended value and work towards a less expensive alterna- tive part. Step 1: Place the completed circuit with a tantalum capac- itor of the recommended value in an environmental cham- ber at the lowest specified operating temperature and monitor the outputs with an oscilloscope. A decade box connected in series with the capacitor will simulate the higher ESR of an aluminum capacitor. Leave the decade box outside the chamber, the small resistance added by the longer leads is negligible. Step 2: With the input voltage at its maximum value, increase the load current slowly from zero to full load while observing the output for any oscillations. If no oscil- lations are observed, the capacitor is large enough to ensure a stable design under steady state conditions. Step 3: Increase the ESR of the capacitor from zero using the decade box and vary the load current until oscillations appear. Record the values of load current and ESR that cause the greatest oscillation. This represents the worst case load conditions for the regulator at low temperature. Step 4: Maintain the worst case load conditions set in step 3 and vary the input voltage until the oscillations increase. This point represents the worst case input voltage condi- tions. Step 5: If the capacitor is adequate, repeat steps 3 and 4 with the next smaller valued capacitor. A smaller capaci- tor will usually cost less and occupy less board space. If the output oscillates within the range of expected operat- ing conditions, repeat steps 3 and 4 with the next larger standard capacitor value. Step 6: Test the load transient response by switching in various loads at several frequencies to simulate its real working environment. Vary the ESR to reduce ringing. Step 7: Remove the unit from the environmental chamber and heat the IC with a heat gun. Vary the load current as instructed in step 5 to test for any oscillations. Once the minimum capacitor value with the maximum ESR is found, a safety factor should be added to allow for the tolerance of the capacitor and any variations in regula- tor performance. Most good quality aluminum electrolytic capacitors have a tolerance of +/- 20% so the minimum value found should be increased by at least 50% to allow for this tolerance plus the variation which will occur at low temperatures. The ESR of the capacitor should be less than 50% of the maximum allowable ESR found in step 3 above. The maximum power dissipation for a single output regu- lator (Figure 1) is: P D(max)={VIN(max)ÐVOUT(min)}IOUT(max)+VIN(max)IQ (1) where VIN(max) is the maximum input voltage, VOUT(min) is the minimum output voltage, IOUT(max) is the maximum output current for the applica- tion, and IQ is the quiescent current the regulator consumes at IOUT(max). Once the value of PD(max) is known, the maximum permis- sible value of RQJA can be calculated: RQJA = (2) The value of RQJA can then be compared with those in the package section of the data sheet. Those packages with R QJA's less than the calculated value in equation 2 will keep the die temperature below 150¡C. In some cases, none of the packages will be sufficient to dissipate the heat generated by the IC, and an external heatsink will be required. 150¡C - T A PD VIN Smart Regulator VOUT IOUT IIN IQ Control Figure 1: Single output regulator with key performance parameters labeled. Stability Considerations Calculating Power Dissipation in a Single Output Linear Regulator

Application Notes: continued CS8129 A heat sink effectively increases the surface area of the package to improve the flow of heat away from the IC and into the surrounding air. Each material in the heat flow path between the IC and the outside environment will have a thermal resistance. Like series electrical resistances, these resistances are summed to determine the value of R QJA. RQJA = RQJC + RQCS + RQSA (3) where RQJC = the junctionÐtoÐcase thermal resistance, RQCS = the caseÐtoÐheatsink thermal resistance, and RQSA = the heatsinkÐtoÐambient thermal resistance. RQJC appears in the package section of the data sheet. Like RQJA, it too is a function of package type. RQCS and RQSA are functions of the package type, heatsink and the inter- face between them. These values appear in heat sink data sheets of heat sink manufacturers. Heat Sinks

CS8129YDW16 16 Lead SOIC Wide CS8129YDWR16 16 Lead SOIC Wide (tape & reel) CS8129YT5 5 Lead TO-220 Straight CS8129YTHA5 5 Lead TO-220 Horizontal CS8129YTVA5 5 Lead TO-220 Vertical Rev. 3/31/99

Ordering Information

D Lead Count Metric English Max Min Max Min 16 L SOIC Wide 10.50 10.10 .413 .398 Thermal Data 16 Lead 5 Lead SOIC Wide TO-220 RQJC typ 23 2.1 ûC/W RQJA typ 105 50 ûC/W Package Specification PACKAGE THERMAL DATAPACKAGE DIMENSIONS IN mm (INCHES) © 1999 Cherry Semiconductor Corporation Cherry Semiconductor Corporation reserves the right to make changes to the specifications without notice. Please contact Cherry Semiconductor Corporation for the latest available information. Surface Mount Wide Body (DW); 300 mil wide 1.27 (.050) BSC 7.60 (.299) 7.40 (.291) 10.65 (.419) 10.00 (.394) D 0.32 (.013) 0.23 (.009) 1.27 (.050) 0.40 (.016) REF: JEDEC MS-013 2.49 (.098) 2.24 (.088) 0.51 (.020) 0.33 (.013) 2.65 (.104) 0.10 (.004)

5 Lead TO-220 (T) Straight

2.87 (.113) 2.62 (.103) 6.93(.273) 6.68(.263) 9.78 (.385) 10.54 (.415) 1.02(.040) 0.63(.025) 1.83(.072) 1.57(.062) 0.56 (.022) 0.36 (.014) 2.92 (.115) 2.29 (.090) 1.40 (.055) 4.06 (.160) 6.55 (.258) 5.94 (.234) 14.22 (.560) 0.76 (.030) 3.71 (.146) 3.96 (.156) 14.99 (.590) 14.22 (.560)

5 Lead TO-220 (TVA) Vertical

1.68 7.51 (.296) 1.78 (.070) 4.34 (.171) 0.56 (.022) 0.36 (.014) 1.40 (.055) 1.14 (.045) 4.83 (.190) 4.06 (.160) 14.99 (.590) 14.22 (.560) 2.92 (.115) 2.29 (.090) .94 (.037) .69 (.027) 8.64 (.340) 7.87 (.310) 6.80 (.268) 10.54 (.415) 9.78 (.385) 2.87 (.113) 2.62 (.103) 6.55 (.258) 5.94 (.234) 3.96 (.156) 3.71 (.146)

5 Lead TO-220 (THA) Horizontal

0.81(.032) 1.70 (.067) 6.81(.268) 1.40 (.055) 1.14 (.045) 5.84 (.230) 6.60 (.260) 6.83 (.269) 0.56 (.022) 0.36 (.014) 10.54 (.415) 9.78 (.385) 6.55 (.258) 5.94 (.234) 3.96 (.156) 3.71 (.146) 1.68 (.066) TYP 14.99 (.590) 14.22 (.560) 2.77 (.109) 2.29 (.090) 2.92 (.115) 4.83 (.190) 4.06 (.160) 2.87 (.113) 2.62 (.103)